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boards: mimxrt1020_evk: Enable mcux ethernet driver and pins

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Enables the mcux ethernet driver and pin muxes on the mimxrt1020_evk
board, the same way it is done on the mimxrt1050_evk board. Updates the
board documentation and yaml supported list accordingly.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Aurelien Jarno 2019-01-20 21:14:08 +01:00 • committed by Maureen Helm
commit 0e7a6ec9ab
5 changed files with 112 additions and 0 deletions
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61
boards/arm/mimxrt1020_evk/pinmux.c
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@ -6,6 +6,15 @@
#include <init.h>
#include <fsl_iomuxc.h>
#include <fsl_gpio.h>
#ifdef CONFIG_ETH_MCUX_0
static gpio_pin_config_t enet_gpio_config = {
.direction = kGPIO_DigitalOutput,
.outputLogic = 0,
.interruptMode = kGPIO_NoIntmode
};
#endif
static int mimxrt1020_evk_init(struct device *dev)
{
@ -57,7 +66,59 @@ static int mimxrt1020_evk_init(struct device *dev)
IOMUXC_SW_PAD_CTL_PAD_DSE(6));
#endif
#ifdef CONFIG_ETH_MCUX_0
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0U);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 1);
IOMUXC_SetPinMux(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_41_ENET_MDC, 0);
IOMUXC_SetPinMux(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_04_GPIO1_IO04, 0xB0A9u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B1_06_GPIO1_IO22, 0xB0A9u);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_10_ENET_RDATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_09_ENET_RDATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_11_ENET_RX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_14_ENET_TDATA00, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_15_ENET_TDATA01, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_13_ENET_TX_EN, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_08_ENET_REF_CLK1, 0x31);
IOMUXC_SetPinConfig(IOMUXC_GPIO_AD_B0_12_ENET_RX_ER, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_41_ENET_MDC, 0xB0E9);
IOMUXC_SetPinConfig(IOMUXC_GPIO_EMC_40_ENET_MDIO, 0xB829);
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
/* Initialize ENET_INT GPIO */
GPIO_PinInit(GPIO1, 4, &enet_gpio_config);
GPIO_PinInit(GPIO1, 22, &enet_gpio_config);
/* pull up the ENET_INT before RESET. */
GPIO_WritePinOutput(GPIO1, 22, 1);
GPIO_WritePinOutput(GPIO1, 4, 0);
#endif
return 0;
}
#ifdef CONFIG_ETH_MCUX_0
static int mimxrt1020_evk_phy_reset(struct device *dev)
{
/* RESET PHY chip. */
k_busy_wait(10*USEC_PER_MSEC);
GPIO_WritePinOutput(GPIO1, 4, 1);
return 0;
}
#endif
SYS_INIT(mimxrt1020_evk_init, PRE_KERNEL_1, 0);
#ifdef CONFIG_ETH_MCUX_0
SYS_INIT(mimxrt1020_evk_phy_reset, PRE_KERNEL_2, 0);
#endif