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drivers: ITE: Use generic name instead of specific chip name

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Use generic name for structure in driver instead of specific chip name
for better compatibility.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2025-03-21 11:21:58 +08:00 • committed by Benjamin Cabé
commit 0e5218cbcc
3 changed files with 26 additions and 18 deletions
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25
drivers/flash/flash_ite_it8xxx2.c
View file

@ -25,8 +25,7 @@
#include <zephyr/logging/log.h> #include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(flash_ite_it8xxx2); LOG_MODULE_REGISTER(flash_ite_it8xxx2);
#define FLASH_IT8XXX2_REG_BASE \ #define FLASH_ITE_EC_REGS_BASE ((struct smfi_ite_ec_regs *)DT_INST_REG_ADDR(0))
((struct smfi_it8xxx2_regs *)DT_INST_REG_ADDR(0))
struct flash_it8xxx2_dev_data { struct flash_it8xxx2_dev_data {
struct k_sem sem; struct k_sem sem;
@ -93,7 +92,7 @@ static const struct flash_parameters flash_it8xxx2_parameters = {
void __soc_ram_code ramcode_reset_i_cache(void) void __soc_ram_code ramcode_reset_i_cache(void)
{ {
struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE; struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
/* I-Cache tag sram reset */ /* I-Cache tag sram reset */
gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET; gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET;
@ -106,7 +105,7 @@ void __soc_ram_code ramcode_reset_i_cache(void)
void __soc_ram_code ramcode_flash_follow_mode(void) void __soc_ram_code ramcode_flash_follow_mode(void)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
/* /*
* ECINDAR3-0 are EC-indirect memory address registers. * ECINDAR3-0 are EC-indirect memory address registers.
* *
@ -127,7 +126,7 @@ void __soc_ram_code ramcode_flash_follow_mode(void)
void __soc_ram_code ramcode_flash_follow_mode_exit(void) void __soc_ram_code ramcode_flash_follow_mode_exit(void)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
/* Exit follow mode, and keep the setting of selecting internal flash */ /* Exit follow mode, and keep the setting of selecting internal flash */
flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH; flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
@ -136,8 +135,8 @@ void __soc_ram_code ramcode_flash_follow_mode_exit(void)
void __soc_ram_code ramcode_flash_fsce_high(void) void __soc_ram_code ramcode_flash_fsce_high(void)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE; struct gctrl_ite_ec_regs *const gctrl_regs = GCTRL_ITE_EC_REGS_BASE;
/* FSCE# high level */ /* FSCE# high level */
flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0); flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0);
@ -160,7 +159,7 @@ void __soc_ram_code ramcode_flash_fsce_high(void)
void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata) void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
/* Write data to FMOSI */ /* Write data to FMOSI */
flash_regs->SMFI_ECINDDR = wdata; flash_regs->SMFI_ECINDDR = wdata;
@ -169,7 +168,7 @@ void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata)
void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen, uint8_t *rbuf, void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen, uint8_t *rbuf,
enum flash_transaction_cmd cmd_end) enum flash_transaction_cmd cmd_end)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
int i; int i;
/* FSCE# with low level */ /* FSCE# with low level */
@ -191,7 +190,7 @@ void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen,
void __soc_ram_code ramcode_flash_cmd_read_status(enum flash_status_mask mask, void __soc_ram_code ramcode_flash_cmd_read_status(enum flash_status_mask mask,
enum flash_status_mask target) enum flash_status_mask target)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
uint8_t cmd_rs[] = {FLASH_CMD_RS}; uint8_t cmd_rs[] = {FLASH_CMD_RS};
/* Send read status command */ /* Send read status command */
@ -343,7 +342,7 @@ void __soc_ram_code ramcode_flash_erase(int addr, int cmd)
static int __soc_ram_code flash_it8xxx2_read(const struct device *dev, off_t offset, void *data, static int __soc_ram_code flash_it8xxx2_read(const struct device *dev, off_t offset, void *data,
size_t len) size_t len)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
uint8_t *data_t = data; uint8_t *data_t = data;
int i; int i;
@ -464,7 +463,7 @@ flash_it8xxx2_get_parameters(const struct device *dev)
static int flash_it8xxx2_init(const struct device *dev) static int flash_it8xxx2_init(const struct device *dev)
{ {
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE; struct smfi_ite_ec_regs *const flash_regs = FLASH_ITE_EC_REGS_BASE;
struct flash_it8xxx2_dev_data *data = dev->data; struct flash_it8xxx2_dev_data *data = dev->data;
/* By default, select internal flash for indirect fast read. */ /* By default, select internal flash for indirect fast read. */
@ -475,7 +474,7 @@ static int flash_it8xxx2_init(const struct device *dev)
* than 256K-byte, enable the page program cycle constructed * than 256K-byte, enable the page program cycle constructed
* by EC-Indirect Follow Mode. * by EC-Indirect Follow Mode.
*/ */
flash_regs->SMFI_FLHCTRL6R |= IT8XXX2_SMFI_MASK_ECINDPP; flash_regs->SMFI_FLHCTRL6R |= ITE_EC_SMFI_MASK_ECINDPP;
/* Initialize mutex for flash controller */ /* Initialize mutex for flash controller */
k_sem_init(&data->sem, 1, 1); k_sem_init(&data->sem, 1, 1);

6
drivers/pinctrl/pinctrl_ite_it8xxx2.c
View file

@ -14,8 +14,6 @@
LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR); LOG_MODULE_REGISTER(pinctrl_ite_it8xxx2, LOG_LEVEL_ERR);
#define GPIO_IT8XXX2_REG_BASE \
((struct gpio_it8xxx2_regs *)DT_REG_ADDR(DT_NODELABEL(gpiogcr)))
#define GPIO_GROUP_MEMBERS 8 #define GPIO_GROUP_MEMBERS 8
struct pinctrl_it8xxx2_gpio { struct pinctrl_it8xxx2_gpio {
@ -356,14 +354,14 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
static int pinctrl_it8xxx2_init(const struct device *dev) static int pinctrl_it8xxx2_init(const struct device *dev)
{ {
struct gpio_it8xxx2_regs *const gpio_base = GPIO_IT8XXX2_REG_BASE; struct gpio_ite_ec_regs *const gpio_base = GPIO_ITE_EC_REGS_BASE;
/* /*
* The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR. * The default value of LPCRSTEN is bit2:1 = 10b(GPD2) in GCR.
* If LPC reset is enabled on GPB7, we have to clear bit2:1 * If LPC reset is enabled on GPB7, we have to clear bit2:1
* to 00b. * to 00b.
*/ */
gpio_base->GPIO_GCR &= ~IT8XXX2_GPIO_LPCRSTEN; gpio_base->GPIO_GCR &= ~ITE_EC_GPIO_LPCRSTEN;
#ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2 #ifdef CONFIG_SOC_IT8XXX2_REG_SET_V2
#if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c5)) #if defined(CONFIG_I2C_ITE_ENHANCE) && DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(i2c5))

13
soc/ite/ec/it8xxx2/chip_chipregs.h
View file

@ -907,6 +907,7 @@ struct smfi_it8xxx2_regs {
#define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6) #define EC_INDIRECT_READ_INTERNAL_FLASH BIT(6)
/* Enable EC-indirect page program command */ /* Enable EC-indirect page program command */
#define IT8XXX2_SMFI_MASK_ECINDPP BIT(3) #define IT8XXX2_SMFI_MASK_ECINDPP BIT(3)
#define ITE_EC_SMFI_MASK_ECINDPP IT8XXX2_SMFI_MASK_ECINDPP
/* Scratch SRAM 0 address(BIT(19)) */ /* Scratch SRAM 0 address(BIT(19)) */
#define IT8XXX2_SMFI_SC0A19 BIT(7) #define IT8XXX2_SMFI_SC0A19 BIT(7)
/* Scratch SRAM enable */ /* Scratch SRAM enable */
@ -1089,6 +1090,7 @@ struct gpio_it8xxx2_regs {
/* GPIO register fields */ /* GPIO register fields */
/* 0x00: General Control */ /* 0x00: General Control */
#define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1)) #define IT8XXX2_GPIO_LPCRSTEN (BIT(2) | BIT(1))
#define ITE_EC_GPIO_LPCRSTEN IT8XXX2_GPIO_LPCRSTEN
#define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2 #define IT8XXX2_GPIO_GCR_ESPI_RST_D2 0x2
#define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1 #define IT8XXX2_GPIO_GCR_ESPI_RST_POS 1
#define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS) #define IT8XXX2_GPIO_GCR_ESPI_RST_EN_MASK (0x3 << IT8XXX2_GPIO_GCR_ESPI_RST_POS)
@ -1455,7 +1457,7 @@ enum chip_pll_mode {
#define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4) #define IT8XXX2_I2C_EM_DEV1_IRQ BIT(4)
/* /*
* TODO: use gctrl_it8xxx2_regs instead of following register declarations * TODO: use gctrl_ite_ec_regs instead of following register declarations
* to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c. * to fix in cros_flash_it8xxx2.c, cros_shi_it8xxx2.c and tcpm\it8xxx2.c.
*/ */
/* --- General Control (GCTRL) --- */ /* --- General Control (GCTRL) --- */
@ -2253,4 +2255,13 @@ struct spisc_it8xxx2_regs {
/* 0x27: Rx Valid Length Interrupt Status */ /* 0x27: Rx Valid Length Interrupt Status */
#define IT8XXX2_SPISC_RVLI BIT(0) #define IT8XXX2_SPISC_RVLI BIT(0)
/* Alias gpio_ite_ec_regs to gpio_it8xxx2_regs for compatibility */
#define gpio_ite_ec_regs gpio_it8xxx2_regs
#define GPIO_ITE_EC_REGS_BASE GPIO_IT8XXX2_REG_BASE
/* Alias smfi_ite_ec_regs to smfi_it8xxx2_regs for compatibility */
#define smfi_ite_ec_regs smfi_it8xxx2_regs
/* Alias gctrl_ite_ec_regs to gctrl_it8xxx2_regs for compatibility */
#define gctrl_ite_ec_regs gctrl_it8xxx2_regs
#define GCTRL_ITE_EC_REGS_BASE GCTRL_IT8XXX2_REGS_BASE
#endif /* CHIP_CHIPREGS_H */ #endif /* CHIP_CHIPREGS_H */