arch: arc: enable divide zero exception
STATUS32.DZ(bit 13) is the EV_DivZero exception enable bit, and it's not enabled by default. we need to set it explicitly to enable divide zero exception on early boot and each thread's setup. The DZ bit is ignored on write and read as zero when there is no hardware division configured. So we can simply set DZ bit even if there is no hardware division configured. Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
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3 changed files with 8 additions and 3 deletions
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@ -83,6 +83,10 @@ SECTION_FUNC(TEXT,__start)
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sr r0, [_ARC_V2_IRQ_VECT_BASE]
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#endif
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_DZ_BIT
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kflag r0
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#if defined(CONFIG_USERSPACE)
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lr r0, [_ARC_V2_STATUS32]
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bset r0, r0, _ARC_V2_STATUS32_US_BIT
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@ -150,14 +150,14 @@ void arch_new_thread(struct k_thread *thread, k_thread_stack_t *stack,
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* level/mask can't be set from user space that's not worse than
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* executing a loop without yielding.
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*/
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iframe->status32 = _ARC_V2_STATUS32_US;
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iframe->status32 = _ARC_V2_STATUS32_US | _ARC_V2_STATUS32_DZ;
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if (is_user(thread)) {
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iframe->pc = (uint32_t)z_user_thread_entry_wrapper;
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} else {
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iframe->pc = (uint32_t)z_thread_entry_wrapper;
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}
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#else
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iframe->status32 = 0;
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iframe->status32 = _ARC_V2_STATUS32_DZ;
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iframe->pc = ((uint32_t)z_thread_entry_wrapper);
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#endif /* CONFIG_USERSPACE */
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#ifdef CONFIG_ARC_SECURE_FIRMWARE
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@ -132,7 +132,8 @@
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#define _ARC_V2_STATUS32_N (1 << 10)
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#define _ARC_V2_STATUS32_Z (1 << 11)
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#define _ARC_V2_STATUS32_L (1 << 12)
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#define _ARC_V2_STATUS32_DZ (1 << 13)
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#define _ARC_V2_STATUS32_DZ_BIT 13
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#define _ARC_V2_STATUS32_DZ (1 << _ARC_V2_STATUS32_DZ_BIT)
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#define _ARC_V2_STATUS32_SC_BIT 14
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#define _ARC_V2_STATUS32_SC (1 << _ARC_V2_STATUS32_SC_BIT)
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#define _ARC_V2_STATUS32_ES (1 << 15)
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