From 0d84e7b2bc72b1bcc10ad49657207115751cb1d1 Mon Sep 17 00:00:00 2001 From: Francois Ramu Date: Fri, 26 Nov 2021 14:16:32 +0100 Subject: [PATCH] drivers: watchdog: stm32H7 window watchdog during debug This commit is controlling the WWDG during the Stop mode in debug. WWDG1 is frozen while the core is in Debug mode, setting the bit of the DBGMCU APB3 peripheral freeze register (DBGMCU_APB3FZ1) for the stm32H7 soc devices. Signed-off-by: Francois Ramu --- drivers/watchdog/wdt_wwdg_stm32.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/watchdog/wdt_wwdg_stm32.c b/drivers/watchdog/wdt_wwdg_stm32.c index c88fef25a0d..61d55a3933a 100644 --- a/drivers/watchdog/wdt_wwdg_stm32.c +++ b/drivers/watchdog/wdt_wwdg_stm32.c @@ -169,7 +169,11 @@ static int wwdg_stm32_setup(const struct device *dev, uint8_t options) #elif defined(CONFIG_SOC_SERIES_STM32L0X) LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU); #endif +#if defined(CONFIG_SOC_SERIES_STM32H7X) + LL_DBGMCU_APB3_GRP1_FreezePeriph(LL_DBGMCU_APB3_GRP1_WWDG1_STOP); +#else LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_WWDG_STOP); +#endif /* CONFIG_SOC_SERIES_STM32H7X */ } if (options & WDT_OPT_PAUSE_IN_SLEEP) {