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drivers: watchdog: atmel: Introduce sam4l wdt

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Introduce sam4l watchdog configuration. This entry is necessary to
select proper watchdog configuration at board init due to #83429.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This commit is contained in:
Gerson Fernando Budke 2024-12-28 16:25:02 +01:00 • committed by Benjamin Cabé
commit 0cf7fd1023
6 changed files with 365 additions and 37 deletions
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36
soc/atmel/sam/sam4l/soc.c
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@ -16,33 +16,6 @@
#include <soc.h>
#include <zephyr/sys/util.h>
/** Watchdog control register first write keys */
#define WDT_FIRST_KEY 0x55ul
/** Watchdog control register second write keys */
#define WDT_SECOND_KEY 0xAAul
/**
* @brief Sets the WatchDog Timer Control register to the \a ctrl value thanks
* to the WatchDog Timer key.
*
* @param ctrl Value to set the WatchDog Timer Control register to.
*/
static ALWAYS_INLINE void wdt_set_ctrl(uint32_t ctrl)
{
volatile uint32_t dly;
/** Calculate delay for internal synchronization
* see 45.1.3 WDT errata
*/
dly = DIV_ROUND_UP(48000000 * 2, 115000);
dly >>= 3; /* ~8 cycles for one while loop */
while (dly--) {
;
}
WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_FIRST_KEY);
WDT->CTRL = ctrl | WDT_CTRL_KEY(WDT_SECOND_KEY);
}
#define XTAL_FREQ 12000000
#define NR_PLLS 1
#define PLL_MAX_STARTUP_CYCLES (SCIF_PLL_PLLCOUNT_Msk >> SCIF_PLL_PLLCOUNT_Pos)
@ -255,13 +228,6 @@ static ALWAYS_INLINE void clock_init(void)
void soc_reset_hook(void)
{
#if defined(CONFIG_WDT_DISABLE_AT_BOOT)
wdt_set_ctrl(WDT->CTRL & ~WDT_CTRL_EN);
while (WDT->CTRL & WDT_CTRL_EN) {
;
}
#endif
/* Setup system clocks. */
clock_init();
}

5
soc/atmel/sam/sam4l/soc.h
View file

@ -1,5 +1,5 @@
/*
* Copyright (c) 2020-2024 Gerson Fernando Budke <nandojve@gmail.com>
* Copyright (c) 2020-2025 Gerson Fernando Budke <nandojve@gmail.com>
* SPDX-License-Identifier: Apache-2.0
*/
@ -66,6 +66,9 @@
/** Master Clock (MCK) Frequency */
#define SOC_ATMEL_SAM_MCK_FREQ_HZ SOC_ATMEL_SAM_HCLK_FREQ_HZ
#define SOC_ATMEL_SAM_RCSYS_NOMINAL_HZ 115000
#define SOC_ATMEL_SAM_RC32K_NOMINAL_HZ 32768
/** Oscillator identifiers
* External Oscillator 0
* External 32 kHz oscillator