diff --git a/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig new file mode 100644 index 00000000000..8e5ecbe7ff2 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.defconfig @@ -0,0 +1,11 @@ +# YD-STM32H750VB board configuration + +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +if BOARD_YD_STM32H750VB + +config DISK_DRIVER_SDMMC + default y if DISK_DRIVERS + +endif # BOARD_YD_STM32H750VB diff --git a/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb new file mode 100644 index 00000000000..14b5ebe4648 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/Kconfig.yd_stm32h750vb @@ -0,0 +1,7 @@ +# YD-STM32H750VB board configuration + +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_YD_STM32H750VB + select SOC_STM32H750XX diff --git a/boards/vcc-gnd/yd_stm32h750vb/board.cmake b/boards/vcc-gnd/yd_stm32h750vb/board.cmake new file mode 100644 index 00000000000..2cf1e034d59 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/board.cmake @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_runner_args(dfu-util "--pid=0483:df11" "--alt=0" "--dfuse") +board_runner_args(jlink "--device=STM32H735IG" "--speed=4000") +board_runner_args(openocd --target-handle=_CHIPNAME.cpu0) +board_runner_args(stm32cubeprogrammer "--port=swd" "--reset-mode=hw") + +include(${ZEPHYR_BASE}/boards/common/stm32cubeprogrammer.board.cmake) +include(${ZEPHYR_BASE}/boards/common/dfu-util.board.cmake) +include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake) +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) diff --git a/boards/vcc-gnd/yd_stm32h750vb/board.yml b/boards/vcc-gnd/yd_stm32h750vb/board.yml new file mode 100644 index 00000000000..f26fffaa901 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/board.yml @@ -0,0 +1,5 @@ +board: + name: yd_stm32h750vb + vendor: vcc-gnd + socs: + - name: stm32h750xx diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png b/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png new file mode 100644 index 00000000000..814f26a1099 Binary files /dev/null and b/boards/vcc-gnd/yd_stm32h750vb/doc/img/yd_stm32h750vb.png differ diff --git a/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst new file mode 100644 index 00000000000..5a5775cae1f --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/doc/index.rst @@ -0,0 +1,133 @@ +.. _yd_stm32h750vb: + +YD-STM32H750VB +############## + +Overview +******** + +The YD-STM32H750VB development board is a complete demonstration and development +platform for Arm |reg| Cortex |reg|-M7 core-based STM32H750VBT6 microcontroller, with +128Kbytes of Flash memory and 1 Mbytes of SRAM. + +.. image:: img/yd_stm32h750vb.png + :align: center + :alt: YD-STM32H750VB + +More information about STM32H750 can be found here: + +- `STM32H750 on www.st.com`_ +- `STM32H750xx reference manual`_ +- `STM32H750xx datasheet`_ + +Supported Features +================== + +The current Zephyr YD-STM32H750VB board supports the following features: + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| CLOCK | on-chip | reset and clock control | ++-----------+------------+-------------------------------------+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| PINMUX | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ + +Other hardware features are not yet supported on Zephyr porting. + +The default configuration can be found in the defconfig file: +:zephyr_file:`boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig` + +Pin Mapping +=========== + +Default Zephyr Peripheral Mapping: +---------------------------------- + +- UART_1_TX : PA9 +- UART_1_RX : PA10 +- LED_1 : PA13 (SWDIO) +- LED_2 : PA14 (SWCLK) +- LED_3 : PA15 +- LED_4 : PB4 +- KEY : PB3 + +System Clock +============ + +The STM32H750VB System Clock can be driven by an internal or external oscillator, +as well as by the main PLL clock. By default, the System clock +is driven by the PLL clock at 480MHz. PLL clock is feed by a 25MHz high speed external clock. + +Flashing +======== + +There are 2 main entry points for flashing STM32H750VB SoCs, one using the ROM +bootloader, and another by using the SWD debug port (which requires additional +hardware such as ST-Link). Flashing using the ROM bootloader requires a special activation +pattern, which can be triggered by using the BOOT0 button. + +Installing dfu-util +------------------- + +It is recommended to use at least v0.8 of `dfu-util`_. The package available in +debian/ubuntu can be quite old, so you might have to build dfu-util from source. + +There is also a Windows version which works, but you may have to install the +right USB drivers with a tool like `Zadig`_. + +Flashing an application to YD-STM32H750VB +----------------------------------------- + +Connect a USB-C cable and the board should power ON. Force the board into DFU mode +by keeping the BOOT0 switch pressed while pressing and releasing the RST switch. + +The dfu-util runner is supported on this board and so a sample can be built and +tested easily. + +Here is an example for the :zephyr:code-sample:`blinky` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/basic/blinky + :board: yd_stm32h750vb + :goals: build flash + +You will see the LED blinking every second. + +Debugging +========= + +You can debug an application in the usual way. Here is an example for the +:ref:`hello_world` application. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: yd_stm32h750vb + :goals: debug + +References +********** + +.. target-notes:: + +.. _Zadig: + https://zadig.akeo.ie/ + +.. _dfu-util: + http://dfu-util.sourceforge.net/build.html + +.. _STM32H750 on www.st.com: + https://www.st.com/en/microcontrollers-microprocessors/stm32h750-value-line.html + +.. _STM32H750xx reference manual: + https://www.st.com/resource/en/reference_manual/rm0433-stm32h742-stm32h743753-and-stm32h750-value-line-advanced-armbased-32bit-mcus-stmicroelectronics.pdf + +.. _STM32H750xx datasheet: + https://www.st.com/resource/en/datasheet/stm32h750vb.pdf diff --git a/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg b/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg new file mode 100644 index 00000000000..f7674378361 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/support/openocd.cfg @@ -0,0 +1,30 @@ +source [find interface/stlink-dap.cfg] +transport select dapdirect_swd + +set WORKAREASIZE 0x2000 +set CHIPNAME STM23H750VB +set BOARDNAME YD_STM23H750VB + +source [find target/stm32h7x.cfg] + +# Use connect_assert_srst here to be able to program +# even when core is in sleep mode +reset_config srst_only srst_nogate connect_assert_srst + +$_CHIPNAME.cpu0 configure -event gdb-attach { + echo "Debugger attaching: halting execution" + gdb_breakpoint_override hard +} + +$_CHIPNAME.cpu0 configure -event gdb-detach { + echo "Debugger detaching: resuming execution" + resume +} + +# Due to the use of connect_assert_srst, running gdb requires +# to reset halt just after openocd init. +rename init old_init +proc init {} { + old_init + reset halt +} diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts new file mode 100644 index 00000000000..926f1f56454 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.dts @@ -0,0 +1,134 @@ +/* + * Copyright(c) 2024 John Sanpe + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; +#include +#include +#include + +/ { + model = "VCC-GND Studio STM32H750VB"; + compatible = "st,stm32h750vb"; + + aliases { + led0 = &yellow_led; + led1 = &blue_led; + sw0 = &user_button; + spi-flash0 = &w25q128jv; + }; + + chosen { + zephyr,console = &usart1; + zephyr,shell-uart = &usart1; + zephyr,sram = &sram0; + zephyr,flash = &flash0; + zephyr,flash-controller = &w25q128jv; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_1 { + gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>; + label = "LED1"; + status = "disabled"; + }; + green_led: led_2 { + gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>; + label = "LED2"; + status = "disabled"; + }; + yellow_led: led_3 { + gpios = <&gpioa 15 GPIO_ACTIVE_HIGH>; + label = "LED3"; + }; + blue_led: led_4 { + gpios = <&gpiob 4 GPIO_ACTIVE_HIGH>; + label = "LED4"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button: button { + gpios = <&gpiob 3 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + zephyr,code = ; + label = "USR"; + }; + }; +}; + +&clk_hse { + clock-frequency = ; + status = "okay"; +}; + +&clk_lse { + status = "okay"; +}; + +&pll { + div-m = <5>; + mul-n = <192>; + div-p = <2>; + div-q = <4>; + div-r = <4>; + clocks = <&clk_hse>; + status = "okay"; +}; + +&rcc { + clocks = <&pll>; + clock-frequency = ; + d1cpre = <1>; + hpre = <2>; + d1ppre = <2>; + d2ppre1 = <2>; + d2ppre2 = <2>; + d3ppre = <2>; +}; + +&usart1 { + pinctrl-names = "default"; + pinctrl-0 = <&usart1_tx_pa9 &usart1_rx_pa10>; + current-speed = <115200>; + status = "okay"; +}; + +&sdmmc1 { + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_d0_pc8 &sdmmc1_d1_pc9 + &sdmmc1_d2_pc10 &sdmmc1_d3_pc11 + &sdmmc1_ck_pc12 &sdmmc1_cmd_pd2>; + cd-gpios = <&gpioa 8 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&quadspi { + pinctrl-names = "default"; + pinctrl-0 = <&quadspi_clk_pb2 &quadspi_bk1_ncs_pb10 + &quadspi_bk1_io0_pd11 &quadspi_bk1_io1_pd12 + &quadspi_bk1_io2_pe2 &quadspi_bk1_io3_pd13>; + status = "okay"; + + w25q128jv: qspi-nor-flash@90000000 { + compatible = "st,stm32-qspi-nor"; + reg = <0x90000000 DT_SIZE_M(16)>; + qspi-max-frequency = <80000000>; + spi-bus-width = <4>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + storage_partition: partition@0 { + label = "storage"; + reg = <0x0 DT_SIZE_M(16)>; + }; + }; + }; +}; diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml new file mode 100644 index 00000000000..0ce537a1bd4 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb.yaml @@ -0,0 +1,15 @@ +identifier: yd_stm32h750vb +name: YD-STM32H750VB +type: mcu +arch: arm +toolchain: + - zephyr + - gnuarmemb + - xtools +ram: 1024 +flash: 128 +supported: + - gpio + - uart + - qspi +vendor: vcc-gnd diff --git a/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig new file mode 100644 index 00000000000..40e6adc0583 --- /dev/null +++ b/boards/vcc-gnd/yd_stm32h750vb/yd_stm32h750vb_defconfig @@ -0,0 +1,26 @@ +# Copyright(c) 2024 John Sanpe +# SPDX-License-Identifier: Apache-2.0 + +# Enable the internal SMPS regulator +CONFIG_POWER_SUPPLY_LDO=y + +# Enable MPU +CONFIG_ARM_MPU=y + +# Enable HW stack protection +CONFIG_HW_STACK_PROTECTION=y + +CONFIG_SERIAL=y + +# console +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y + +# enable GPIO +CONFIG_GPIO=y + +# Enable Clocks +CONFIG_CLOCK_CONTROL=y + +# enable pin controller +CONFIG_PINCTRL=y