drivers: ethernet: adin2111: add Open Alliance SPI support
Add Open Alliance spi protocol support. Open Alliance is a chunk-based SPI protocol, based on sending over SPI an ethernet frame divided in smaller chunks, using a specific 32-bit header for each chunk transferred. All chunks can be sent or received by a single dma transfer. Default mode is set to Open Alliance SPI without protection, since the adin2111 dev. board comes shipped this way. Tested: - Open Alliance SPI, no protection (default board shipped) - Open Alliance SPI, protection - Generic SPI, no crc - Generic SPI, with crc8 Signed-off-by: Angelo Dureghello <adureghello@baylibre.com>
This commit is contained in:
Angelo Dureghello
Carles Cufí
parent
06c8460a9e
commit
0ca8b0756b
7 changed files with 488 additions and 45 deletions
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@ -5,9 +5,11 @@
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if BOARD_ADI_EVAL_ADIN1110EBZ
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config SPI_STM32_INTERRUPT
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config BOARD
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default "adi_eval_adin1110ebz"
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config SPI_STM32_DMA
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default y
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depends on SPI
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config MDIO_INIT_PRIORITY
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default 81
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@ -197,6 +197,11 @@
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pinctrl-0 = <&spi2_sck_pb13 &spi2_miso_pb14 &spi2_mosi_pb15>;
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pinctrl-names = "default";
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cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>,
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<&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>;
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dma-names = "tx", "rx";
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status = "okay";
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adin1110: adin1110@0 {
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@ -205,6 +210,9 @@
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spi-max-frequency = <25000000>;
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int-gpios = <&gpiob 11 GPIO_ACTIVE_LOW>;
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reset-gpios = <&gpioc 7 GPIO_ACTIVE_LOW>;
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status = "okay";
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spi-oa;
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spi-oa-protection;
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port1 {
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local-mac-address = [ 00 E0 22 FE DA C8 ];
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@ -5,9 +5,8 @@
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if BOARD_ADI_EVAL_ADIN2111EBZ
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config SPI_STM32_INTERRUPT
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default y
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depends on SPI
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config BOARD
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default "adi_eval_adin2111ebz"
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config MDIO_INIT_PRIORITY
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default 81
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@ -17,6 +16,9 @@ config PHY_INIT_PRIORITY
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default 82
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depends on NET_L2_ETHERNET && ETH_DRIVER
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config SPI_STM32_DMA
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default y
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if NETWORKING
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config NET_L2_ETHERNET
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@ -162,6 +162,11 @@
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pinctrl-names = "default";
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cs-gpios = <&gpiob 12 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
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status = "okay";
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dmas = <&dmamux1 2 13 (STM32_DMA_MEMORY_TO_PERIPH | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>,
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<&dmamux1 3 12 (STM32_DMA_PERIPH_TO_MEMORY | STM32_DMA_MEM_INC |
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STM32_DMA_MEM_8BITS | STM32_DMA_PERIPH_8BITS)>;
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dma-names = "tx", "rx";
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adin2111: adin2111@0 {
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compatible = "adi,adin2111";
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@ -169,6 +174,8 @@
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spi-max-frequency = <25000000>;
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int-gpios = <&gpioa 12 GPIO_ACTIVE_LOW>;
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status = "okay";
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spi-oa;
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spi-oa-protection;
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port1 {
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local-mac-address = [ 00 E0 22 FE DA C9 ];
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@ -25,6 +25,8 @@ LOG_MODULE_REGISTER(eth_adin2111, CONFIG_ETHERNET_LOG_LEVEL);
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#include "phy/phy_adin2111_priv.h"
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#include "eth_adin2111_priv.h"
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#define DT_DRV_COMPAT adi_adin2111
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/* SPI Communication check retry delay */
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#define ADIN2111_DEV_AWAIT_DELAY_POLL_US 100U
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/* Number of retries SPI Communication check */
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@ -46,6 +48,10 @@ LOG_MODULE_REGISTER(eth_adin2111, CONFIG_ETHERNET_LOG_LEVEL);
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#define ADIN2111_UNICAST_P1_ADDR_SLOT 2U
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/* MAC Address Rule and DA Filter Port 2 slot/idx */
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#define ADIN2111_UNICAST_P2_ADDR_SLOT 3U
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/* As per RM rev. A table 3, t3 >= 50ms, delay for SPI interface to be ready */
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#define ADIN2111_SPI_ACTIVE_DELAY_MS 50U
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/* As per RM rev. A page 20: approximately 10 ms (maximum) for internal logic to be ready */
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#define ADIN2111_SW_RESET_DELAY_MS 10U
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int eth_adin2111_lock(const struct device *dev, k_timeout_t timeout)
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{
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@ -61,43 +67,288 @@ int eth_adin2111_unlock(const struct device *dev)
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return k_mutex_unlock(&ctx->lock);
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}
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int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg,
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const uint32_t val)
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static inline bool eth_adin2111_oa_get_parity(const uint32_t x)
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{
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const struct adin2111_config *cfg = dev->config;
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size_t header_size = ADIN2111_WRITE_HEADER_SIZE;
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size_t data_size = sizeof(uint32_t);
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#if CONFIG_ETH_ADIN2111_SPI_CFG0
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uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE_CRC] = { 0 };
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#else
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uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE] = { 0 };
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#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
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uint32_t y;
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/* spi header */
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*(uint16_t *)buf = htons((ADIN2111_WRITE_TXN_CTRL | reg));
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#if CONFIG_ETH_ADIN2111_SPI_CFG0
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buf[2] = crc8_ccitt(0, buf, header_size);
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++header_size;
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#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
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y = x ^ (x >> 1);
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y = y ^ (y >> 2);
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y = y ^ (y >> 4);
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y = y ^ (y >> 8);
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y = y ^ (y >> 16);
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/* reg */
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*(uint32_t *)(buf + header_size) = htonl(val);
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#if CONFIG_ETH_ADIN2111_SPI_CFG0
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buf[header_size + data_size] = crc8_ccitt(0, &buf[header_size], data_size);
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++data_size;
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#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
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const struct spi_buf spi_tx_buf = {
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.buf = buf,
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.len = header_size + data_size
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};
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const struct spi_buf_set tx = { .buffers = &spi_tx_buf, .count = 1U };
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return spi_write_dt(&cfg->spi, &tx);
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return !(y & 1);
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}
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int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg,
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uint32_t *val)
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int eth_adin2111_oa_spi_xfer(const struct device *dev, uint8_t *buf_rx, uint8_t *buf_tx, int len)
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{
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const struct adin2111_config *cfg = dev->config;
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struct spi_buf tx_buf[1];
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struct spi_buf rx_buf[1];
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struct spi_buf_set tx;
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struct spi_buf_set rx;
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int ret;
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tx_buf[0].buf = buf_tx;
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tx_buf[0].len = len;
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rx_buf[0].buf = buf_rx;
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rx_buf[0].len = len;
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rx.buffers = rx_buf;
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rx.count = 1;
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tx.buffers = tx_buf;
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tx.count = 1;
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ret = spi_transceive_dt(&cfg->spi, &tx, &rx);
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if (ret < 0) {
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LOG_ERR("ERRR dma!\n");
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return ret;
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}
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return 0;
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}
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static int eth_adin2111_reg_read_oa(const struct device *dev, const uint16_t reg,
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uint32_t *val)
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{
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struct adin2111_data *ctx = dev->data;
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uint32_t pval;
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uint32_t *hdr = (uint32_t *)ctx->oa_tx_buf;
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int len;
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int ret;
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*hdr = reg << 8;
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if (reg >= 0x30) {
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*hdr |= ADIN2111_OA_CTL_MMS;
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}
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*hdr |= eth_adin2111_oa_get_parity(*hdr);
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*hdr = sys_cpu_to_be32(*hdr);
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len = (ctx->oa_prot) ? ADIN2111_OA_CTL_LEN_PROT : ADIN2111_OA_CTL_LEN;
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ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len);
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if (ret < 0) {
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return ret;
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}
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*val = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[8]);
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/* In protected mode read data is followed by its compliment value */
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if (ctx->oa_prot) {
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pval = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[12]);
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if (*val != ~pval) {
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LOG_ERR("OA protected mode rx error !");
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return -1;
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}
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}
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return 0;
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}
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static int eth_adin2111_reg_write_oa(const struct device *dev, const uint16_t reg,
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uint32_t val)
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{
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struct adin2111_data *ctx = dev->data;
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uint32_t pval;
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uint32_t *hdr = (uint32_t *)ctx->oa_tx_buf;
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int len;
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int ret;
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*hdr = reg << 8 | ADIN2111_OA_CTL_WNR;
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if (reg >= 0x30) {
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*hdr |= ADIN2111_OA_CTL_MMS;
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}
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*hdr |= eth_adin2111_oa_get_parity(*hdr);
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*hdr = sys_cpu_to_be32(*hdr);
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len = (ctx->oa_prot) ? ADIN2111_OA_CTL_LEN_PROT : ADIN2111_OA_CTL_LEN;
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*(uint32_t *)&ctx->oa_tx_buf[4] = sys_cpu_to_be32(val);
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if (ctx->oa_prot) {
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*(uint32_t *)&ctx->oa_tx_buf[8] = sys_cpu_to_be32(~val);
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}
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ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len);
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if (ret < 0) {
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return ret;
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}
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if (ctx->oa_prot) {
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pval = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[12]);
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if (val != ~pval) {
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LOG_ERR("OA protected mode tx error !");
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return -1;
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}
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}
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return 0;
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}
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int eth_adin2111_oa_data_read(const struct device *dev, int port)
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{
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struct adin2111_data *ctx = dev->data;
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struct net_if *iface = ((struct adin2111_port_data *)ctx->port[port]->data)->iface;
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struct net_pkt *pkt;
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uint32_t hdr, ftr;
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int i, len, rx_pos, ret, rca, swo;
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ret = eth_adin2111_reg_read(dev, ADIN2111_BUFSTS, &rca);
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if (ret < 0) {
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LOG_ERR("can't read BUFSTS");
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return -EIO;
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}
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rca &= ADIN2111_BUFSTS_RCA_MASK;
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/* Preare all tx headers */
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for (i = 0, len = 0; i < rca; ++i) {
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hdr = ADIN2111_OA_DATA_HDR_DNC;
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hdr |= eth_adin2111_oa_get_parity(hdr);
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*(uint32_t *)&ctx->oa_tx_buf[len] = sys_cpu_to_be32(hdr);
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len += sizeof(uint32_t) + ctx->oa_cps;
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}
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ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, len);
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if (ret < 0) {
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LOG_ERR("SPI xfer failed");
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return ret;
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}
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for (i = 0, rx_pos = 0; i < rca; ++i) {
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ftr = sys_be32_to_cpu(*(uint32_t *)&ctx->oa_rx_buf[rx_pos + ctx->oa_cps]);
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if (eth_adin2111_oa_get_parity(ftr)) {
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LOG_ERR("OA RX: Footer parity error !");
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return -EIO;
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}
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if (!(ftr & ADIN2111_OA_DATA_FTR_SYNC)) {
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LOG_ERR("OA RX: Configuration not in sync !");
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return -EIO;
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}
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if (!(ftr & ADIN2111_OA_DATA_FTR_DV)) {
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LOG_DBG("OA RX: Data chunk not valid, skip !");
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goto update_pos;
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}
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if (ftr & ADIN2111_OA_DATA_FTR_SV) {
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swo = (ftr & ADIN2111_OA_DATA_FTR_SWO_MSK) >> ADIN2111_OA_DATA_FTR_SWO;
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if (swo != 0) {
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LOG_ERR("OA RX: Misalignbed start of frame !");
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return -EIO;
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}
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/* Reset store cursor */
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ctx->scur = 0;
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}
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len = (ftr & ADIN2111_OA_DATA_FTR_EV) ?
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((ftr & ADIN2111_OA_DATA_FTR_EBO_MSK) >> ADIN2111_OA_DATA_FTR_EBO) + 1 :
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ctx->oa_cps;
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memcpy(&ctx->buf[ctx->scur], &ctx->oa_rx_buf[rx_pos], len);
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ctx->scur += len;
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if (ftr & ADIN2111_OA_DATA_FTR_EV) {
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pkt = net_pkt_rx_alloc_with_buffer(iface, CONFIG_ETH_ADIN2111_BUFFER_SIZE,
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AF_UNSPEC, 0,
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K_MSEC(CONFIG_ETH_ADIN2111_TIMEOUT));
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if (!pkt) {
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LOG_ERR("OA RX: cannot allcate packet space, skipping.");
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return -EIO;
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}
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/* Skipping CRC32 */
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ret = net_pkt_write(pkt, ctx->buf, ctx->scur - sizeof(uint32_t));
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if (ret < 0) {
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net_pkt_unref(pkt);
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LOG_ERR("Failed to write pkt, scur %d, err %d", ctx->scur, ret);
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return ret;
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}
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ret = net_recv_data(iface, pkt);
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if (ret < 0) {
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net_pkt_unref(pkt);
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LOG_ERR("Port %u failed to enqueue frame to RX queue, %d",
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port, ret);
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return ret;
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}
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}
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update_pos:
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rx_pos += ctx->oa_cps + sizeof(uint32_t);
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}
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return ret;
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}
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/*
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* Setting up for a single dma transfer.
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*/
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static int eth_adin2111_send_oa_frame(const struct device *dev, struct net_pkt *pkt, int port)
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{
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struct adin2111_data *ctx = dev->data;
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uint16_t clen, len = net_pkt_get_len(pkt);
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uint32_t hdr;
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uint8_t chunks, i;
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int ret, txc, cur;
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chunks = len / ctx->oa_cps;
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if (len % ctx->oa_cps) {
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chunks++;
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}
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ret = eth_adin2111_reg_read(dev, ADIN2111_BUFSTS, &txc);
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if (ret < 0) {
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LOG_ERR("Cannot read txc");
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return -EIO;
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}
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txc = (txc & ADIN2111_BUFSTS_TXC_MASK) >> ADIN2111_BUFSTS_TXC;
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if (txc < chunks) {
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return -EIO;
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}
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/* Prepare for single dma transfer */
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for (i = 1, cur = 0; i <= chunks; i++) {
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hdr = ADIN2111_OA_DATA_HDR_DNC | ADIN2111_OA_DATA_HDR_DV |
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ADIN2111_OA_DATA_HDR_NORX;
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hdr |= (!!port << ADIN2111_OA_DATA_HDR_VS);
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if (i == 1) {
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hdr |= ADIN2111_OA_DATA_HDR_SV;
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}
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if (i == chunks) {
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hdr |= ADIN2111_OA_DATA_HDR_EV;
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hdr |= (ctx->oa_cps - 1) << ADIN2111_OA_DATA_HDR_EBO;
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}
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hdr |= eth_adin2111_oa_get_parity(hdr);
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*(uint32_t *)&ctx->oa_tx_buf[cur] = sys_cpu_to_be32(hdr);
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cur += sizeof(uint32_t);
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clen = len > ctx->oa_cps ? ctx->oa_cps : len;
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ret = net_pkt_read(pkt, &ctx->oa_tx_buf[cur], clen);
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if (ret < 0) {
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LOG_ERR("Cannot read from tx packet");
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return ret;
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}
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cur += ctx->oa_cps;
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len -= clen;
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}
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ret = eth_adin2111_oa_spi_xfer(dev, ctx->oa_rx_buf, ctx->oa_tx_buf, cur);
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if (ret < 0) {
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LOG_ERR("Error on SPI xfer");
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return ret;
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}
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return 0;
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}
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static int eth_adin2111_reg_read_generic(const struct device *dev,
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const uint16_t reg,
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uint32_t *val)
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{
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const struct adin2111_config *cfg = dev->config;
|
||||
size_t header_len = ADIN2111_READ_HEADER_SIZE;
|
||||
|
|
@ -149,6 +400,72 @@ int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg,
|
|||
return ret;
|
||||
}
|
||||
|
||||
static int eth_adin2111_reg_write_generic(const struct device *dev,
|
||||
const uint16_t reg,
|
||||
const uint32_t val)
|
||||
{
|
||||
const struct adin2111_config *cfg = dev->config;
|
||||
size_t header_size = ADIN2111_WRITE_HEADER_SIZE;
|
||||
size_t data_size = sizeof(uint32_t);
|
||||
#if CONFIG_ETH_ADIN2111_SPI_CFG0
|
||||
uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE_CRC] = { 0 };
|
||||
#else
|
||||
uint8_t buf[ADIN2111_REG_WRITE_BUF_SIZE] = { 0 };
|
||||
#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
|
||||
|
||||
/* spi header */
|
||||
*(uint16_t *)buf = htons((ADIN2111_WRITE_TXN_CTRL | reg));
|
||||
#if CONFIG_ETH_ADIN2111_SPI_CFG0
|
||||
buf[2] = crc8_ccitt(0, buf, header_size);
|
||||
++header_size;
|
||||
#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
|
||||
|
||||
/* reg */
|
||||
*(uint32_t *)(buf + header_size) = htonl(val);
|
||||
#if CONFIG_ETH_ADIN2111_SPI_CFG0
|
||||
buf[header_size + data_size] = crc8_ccitt(0, &buf[header_size], data_size);
|
||||
++data_size;
|
||||
#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
|
||||
|
||||
const struct spi_buf spi_tx_buf = {
|
||||
.buf = buf,
|
||||
.len = header_size + data_size
|
||||
};
|
||||
const struct spi_buf_set tx = { .buffers = &spi_tx_buf, .count = 1U };
|
||||
|
||||
return spi_write_dt(&cfg->spi, &tx);
|
||||
}
|
||||
|
||||
int eth_adin2111_reg_read(const struct device *dev, const uint16_t reg,
|
||||
uint32_t *val)
|
||||
{
|
||||
struct adin2111_data *ctx = dev->data;
|
||||
int rval;
|
||||
|
||||
if (ctx->oa) {
|
||||
rval = eth_adin2111_reg_read_oa(dev, reg, val);
|
||||
} else {
|
||||
rval = eth_adin2111_reg_read_generic(dev, reg, val);
|
||||
}
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
||||
int eth_adin2111_reg_write(const struct device *dev, const uint16_t reg,
|
||||
const uint32_t val)
|
||||
{
|
||||
struct adin2111_data *ctx = dev->data;
|
||||
int rval;
|
||||
|
||||
if (ctx->oa) {
|
||||
rval = eth_adin2111_reg_write_oa(dev, reg, val);
|
||||
} else {
|
||||
rval = eth_adin2111_reg_write_generic(dev, reg, val);
|
||||
}
|
||||
|
||||
return rval;
|
||||
}
|
||||
|
||||
static int adin2111_read_fifo(const struct device *dev, const uint8_t port)
|
||||
{
|
||||
const struct adin2111_config *cfg = dev->config;
|
||||
|
|
@ -302,11 +619,13 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3)
|
|||
goto continue_unlock;
|
||||
}
|
||||
|
||||
if (!ctx->oa) {
|
||||
#if CONFIG_ETH_ADIN2111_SPI_CFG0
|
||||
if (status0 & ADIN2111_STATUS1_SPI_ERR) {
|
||||
LOG_WRN("Detected TX SPI CRC error");
|
||||
if (status0 & ADIN2111_STATUS1_SPI_ERR) {
|
||||
LOG_WRN("Detected TX SPI CRC error");
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif /* CONFIG_ETH_ADIN2111_SPI_CFG0 */
|
||||
|
||||
/* handle port 1 phy interrupts */
|
||||
if (status0 & ADIN2111_STATUS0_PHYINT) {
|
||||
|
|
@ -318,6 +637,22 @@ static void adin2111_offload_thread(void *p1, void *p2, void *p3)
|
|||
adin2111_port_on_phyint(ctx->port[1]);
|
||||
}
|
||||
|
||||
if (ctx->oa) {
|
||||
if (status1 & ADIN2111_STATUS1_P1_RX_RDY) {
|
||||
ret = eth_adin2111_oa_data_read(dev, 0);
|
||||
if (ret < 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
if (status1 & ADIN2111_STATUS1_P2_RX_RDY) {
|
||||
ret = eth_adin2111_oa_data_read(dev, 1);
|
||||
if (ret < 0) {
|
||||
break;
|
||||
}
|
||||
}
|
||||
goto continue_unlock;
|
||||
}
|
||||
|
||||
/* handle port 1 rx */
|
||||
if (status1 & ADIN2111_STATUS1_P1_RX_RDY) {
|
||||
do {
|
||||
|
|
@ -368,7 +703,7 @@ continue_unlock:
|
|||
LOG_ERR("Failed to write IMASK1, %d", ret);
|
||||
}
|
||||
eth_adin2111_unlock(dev);
|
||||
};
|
||||
}
|
||||
}
|
||||
|
||||
static void adin2111_int_callback(const struct device *dev,
|
||||
|
|
@ -416,6 +751,31 @@ static int adin2111_port_send(const struct device *dev, struct net_pkt *pkt)
|
|||
|
||||
eth_adin2111_lock(adin, K_FOREVER);
|
||||
|
||||
if (ctx->oa) {
|
||||
uint32_t val, rca = 0;
|
||||
/*
|
||||
* By high-traffic zperf test, noted that ADIN2111 does not like we send
|
||||
* if there is something to be received. It stops to issue rx interrupts
|
||||
* and zperf transfer hangs. Forcing a receive for this case.
|
||||
*/
|
||||
ret = eth_adin2111_reg_read(adin, ADIN2111_BUFSTS, &val);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
rca = val & ADIN2111_BUFSTS_RCA_MASK;
|
||||
|
||||
if (rca > 0) {
|
||||
eth_adin2111_unlock(adin);
|
||||
k_sem_give(&ctx->offload_sem);
|
||||
k_yield();
|
||||
eth_adin2111_lock(adin, K_FOREVER);
|
||||
}
|
||||
|
||||
ret = eth_adin2111_send_oa_frame(cfg->adin, pkt, htons(cfg->port_idx));
|
||||
|
||||
goto end_check;
|
||||
}
|
||||
|
||||
/* query remaining tx fifo space */
|
||||
ret = adin2111_read_tx_space(adin, &tx_space);
|
||||
if (ret < 0) {
|
||||
|
|
@ -497,6 +857,7 @@ static int adin2111_port_send(const struct device *dev, struct net_pkt *pkt)
|
|||
|
||||
ret = spi_write_dt(&((const struct adin2111_config *) adin->config)->spi,
|
||||
&tx);
|
||||
end_check:
|
||||
if (ret < 0) {
|
||||
eth_stats_update_errors_tx(data->iface);
|
||||
LOG_ERR("Port %u frame SPI write failed, %d", cfg->port_idx, ret);
|
||||
|
|
@ -670,7 +1031,7 @@ static void adin2111_port_iface_init(struct net_if *iface)
|
|||
|
||||
/* all ifaces are done, start INT processing */
|
||||
k_thread_create(&ctx->rx_thread, ctx->rx_thread_stack,
|
||||
CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE,
|
||||
K_KERNEL_STACK_SIZEOF(ctx->rx_thread_stack),
|
||||
adin2111_offload_thread,
|
||||
(void *)adin, NULL, NULL,
|
||||
CONFIG_ETH_ADIN2111_IRQ_THREAD_PRIO,
|
||||
|
|
@ -839,6 +1200,8 @@ static int adin2111_init(const struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
k_msleep(ADIN2111_SPI_ACTIVE_DELAY_MS);
|
||||
|
||||
ret = adin2111_check_spi(dev);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("Failed to communicate over SPI, %d", ret);
|
||||
|
|
@ -852,6 +1215,8 @@ static int adin2111_init(const struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
k_msleep(ADIN2111_SW_RESET_DELAY_MS);
|
||||
|
||||
ret = adin2111_await_device(dev);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("ADIN did't come out of the reset, %d", ret);
|
||||
|
|
@ -871,6 +1236,10 @@ static int adin2111_init(const struct device *dev)
|
|||
val &= ~ADIN2111_CONFIG0_RXCTE;
|
||||
val &= ~(ADIN2111_CONFIG0_TXCTE | ADIN2111_CONFIG0_TXFCSVE);
|
||||
|
||||
if (ctx->oa) {
|
||||
val |= ADIN2111_CONFIG0_ZARFE;
|
||||
}
|
||||
|
||||
ret = eth_adin2111_reg_write(dev, ADIN2111_CONFIG0, val);
|
||||
if (ret < 0) {
|
||||
LOG_ERR("Failed to write CONFIG0, %d", ret);
|
||||
|
|
@ -966,12 +1335,11 @@ static const struct ethernet_api adin2111_port_api = {
|
|||
NET_L2_GET_CTX_TYPE(ETHERNET_L2), NET_ETH_MTU);
|
||||
|
||||
#define ADIN2111_SPI_OPERATION ((uint16_t)(SPI_OP_MODE_MASTER | SPI_TRANSFER_MSB | SPI_WORD_SET(8)))
|
||||
|
||||
#define ADIN2111_MAC_INITIALIZE(inst, dev_id, ifaces, name) \
|
||||
static uint8_t __aligned(4) name##_buffer_##inst[CONFIG_ETH_ADIN2111_BUFFER_SIZE]; \
|
||||
static const struct adin2111_config name##_config_##inst = { \
|
||||
.id = dev_id, \
|
||||
.spi = SPI_DT_SPEC_INST_GET(inst, ADIN2111_SPI_OPERATION, 1), \
|
||||
.id = dev_id, \
|
||||
.spi = SPI_DT_SPEC_INST_GET(inst, ADIN2111_SPI_OPERATION, 0), \
|
||||
.interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \
|
||||
.reset = GPIO_DT_SPEC_INST_GET_OR(inst, reset_gpios, { 0 }), \
|
||||
}; \
|
||||
|
|
@ -981,6 +1349,9 @@ static const struct ethernet_api adin2111_port_api = {
|
|||
.offload_sem = Z_SEM_INITIALIZER(name##_data_##inst.offload_sem, 0, 1), \
|
||||
.lock = Z_MUTEX_INITIALIZER(name##_data_##inst.lock), \
|
||||
.buf = name##_buffer_##inst, \
|
||||
.oa = DT_INST_PROP(inst, spi_oa), \
|
||||
.oa_prot = DT_INST_PROP(inst, spi_oa_protection), \
|
||||
.oa_cps = 64, \
|
||||
}; \
|
||||
/* adin */ \
|
||||
DEVICE_DT_DEFINE(DT_DRV_INST(inst), adin2111_init, NULL, \
|
||||
|
|
|
|||
|
|
@ -33,6 +33,10 @@
|
|||
#define ADIN2111_CONFIG0_SYNC BIT(15)
|
||||
/* Transmit Frame Check Sequence Validation Enable */
|
||||
#define ADIN2111_CONFIG0_TXFCSVE BIT(14)
|
||||
/* Zero Align Receive Frame Enable */
|
||||
#define ADIN2111_CONFIG0_ZARFE BIT(12)
|
||||
/* New packet received only after a new CS assertion */
|
||||
#define ADIN2111_CONFIG0_CSARFE BIT(13)
|
||||
/* Transmit Cut Through Enable */
|
||||
#define ADIN2111_CONFIG0_TXCTE BIT(9)
|
||||
/* Receive Cut Through Enable. Must be 0 for Generic SPI */
|
||||
|
|
@ -72,9 +76,18 @@
|
|||
#define ADIN2111_STATUS1_SPI_ERR BIT(10)
|
||||
/* Port 1 RX FIFO Contains Data */
|
||||
#define ADIN2111_STATUS1_P1_RX_RDY BIT(4)
|
||||
/* Frame transmitted */
|
||||
#define ADIN2111_STATUS1_TX_RDY BIT(3)
|
||||
/* Value to completely clear status register 1 */
|
||||
#define ADIN2111_STATUS1_CLEAR 0xFFF01F08U
|
||||
|
||||
/* Buffer Status Register */
|
||||
#define ADIN2111_BUFSTS 0x0BU
|
||||
/* Rx chunks available */
|
||||
#define ADIN2111_BUFSTS_RCA_MASK GENMASK(7, 0)
|
||||
/* Tx credits */
|
||||
#define ADIN2111_BUFSTS_TXC 8U
|
||||
#define ADIN2111_BUFSTS_TXC_MASK GENMASK(15, 8)
|
||||
|
||||
/* Interrupt Mask Register 0 */
|
||||
#define ADIN2111_IMASK0 0x0CU
|
||||
|
|
@ -161,6 +174,34 @@
|
|||
/* Manufacturer unique ID */
|
||||
#define ADIN2111_PHYID_OUI 0xa0ef
|
||||
|
||||
/* Open Alliance definitions */
|
||||
#define ADIN2111_OA_ALLOC_TIMEOUT K_MSEC(10)
|
||||
/* Max setting to a max RCA of 255 68-bytes ckunks */
|
||||
#define ADIN2111_OA_BUF_SZ (255U * 64U)
|
||||
|
||||
#define ADIN2111_OA_CTL_LEN_PROT 16U
|
||||
#define ADIN2111_OA_CTL_LEN 12U
|
||||
#define ADIN2111_OA_CTL_MMS BIT(24)
|
||||
#define ADIN2111_OA_CTL_WNR BIT(29)
|
||||
|
||||
#define ADIN2111_OA_DATA_HDR_DNC BIT(31)
|
||||
#define ADIN2111_OA_DATA_HDR_NORX BIT(29)
|
||||
#define ADIN2111_OA_DATA_HDR_VS 22U
|
||||
#define ADIN2111_OA_DATA_HDR_DV BIT(21)
|
||||
#define ADIN2111_OA_DATA_HDR_SV BIT(20)
|
||||
#define ADIN2111_OA_DATA_HDR_EV BIT(14)
|
||||
#define ADIN2111_OA_DATA_HDR_EBO 8U
|
||||
|
||||
#define ADIN2111_OA_DATA_FTR_SYNC BIT(29)
|
||||
#define ADIN2111_OA_DATA_FTR_EBO 8U
|
||||
#define ADIN2111_OA_DATA_FTR_DV BIT(21)
|
||||
#define ADIN2111_OA_DATA_FTR_SV BIT(20)
|
||||
#define ADIN2111_OA_DATA_FTR_EV BIT(14)
|
||||
#define ADIN2111_OA_DATA_FTR_SWO 16U
|
||||
#define ADIN2111_OA_DATA_FTR_SWO_MSK GENMASK(19, 16)
|
||||
#define ADIN2111_OA_DATA_FTR_EBO 8U
|
||||
#define ADIN2111_OA_DATA_FTR_EBO_MSK GENMASK(13, 8)
|
||||
|
||||
enum adin2111_chips_id {
|
||||
ADIN2111_MAC = 0,
|
||||
ADIN1110_MAC,
|
||||
|
|
@ -183,6 +224,12 @@ struct adin2111_data {
|
|||
uint32_t imask1;
|
||||
uint16_t ifaces_left_to_init;
|
||||
uint8_t *buf;
|
||||
uint16_t scur;
|
||||
bool oa;
|
||||
bool oa_prot;
|
||||
uint8_t oa_cps;
|
||||
uint8_t oa_tx_buf[ADIN2111_OA_BUF_SZ];
|
||||
uint8_t oa_rx_buf[ADIN2111_OA_BUF_SZ];
|
||||
|
||||
K_KERNEL_STACK_MEMBER(rx_thread_stack, CONFIG_ETH_ADIN2111_IRQ_THREAD_STACK_SIZE);
|
||||
struct k_thread rx_thread;
|
||||
|
|
|
|||
|
|
@ -53,6 +53,12 @@ properties:
|
|||
reset-gpios:
|
||||
type: phandle-array
|
||||
description: The reset pin of ADIN2111.
|
||||
spi-oa:
|
||||
type: boolean
|
||||
description: Enables Open Alliance SPI protocol.
|
||||
spi-oa-protection:
|
||||
type: boolean
|
||||
description: Enables Open Alliance SPI protocol protection.
|
||||
|
||||
child-binding:
|
||||
description: Port properties
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue