driver: clock: Update clock control driver for RA8

This update is to support clock API for RA8
Move the clock initialize function into clock driver
Peripheral clock now has 2 more property in clock cell for enable
and disable clock to peripheral module

Signed-off-by: Duy Phuong Hoang. Nguyen <duy.nguyen.xa@renesas.com>

boards/renesas/ek_ra8m1/doc/index.rst

@@ -96,6 +96,8 @@ The below features are currently supported on Zephyr OS for EK-RA8M1 board:
 +-----------+------------+----------------------+
 | UART      | on-chip    | serial               |
 +-----------+------------+----------------------+
+| CLOCK     | on-chip    | clock control        |
++-----------+------------+----------------------+
 
 Other hardware features are currently not supported by the port.
 

boards/renesas/ek_ra8m1/ek_ra8m1_defconfig

@@ -15,3 +15,4 @@ CONFIG_CONSOLE=y
 
 CONFIG_BUILD_OUTPUT_HEX=y
 CONFIG_BUILD_NO_GAP_FILL=y
+CONFIG_CLOCK_CONTROL=y

drivers/clock_control/CMakeLists.txt

@@ -27,6 +27,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_SMARTBOND           clock_cont
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NUMAKER_SCC         clock_control_numaker_scc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NXP_S32             clock_control_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA          clock_control_renesas_ra.c)
+zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RENESAS_RA_CGC      clock_control_renesas_ra_cgc.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_AMBIQ               clock_control_ambiq.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_PWM                 clock_control_pwm.c)
 zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_RPI_PICO            clock_control_rpi_pico.c)

drivers/clock_control/Kconfig

@@ -82,6 +82,8 @@ source "drivers/clock_control/Kconfig.agilex5"
 
 source "drivers/clock_control/Kconfig.renesas_ra"
 
+source "drivers/clock_control/Kconfig.renesas_ra8"
+
 source "drivers/clock_control/Kconfig.max32"
 
 source "drivers/clock_control/Kconfig.ambiq"

drivers/clock_control/Kconfig.renesas_ra8

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Renesas Electronics Corporation
+# SPDX-License-Identifier: Apache-2.0
+
+config CLOCK_CONTROL_RENESAS_RA_CGC
+	bool "RA CGC driver"
+	default y
+	depends on SOC_FAMILY_RENESAS_RA
+	depends on HAS_RENESAS_RA_FSP
+	help
+	  Enable support for Renesas RA CGC driver.

drivers/clock_control/clock_control_renesas_ra_cgc.c

@@ -0,0 +1,92 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <string.h>
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/kernel.h>
+#include <soc.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+#include <zephyr/drivers/clock_control/renesas_ra_cgc.h>
+
+static int clock_control_renesas_ra_on(const struct device *dev, clock_control_subsys_t sys)
+{
+	struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys;
+
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+	WRITE_BIT(*subsys_clk->mstp, subsys_clk->stop_bit, false);
+	return 0;
+}
+
+static int clock_control_renesas_ra_off(const struct device *dev, clock_control_subsys_t sys)
+{
+	struct clock_control_ra_subsys_cfg *subsys_clk = (struct clock_control_ra_subsys_cfg *)sys;
+
+	if (!dev || !sys) {
+		return -EINVAL;
+	}
+
+	WRITE_BIT(*subsys_clk->mstp, subsys_clk->stop_bit, true);
+	return 0;
+}
+
+static int clock_control_renesas_ra_get_rate(const struct device *dev, clock_control_subsys_t sys,
+					     uint32_t *rate)
+{
+	const struct clock_control_ra_pclk_cfg *config = dev->config;
+	uint32_t clk_src_rate;
+	uint32_t clk_div_val;
+
+	if (!dev || !sys || !rate) {
+		return -EINVAL;
+	}
+
+	clk_src_rate = R_BSP_SourceClockHzGet(config->clk_src);
+	clk_div_val = R_FSP_ClockDividerGet(config->clk_div);
+	*rate = clk_src_rate / clk_div_val;
+	return 0;
+}
+
+/**
+ * @brief Initializes a peripheral clock device driver
+ */
+static int clock_control_ra_init_pclk(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+
+	return 0;
+}
+
+static int clock_control_ra_init(const struct device *dev)
+{
+	ARG_UNUSED(dev);
+	/* Call to HAL layer to initialize system clock and peripheral clock */
+	bsp_clock_init();
+	return 0;
+}
+
+static const struct clock_control_driver_api clock_control_reneas_ra_api = {
+	.on = clock_control_renesas_ra_on,
+	.off = clock_control_renesas_ra_off,
+	.get_rate = clock_control_renesas_ra_get_rate,
+};
+
+#define INIT_PCLK(node_id)                                                                         \
+	IF_ENABLED(DT_NODE_HAS_COMPAT(node_id, renesas_ra8_cgc_pclk),                              \
+		   (static const struct clock_control_ra_pclk_cfg node_id##_cfg =                  \
+			    {.clk_src = DT_PROP_OR(node_id, clk_src, RA_CLOCK_SOURCE_DISABLE),     \
+			     .clk_div = DT_PROP_OR(node_id, clk_div, RA_SYS_CLOCK_DIV_1)};         \
+		    DEVICE_DT_DEFINE(node_id, &clock_control_ra_init_pclk, NULL, NULL,             \
+				     &node_id##_cfg, PRE_KERNEL_1,                                 \
+				     CONFIG_KERNEL_INIT_PRIORITY_OBJECTS,                          \
+				     &clock_control_reneas_ra_api)));
+
+DEVICE_DT_DEFINE(DT_NODELABEL(pclkblock), &clock_control_ra_init, NULL, NULL, NULL, PRE_KERNEL_1,
+		 CONFIG_KERNEL_INIT_PRIORITY_OBJECTS, NULL);
+
+DT_FOREACH_CHILD_STATUS_OKAY(DT_NODELABEL(pclkblock), INIT_PCLK);

dts/arm/renesas/ra/ra8/r7fa8m1xh.dtsi

@@ -84,49 +84,49 @@
 			cpuclk: cpuclk {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_1>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			iclk: iclk {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_2>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			pclka: pclka {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_4>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			pclkb: pclkb {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_8>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			pclkc: pclkc {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_8>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			pclkd: pclkd {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_4>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			pclke: pclke {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_2>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
@@ -139,62 +139,62 @@
 					sdclk = <1>;
 					#clock-cells = <0>;
 				};
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			fclk: fclk {
 				compatible = "renesas,ra8-cgc-pclk";
 				clk_div = <RA_SYS_CLOCK_DIV_8>;
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "okay";
 			};
 
 			clkout: clkout {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			sciclk: sciclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			spiclk: spiclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			canfdclk: canfdclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			i3cclk: i3cclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			uclk: uclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			u60clk: u60clk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 
 			octaspiclk: octaspiclk {
 				compatible = "renesas,ra8-cgc-pclk";
-				#clock-cells = <0>;
+				#clock-cells = <2>;
 				status = "disabled";
 			};
 		};

dts/arm/renesas/ra/ra8/ra8x1.dtsi

@@ -8,7 +8,7 @@
 #include <arm/armv8.1-m.dtsi>
 #include <freq.h>
 #include <zephyr/dt-bindings/pinctrl/renesas/ra-pinctrl.h>
-
+#include <zephyr/dt-bindings/clock/ra_clock.h>
 
 / {
 	cpus {
@@ -175,7 +175,7 @@
 			interrupts = <4 1>, <5 1>, <6 1>, <7 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358000 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 31>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";
@@ -189,7 +189,7 @@
 			interrupts = <8 1>, <9 1>, <10 1>, <11 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358100 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 30>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";
@@ -203,7 +203,7 @@
 			interrupts = <12 1>, <13 1>, <14 1>, <15 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358200 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 29>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";
@@ -217,7 +217,7 @@
 			interrupts = <16 1>, <17 1>, <18 1>, <19 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358300 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 28>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";
@@ -231,7 +231,7 @@
 			interrupts = <20 1>, <21 1>, <22 1>, <23 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358400 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 27>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";
@@ -245,7 +245,7 @@
 			interrupts = <24 1>, <25 1>, <26 1>, <27 1>;
 			interrupt-names = "rxi", "txi", "tei", "eri";
 			reg = <0x40358900 0x100>;
-			clocks = <&sciclk>;
+			clocks = <&sciclk MSTPB 22>;
 			status = "disabled";
 			uart {
 				compatible = "renesas,ra8-uart-sci-b";

dts/bindings/clock/renesas,ra8-cgc-pclk.yaml

@@ -18,4 +18,8 @@ properties:
                  system clock frequency.
 
   "#clock-cells":
-    const: 0
+    const: 2
+
+clock-cells:
+  - mstp
+  - stop_bit

include/zephyr/drivers/clock_control/renesas_ra_cgc.h

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2024 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_
+#define ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_
+
+#include <zephyr/drivers/clock_control.h>
+#include <zephyr/dt-bindings/clock/ra_clock.h>
+
+struct clock_control_ra_pclk_cfg {
+	uint32_t clk_src;
+	uint32_t clk_div;
+};
+
+struct clock_control_ra_subsys_cfg {
+	volatile uint32_t *mstp;
+	uint32_t stop_bit;
+};
+
+#endif /* ZEPHYR_INCLUDE_DRIVERS_CLOCK_CONTROL_RENESAS_RA_CGC_H_ */

include/zephyr/dt-bindings/clock/ra_clock.h

@@ -117,4 +117,10 @@
 #define RA_I3C_CLOCK_DIV_6 3
 #define RA_I3C_CLOCK_DIV_8 4
 
+#define MSTPA 0x40203000
+#define MSTPB 0x40203004
+#define MSTPC 0x40203008
+#define MSTPD 0x4020300C
+#define MSTPE 0x40203010
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_RA_H_ */

soc/renesas/ra/ra8m1/Kconfig

@@ -11,6 +11,7 @@ config SOC_SERIES_RA8M1
 	select FPU
 	select HAS_SWO
 	select XIP
+	select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
 	select HAS_RENESAS_RA_FSP
 	help
 	  Enable support for Renesas RA8M1 MCU series

soc/renesas/ra/ra8m1/soc.c

@@ -37,7 +37,6 @@ static int renesas_ra8m1_init(void)
 {
 	SystemCoreClock = BSP_MOCO_HZ;
 	g_protect_pfswe_counter = 0;
-	bsp_clock_init();
 
 	return 0;
 }