drivers: pwm: remove duplicated pulse > period checks

The API call checks for this condition before calling the pin_set driver
OP call, so drivers don't have to do this check now.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

drivers/pwm/pwm_gd32.c

@@ -142,10 +142,6 @@ static int pwm_gd32_pin_set(const struct device *dev, uint32_t pwm,
 		return -EINVAL;
 	}
 
-	if (pulse_cycles > period_cycles) {
-		return -EINVAL;
-	}
-
 	/* 16-bit timers can count up to UINT16_MAX */
 	if (!config->is_32bit && (period_cycles > UINT16_MAX)) {
 		return -ENOTSUP;

drivers/pwm/pwm_imx.c

@@ -60,7 +60,7 @@ static int imx_pwm_pin_set(const struct device *dev, uint32_t pwm,
 	uint32_t cr, sr;
 
 
-	if ((period_cycles == 0U) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0U) {
 		LOG_ERR("Invalid combination: period_cycles=%d, "
 			    "pulse_cycles=%d", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_ite_it8xxx2.c

@@ -109,9 +109,6 @@ static int pwm_it8xxx2_pin_set(const struct device *dev,
 
 	ARG_UNUSED(pwm);
 
-	if (pulse_cycles > period_cycles)
-		return -EINVAL;
-
 	/* PWM channel clock source gating before configuring */
 	pwm_enable(dev, 0);
 

drivers/pwm/pwm_mchp_xec.c

@@ -326,10 +326,6 @@ static int pwm_xec_pin_set(const struct device *dev, uint32_t pwm,
 		return -EIO;
 	}
 
-	if (pulse_cycles > period_cycles) {
-		return -EINVAL;
-	}
-
 	if (flags) {
 		/* PWM polarity not supported (yet?) */
 		return -ENOTSUP;

drivers/pwm/pwm_mcux.c

@@ -52,7 +52,7 @@ static int mcux_pwm_pin_set(const struct device *dev, uint32_t pwm,
 		return -ENOTSUP;
 	}
 
-	if ((period_cycles == 0) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0) {
 		LOG_ERR("Invalid combination: period_cycles=%u, "
 			"pulse_cycles=%u", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_mcux_ftm.c

@@ -70,7 +70,7 @@ static int mcux_ftm_pin_set(const struct device *dev, uint32_t pwm,
 	uint32_t irqs;
 #endif /* CONFIG_PWM_CAPTURE */
 
-	if ((period_cycles == 0U) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0U) {
 		LOG_ERR("Invalid combination: period_cycles=%d, "
 			    "pulse_cycles=%d", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_mcux_sctimer.c

@@ -48,7 +48,7 @@ static int mcux_sctimer_pwm_pin_set(const struct device *dev, uint32_t pwm,
 		return -EINVAL;
 	}
 
-	if ((period_cycles == 0) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0) {
 		LOG_ERR("Invalid combination: period_cycles=%u, "
 			"pulse_cycles=%u", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_mcux_tpm.c

@@ -49,7 +49,7 @@ static int mcux_tpm_pin_set(const struct device *dev, uint32_t pwm,
 	struct mcux_tpm_data *data = dev->data;
 	uint8_t duty_cycle;
 
-	if ((period_cycles == 0U) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0U) {
 		LOG_ERR("Invalid combination: period_cycles=%d, "
 			    "pulse_cycles=%d", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_npcx.c

@@ -102,10 +102,6 @@ static int pwm_npcx_pin_set(const struct device *dev, uint32_t pwm,
 	uint32_t dcr;
 	uint32_t prsc;
 
-	if (pulse_cycles > period_cycles) {
-		return -EINVAL;
-	}
-
 	ctl = inst->PWMCTL | BIT(NPCX_PWMCTL_PWR);
 
 	/* Select PWM inverted polarity (ie. active-low pulse). */

drivers/pwm/pwm_nrfx.c

@@ -189,12 +189,6 @@ static int pwm_nrfx_pin_set(const struct device *dev, uint32_t pwm,
 		}
 	}
 
-	/* Limit pulse cycles to period cycles (meaning 100% duty), bigger
-	 * values might not fit after prescaling into the 15-bit field that
-	 * is filled below.
-	 */
-	pulse_cycles = MIN(pulse_cycles, period_cycles);
-
 	/* Store new pulse value bit[14:0], and polarity bit[15] for channel. */
 	data->current[channel] = (
 		(data->current[channel] & PWM_NRFX_CH_POLARITY_MASK)

drivers/pwm/pwm_rv32m1_tpm.c

@@ -46,7 +46,7 @@ static int rv32m1_tpm_pin_set(const struct device *dev, uint32_t pwm,
 	struct rv32m1_tpm_data *data = dev->data;
 	uint8_t duty_cycle;
 
-	if ((period_cycles == 0U) || (pulse_cycles > period_cycles)) {
+	if (period_cycles == 0U) {
 		LOG_ERR("Invalid combination: period_cycles=%d, "
 			    "pulse_cycles=%d", period_cycles, pulse_cycles);
 		return -EINVAL;

drivers/pwm/pwm_sam.c

@@ -54,7 +54,7 @@ static int sam_pwm_pin_set(const struct device *dev, uint32_t ch,
 		return -ENOTSUP;
 	}
 
-	if (period_cycles == 0U || pulse_cycles > period_cycles) {
+	if (period_cycles == 0U) {
 		return -EINVAL;
 	}
 

drivers/pwm/pwm_sifive.c

@@ -171,12 +171,6 @@ static int pwm_sifive_pin_set(const struct device *dev,
 		return -EIO;
 	}
 
-	if (pulse_cycles > period_cycles) {
-		LOG_ERR("Requested pulse %d is longer than period %d\n",
-			pulse_cycles, period_cycles);
-		return -EIO;
-	}
-
 	/* Set the pwmscale field */
 	sys_set_mask(PWM_REG(config, REG_PWMCFG),
 		     SF_PWMSCALEMASK,

drivers/pwm/pwm_stm32.c

@@ -235,11 +235,6 @@ static int pwm_stm32_pin_set(const struct device *dev, uint32_t pwm,
 		return -EINVAL;
 	}
 
-	if (pulse_cycles > period_cycles) {
-		LOG_ERR("Invalid combination of pulse and period cycles");
-		return -EINVAL;
-	}
-
 	/*
 	 * Non 32-bit timers count from 0 up to the value in the ARR register
 	 * (16-bit). Thus period_cycles cannot be greater than UINT16_MAX + 1.

drivers/pwm/pwm_xlnx_axi_timer.c

@@ -74,11 +74,6 @@ static int xlnx_axi_timer_pin_set(const struct device *dev, uint32_t pwm,
 		return -ENOTSUP;
 	}
 
-	if (pulse_cycles > period_cycles) {
-		LOG_ERR("pulse cycles must be less than or equal to period");
-		return -EINVAL;
-	}
-
 	LOG_DBG("period = 0x%08x, pulse = 0x%08x", period_cycles, pulse_cycles);
 
 	if (pulse_cycles == 0) {