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boards: nxp: enable mcux udc on lpc55s69, rt1060 and rt685

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set DT node as Okay in board device tree;
add board level's d-cal, txcal45dp and txcal45dm to usbphy node;
enable usb clock; set USB_STACK_USE_DEDICATED_RAM for lpc55s69 and rt685;
load usb.ld for lpc55s69 and rt685.

Signed-off-by: Mark Wang <yichang.wang@nxp.com>
This commit is contained in:
Mark Wang 2024-05-27 15:43:27 +08:00 • committed by Alberto Escolar
commit 0c70a72ac7
9 changed files with 45 additions and 8 deletions
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8
boards/nxp/lpcxpresso55s69/lpcxpresso55s69_lpc55s69_cpu0.dts
View file

@ -149,6 +149,14 @@
zephyr_udc0: &usbhs {
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <5>;
tx-cal-45-dp-ohms = <10>;
tx-cal-45-dm-ohms = <10>;
};
&ctimer0 {

8
boards/nxp/mimxrt1060_evk/mimxrt1060_evk.dts
View file

@ -183,6 +183,14 @@ arduino_i2c: &lpi2c1 {
zephyr_udc0: &usb1 {
status = "okay";
phy_handle = <&usbphy1>;
};
&usbphy1 {
status = "okay";
tx-d-cal = <12>;
tx-cal-45-dp-ohms = <6>;
tx-cal-45-dm-ohms = <6>;
};
&flexpwm2_pwm3 {

8
boards/nxp/mimxrt685_evk/mimxrt685_evk_mimxrt685s_cm33.dts
View file

@ -355,6 +355,14 @@ i2s1: &flexcomm3 {
zephyr_udc0: &usbhs {
status = "okay";
phy_handle = <&usbphy>;
};
&usbphy {
status = "okay";
tx-d-cal = <12>;
tx-cal-45-dp-ohms = <6>;
tx-cal-45-dm-ohms = <6>;
};
&ctimer0 {

1
soc/nxp/imxrt/CMakeLists.txt
View file

@ -39,6 +39,7 @@ endif()
if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX)
zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld)
endif()
if(CONFIG_MEMC)

10
soc/nxp/imxrt/imxrt10xx/soc.c
View file

@ -243,21 +243,27 @@ static ALWAYS_INLINE void clock_init(void)
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && \
(CONFIG_USB_DC_NXP_EHCI || CONFIG_UDC_NXP_EHCI)
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
/* Configure USDHC clock source and divider */

1
soc/nxp/imxrt/imxrt6xx/cm33/CMakeLists.txt
View file

@ -18,6 +18,7 @@ zephyr_library_include_directories(
)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
if(CONFIG_FLASH_MCUX_FLEXSPI_XIP)
zephyr_code_relocate(FILES flash_clock_setup.c LOCATION RAM)

8
soc/nxp/imxrt/imxrt6xx/cm33/soc.c
View file

@ -30,7 +30,7 @@
#include "flash_clock_setup.h"
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
#include "usb_phy.h"
#include "usb.h"
#endif
@ -68,7 +68,7 @@ const clock_audio_pll_config_t g_audioPllConfig = {
};
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
@ -124,7 +124,7 @@ __imx_boot_ivt_section void (* const image_vector_table[])(void) = {
};
#endif /* CONFIG_NXP_IMXRT_BOOT_HEADER */
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
static void usb_device_clock_init(void)
{
@ -244,7 +244,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_AttachClk(kSFRO_to_FLEXCOMM0);
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
usb_device_clock_init();
#endif

3
soc/nxp/lpc/lpc55xxx/CMakeLists.txt
View file

@ -14,8 +14,11 @@ zephyr_library_include_directories(
if(DEFINED CONFIG_LPC55XXX_USB_RAM)
zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER
SECTIONS usb.ld)
zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER
SECTIONS usb.ld)
zephyr_compile_definitions_ifdef(CONFIG_USB_DEVICE_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
zephyr_compile_definitions_ifdef(CONFIG_UDC_DRIVER USB_STACK_USE_DEDICATED_RAM=1)
endif()
# CMSIS SystemInit allows us to skip enabling clock to SRAM banks via

6
soc/nxp/lpc/lpc55xxx/soc.c
View file

@ -26,7 +26,7 @@
#ifdef CONFIG_GPIO_MCUX_LPC
#include <fsl_pint.h>
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
#include "usb_phy.h"
#include "usb.h"
#endif
@ -207,7 +207,7 @@ static ALWAYS_INLINE void clock_init(void)
CLOCK_EnableClock(kCLOCK_Mailbox);
#endif
#if CONFIG_USB_DC_NXP_LPCIP3511
#if CONFIG_USB_DC_NXP_LPCIP3511 || CONFIG_UDC_NXP_IP3511
#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(usbfs), nxp_lpcip3511, okay)
/*< Turn on USB Phy */
@ -256,7 +256,9 @@ static ALWAYS_INLINE void clock_init(void)
/* enable USB IP clock */
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_UsbPhySrcExt, CLK_CLK_IN);
CLOCK_EnableUsbhs0DeviceClock(kCLOCK_UsbSrcUnused, 0U);
#if CONFIG_USB_DC_NXP_LPCIP3511
USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, CLK_CLK_IN, NULL);
#endif
#if defined(FSL_FEATURE_USBHSD_USB_RAM) && (FSL_FEATURE_USBHSD_USB_RAM)
memset((uint8_t *)FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS, 0, FSL_FEATURE_USBHSD_USB_RAM);
#endif