diff --git a/drivers/serial/uart_stm32.c b/drivers/serial/uart_stm32.c
index f2c05da357e..edaff82e033 100644
--- a/drivers/serial/uart_stm32.c
+++ b/drivers/serial/uart_stm32.c
@@ -1956,6 +1956,12 @@ static int uart_stm32_registers_configure(const struct device *dev)
 	}
 #endif
 
+#ifdef USART_CR1_FIFOEN
+	if (config->fifo_enable) {
+		LL_USART_EnableFIFO(config->usart);
+	}
+#endif
+
 	LL_USART_Enable(config->usart);
 
 #ifdef USART_ISR_TEACK
@@ -2334,6 +2340,7 @@ static const struct uart_stm32_config uart_stm32_cfg_##index = {	\
 	.de_assert_time = DT_INST_PROP(index, de_assert_time),		\
 	.de_deassert_time = DT_INST_PROP(index, de_deassert_time),	\
 	.de_invert = DT_INST_PROP(index, de_invert),			\
+	.fifo_enable = DT_INST_PROP(index, fifo_enable),		\
 	STM32_UART_IRQ_HANDLER_FUNC(index)				\
 	STM32_UART_PM_WAKEUP(index)					\
 };									\
diff --git a/drivers/serial/uart_stm32.h b/drivers/serial/uart_stm32.h
index ed8e8584cd6..7c6f432a504 100644
--- a/drivers/serial/uart_stm32.h
+++ b/drivers/serial/uart_stm32.h
@@ -49,6 +49,8 @@ struct uart_stm32_config {
 	uint8_t de_deassert_time;
 	/* enable de pin inversion */
 	bool de_invert;
+	/* enable fifo */
+	bool fifo_enable;
 	/* pin muxing */
 	const struct pinctrl_dev_config *pcfg;
 #if defined(CONFIG_UART_INTERRUPT_DRIVEN) || defined(CONFIG_UART_ASYNC_API) || \
diff --git a/dts/bindings/serial/st,stm32-uart-base.yaml b/dts/bindings/serial/st,stm32-uart-base.yaml
index ed8a6e1e3a9..230c384906a 100644
--- a/dts/bindings/serial/st,stm32-uart-base.yaml
+++ b/dts/bindings/serial/st,stm32-uart-base.yaml
@@ -86,3 +86,13 @@ properties:
     description: |
       Invert the binary logic of the de pin. When enabled, physical logic levels are inverted and
       we use 1=Low, 0=High instead of 1=High, 0=Low.
+
+  fifo-enable:
+    type: boolean
+    description: |
+      Enables transmit and receive FIFO using default FIFO confugration (typically threasholds
+      set to 1/8).
+      In TX, FIFO allows to work in burst mode, easing scheduling of loaded applications. It also
+      allows more reliable communication with UART devices sensitive to variation of inter-frames
+      delays.
+      In RX, FIFO reduces overrun occurences.