diff --git a/arch/nios2/core/cache.c b/arch/nios2/core/cache.c
index bcaa9dbc56d..48cea3dfe8a 100644
--- a/arch/nios2/core/cache.c
+++ b/arch/nios2/core/cache.c
@@ -31,12 +31,12 @@
  * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more
  * information on cache considerations.
  */
-#if NIOS2_ICACHE_SIZE > 0
+#if ALT_CPU_ICACHE_SIZE > 0
 void _nios2_icache_flush_all(void)
 {
 	uint32_t i;
 
-	for (i = 0; i < NIOS2_ICACHE_SIZE; i += NIOS2_ICACHE_LINE_SIZE) {
+	for (i = 0; i < ALT_CPU_ICACHE_SIZE; i += ALT_CPU_ICACHE_LINE_SIZE) {
 		_nios2_icache_flush(i);
 	}
 
@@ -60,12 +60,12 @@ void _nios2_icache_flush_all(void)
  * See Chapter 9 of the Nios II Gen 2 Software Developer's Handbook for more
  * information on cache considerations.
  */
-#if NIOS2_DCACHE_SIZE > 0
+#if ALT_CPU_DCACHE_SIZE > 0
 void _nios2_dcache_flush_all(void)
 {
 	uint32_t i;
 
-	for (i = 0; i < NIOS2_DCACHE_SIZE; i += NIOS2_DCACHE_LINE_SIZE) {
+	for (i = 0; i < ALT_CPU_DCACHE_SIZE; i += ALT_CPU_DCACHE_LINE_SIZE) {
 		_nios2_dcache_flush(i);
 	}
 }
diff --git a/arch/nios2/core/crt0.S b/arch/nios2/core/crt0.S
index 4648eef7a98..c886e1f8432 100644
--- a/arch/nios2/core/crt0.S
+++ b/arch/nios2/core/crt0.S
@@ -43,7 +43,7 @@ GTEXT(_interrupt_stack)
  */
 SECTION_FUNC(reset, __reset)
 
-#if NIOS2_ICACHE_SIZE > 0
+#if ALT_CPU_ICACHE_SIZE > 0
 	/* Aside from the instruction cache line associated with the reset
 	 * vector, the contents of the cache memories are indeterminate after
 	 * reset. To ensure cache coherency after reset, the reset handler
@@ -53,23 +53,23 @@ SECTION_FUNC(reset, __reset)
 	 *
 	 * The cache memory sizes are *always* a power of 2.
 	 */
-#if NIOS2_ICACHE_SIZE > 0x8000
-	movhi r2, %hi(NIOS2_ICACHE_SIZE)
+#if ALT_CPU_ICACHE_SIZE > 0x8000
+	movhi r2, %hi(ALT_CPU_ICACHE_SIZE)
 #else
-	movui r2, NIOS2_ICACHE_SIZE
+	movui r2, ALT_CPU_ICACHE_SIZE
 #endif
 0:
 	/* If ECC present, need to execute initd for each word address
 	 * to ensure ECC parity bits in data RAM get initialized
 	 */
-#if NIOS2_ECC_PRESENT
+#ifdef ALT_CPU_ECC_PRESENT
 	subi r2, r2, 4
 #else
-	subi r2, r2, NIOS2_ICACHE_LINE_SIZE
+	subi r2, r2, ALT_CPU_ICACHE_LINE_SIZE
 #endif
 	initi r2
 	bgt r2, zero, 0b
-#endif /* NIOS2_ICACHE_SIZE > 0 */
+#endif /* ALT_CPU_ICACHE_SIZE > 0 */
 
 	/* Done all we need to do here, jump to __text_start */
 	movhi r1, %hi(__start)
@@ -90,25 +90,25 @@ SECTION_FUNC(TEXT, __start)
 	 * we're not booting from our reset vector, either by a bootloader
 	 * or JTAG, assume caches already initialized.
 	 */
-#if NIOS2_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR)
+#if ALT_CPU_DCACHE_SIZE > 0 && defined(CONFIG_INCLUDE_RESET_VECTOR)
 	/* Per documentation data cache size is always a power of two. */
-#if NIOS2_DCACHE_SIZE > 0x8000
-	movhi r2, %hi(NIOS2_DCACHE_SIZE)
+#if ALT_CPU_DCACHE_SIZE > 0x8000
+	movhi r2, %hi(ALT_CPU_DCACHE_SIZE)
 #else
-	movui r2, NIOS2_DCACHE_SIZE
+	movui r2, ALT_CPU_DCACHE_SIZE
 #endif
 0:
 	/* If ECC present, need to execute initd for each word address
 	 * to ensure ECC parity bits in data RAM get initialized
 	 */
-#if NIOS2_ECC_PRESENT
+#ifdef ALT_CPU_ECC_PRESENT
 	subi r2, r2, 4
 #else
-	subi r2, r2, NIOS2_DCACHE_LINE_SIZE
+	subi r2, r2, ALT_CPU_DCACHE_LINE_SIZE
 #endif
 	initd 0(r2)
 	bgt r2, zero, 0b
-#endif /* NIOS2_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */
+#endif /* ALT_CPU_DCACHE_SIZE && defined(CONFIG_INCLUDE_RESET_VECTOR) */
 
 #ifdef CONFIG_INIT_STACKS
 	/* Pre-populate all bytes in _interrupt_stack with 0xAA */
diff --git a/arch/nios2/core/fatal.c b/arch/nios2/core/fatal.c
index 0403e3c6559..e3589710db5 100644
--- a/arch/nios2/core/fatal.c
+++ b/arch/nios2/core/fatal.c
@@ -109,7 +109,7 @@ FUNC_NORETURN void _Fault(const NANO_ESF *esf)
 {
 #ifdef CONFIG_PRINTK
 	/* Unfortunately, completely unavailable on Nios II/e cores */
-#ifdef NIOS2_HAS_EXTRA_EXCEPTION_INFO
+#ifdef ALT_CPU_HAS_EXTRA_EXCEPTION_INFO
 	uint32_t exc_reg, badaddr_reg, eccftl;
 	enum nios2_exception_cause cause;
 
@@ -126,7 +126,7 @@ FUNC_NORETURN void _Fault(const NANO_ESF *esf)
 		badaddr_reg = _nios2_creg_read(NIOS2_CR_BADADDR);
 		printk("Badaddr: 0x%x\n", badaddr_reg);
 	}
-#endif /* NIOS2_HAS_EXTRA_EXCEPTION_INFO */
+#endif /* ALT_CPU_HAS_EXTRA_EXCEPTION_INFO */
 #endif /* CONFIG_PRINTK */
 
 	_NanoFatalErrorHandler(_NANO_ERR_CPU_EXCEPTION, esf);
@@ -181,7 +181,7 @@ FUNC_NORETURN void _SysFatalErrorHandler(unsigned int reason,
 		       ? "ISR"
 		       : curCtx == NANO_CTX_FIBER ? "essential fiber"
 						  : "essential task");
-#ifdef NIOS2_HAS_DEBUG_STUB
+#ifdef ALT_CPU_HAS_DEBUG_STUB
 	_nios2_break();
 #endif
 	for (;;)
diff --git a/arch/nios2/core/prep_c.c b/arch/nios2/core/prep_c.c
index c6176491698..c5f896820a3 100644
--- a/arch/nios2/core/prep_c.c
+++ b/arch/nios2/core/prep_c.c
@@ -50,7 +50,7 @@ void _PrepC(void)
 	 * to flush instruction cache.
 	 */
 	_nios2_icache_flush_all();
-#if NIOS2_ICACHE_SIZE > 0
+#if ALT_CPU_ICACHE_SIZE > 0
 	/* Only need to flush the data cache here if there actually is an
 	 * instruction cache, so that the cached instruction data written is
 	 * actually committed.
diff --git a/arch/nios2/core/swap.S b/arch/nios2/core/swap.S
index c659db333ef..898f22f0510 100644
--- a/arch/nios2/core/swap.S
+++ b/arch/nios2/core/swap.S
@@ -108,10 +108,10 @@ BRANCH_LABEL(next_chosen)
 	 * key was supplied as argument to _Swap()
 	 */
 	ldw r3, __tTCS_coopReg_OFFSET + __t_coop_key_OFFSET(r11)
-#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || \
-		(defined NIOS2_EIC_PRESENT) || \
-		(defined NIOS2_MMU_PRESENT) || \
-		(defined NIOS2_MPU_PRESENT)
+#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
+		(defined ALT_CPU_EIC_PRESENT) || \
+		(defined ALT_CPU_MMU_PRESENT) || \
+		(defined ALT_CPU_MPU_PRESENT)
 	andi r3, r3, NIOS2_STATUS_PIE_MSK
 	beq r3, zero, no_unlock
 	rdctl r3, status
diff --git a/arch/nios2/include/nano_private.h b/arch/nios2/include/nano_private.h
index 2e42452380b..fecb29c8b6c 100644
--- a/arch/nios2/include/nano_private.h
+++ b/arch/nios2/include/nano_private.h
@@ -200,13 +200,13 @@ static ALWAYS_INLINE int _IS_IN_ISR(void)
 void _irq_do_offload(void);
 #endif
 
-#if NIOS2_ICACHE_SIZE > 0
+#if ALT_CPU_ICACHE_SIZE > 0
 void _nios2_icache_flush_all(void);
 #else
 #define _nios2_icache_flush_all() do { } while (0)
 #endif
 
-#if NIOS2_DCACHE_SIZE > 0
+#if ALT_CPU_DCACHE_SIZE > 0
 void _nios2_dcache_flush_all(void);
 #else
 #define _nios2_dcache_flush_all() do { } while (0)
diff --git a/include/arch/nios2/arch.h b/include/arch/nios2/arch.h
index 1ed73e76546..19737ff4ad4 100644
--- a/include/arch/nios2/arch.h
+++ b/include/arch/nios2/arch.h
@@ -114,10 +114,10 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
 	 * specifically flip just that bit.
 	 */
 
-#if (NIOS2_NUM_OF_SHADOW_REG_SETS > 0) || \
-		(defined NIOS2_EIC_PRESENT) || \
-		(defined NIOS2_MMU_PRESENT) || \
-		(defined NIOS2_MPU_PRESENT)
+#if (ALT_CPU_NUM_OF_SHADOW_REG_SETS > 0) || \
+		(defined ALT_CPU_EIC_PRESENT) || \
+		(defined ALT_CPU_MMU_PRESENT) || \
+		(defined ALT_CPU_MPU_PRESENT)
 	uint32_t status_reg;
 
 	/* Interrupts were already locked when irq_lock() was called,