boards nrf_bsim: Add a new nrf54l15bsim target

Add a new simulated nrf54l15 cpuapp target

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>

boards/native/doc/bsim_boards_design.rst

@@ -7,6 +7,7 @@ Bsim boards
 
 * :ref:`Simulated nRF52833 (nrf52_bsim)<nrf52_bsim>`
 * :ref:`Simulated nRF5340 (nrf5340bsim)<nrf5340bsim>`
+* :ref:`Simulated nRF54L15 (nrf54l15bsim)<nrf54l15bsim>`
 
 .. contents:: Table of contents
    :depth: 2
@@ -20,8 +21,8 @@ These boards are postfixed with `_bsim` as they use BabbleSim_
 These boards use the `native simulator`_ and the :ref:`POSIX architecture<Posix arch>` to build
 and execute the embedded code natively on Linux.
 
-Particular details on the :ref:`nRF52<nrf52_bsim>` and :ref:`nRF5340<nrf5340bsim>`
-simulation boards, including how to use them,
+Particular details on the :ref:`nRF52<nrf52_bsim>`, :ref:`nRF5340<nrf5340bsim>` and
+:ref:`nRF54l15<nrf54l15bsim>` simulation boards, including how to use them,
 can be found in their respective documentation.
 
 .. _BabbleSim:

boards/native/nrf_bsim/Kconfig

@@ -34,6 +34,17 @@ config BOARD_NRF5340BSIM_NRF5340_CPUAPP
 	  Will produce a console Linux process which can be executed natively.
 	  It needs the BabbleSim simulator both in compile time and to execute
 
+config BOARD_NRF54L15BSIM_NRF54L15_CPUAPP
+	bool
+	select SOC_SERIES_BSIM_NRF54LX
+	select SOC_COMPATIBLE_NRF54L15
+	select SOC_COMPATIBLE_NRF54L15_CPUAPP
+	select CLOCK_CONTROL
+	help
+	  Simulated NRF54L15 Application core
+	  Will produce a console Linux process which can be executed natively.
+	  It needs the BabbleSim simulator both in compile time and to execute
+
 
 if SOC_SERIES_BSIM_NRFXX
 
@@ -76,6 +87,13 @@ config SOC_SERIES_BSIM_NRF53X
 	help
 	  Any NRF53 simulated SOC with BabbleSim, based on the POSIX arch
 
+config SOC_SERIES_BSIM_NRF54LX
+	bool
+	select SOC_SERIES_BSIM_NRFXX
+	select SOC_COMPATIBLE_NRF54LX
+	help
+	  Any NRF54L simulated SOC with BabbleSim, based on the POSIX arch
+
 if BOARD_NRF5340BSIM_NRF5340_CPUAPP
 
 # Replica of the option provided by the BOARD_NRF5340DK_NRF5340_CPUAPP board so samples can be

boards/native/nrf_bsim/Kconfig.defconfig

@@ -30,10 +30,12 @@ config NATIVE_SIMULATOR_PRIMARY_MCU_INDEX
 	default 0
 
 config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 1000000 if NRF_GRTC_TIMER
 	default 32768
 
 config SYS_CLOCK_TICKS_PER_SEC
 	default 128 if !TICKLESS_KERNEL
+	default 10000 if NRF_GRTC_TIMER
 	default 32768
 
 config BT_CTLR

boards/native/nrf_bsim/Kconfig.nrf54l15bsim

@@ -0,0 +1,5 @@
+# Copyright (c) 2024 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_NRF54L15BSIM
+	select SOC_POSIX

boards/native/nrf_bsim/board.yml

@@ -6,6 +6,10 @@ boards:
 - name: nrf5340bsim
   vendor: zephyr
   socs:
-  # Note this is referring to the real SOC yaml, but we only use its name and cpu-cluster definition
-  # In practice this board uses the same native SOC (SOC_POSIX) as the nrf52_bsim
   - name: nrf5340
+- name: nrf54l15bsim
+  vendor: zephyr
+  socs:
+  - name: nrf54l15
+# Note the 53 and 54 are referring to the real SOC yamls, but we only use their name and cpu-cluster
+# definitions. In practice these board uses the same native SOC (SOC_POSIX) as the nrf52_bsim

boards/native/nrf_bsim/board_soc.h

@@ -31,12 +31,15 @@
 #include "cmsis.h"
 #include "soc_nrf_common.h"
 
+/* For offloading interrupts we can use any free interrupt */
 #if defined(CONFIG_BOARD_NRF52_BSIM)
 #define OFFLOAD_SW_IRQ SWI0_EGU0_IRQn
 #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUAPP)
 #define OFFLOAD_SW_IRQ EGU0_IRQn
 #elif defined(CONFIG_BOARD_NRF5340BSIM_NRF5340_CPUNET)
 #define OFFLOAD_SW_IRQ SWI0_IRQn
+#elif defined(CONFIG_BOARD_NRF54L15BSIM)
+#define OFFLOAD_SW_IRQ SWI00_IRQn
 #endif
 
 #define FLASH_PAGE_ERASE_MAX_TIME_US	89700UL

boards/native/nrf_bsim/doc/nrf54l15bsim.rst

@@ -0,0 +1,86 @@
+.. _nrf54l15bsim:
+
+NRF54L15 simulated boards (BabbleSim)
+#####################################
+
+.. contents::
+   :depth: 1
+   :backlinks: entry
+   :local:
+
+
+Overview
+********
+
+To allow simulating nRF54L15 SOCs a Zephyr target boards is provided: the
+``nrf54l15bsim/nrf54l15/cpuapp``.
+
+This uses `BabbleSim`_ to simulate the radio activity, and the
+:ref:`POSIX architecture<Posix arch>` and the `native simulator`_ to
+run applications natively on the development system. This has the benefit of
+providing native code execution performance and easy debugging using
+native tools, but inherits :ref:`its limitations <posix_arch_limitations>`.
+
+Just like for the nrf54l15pdk target,
+the nrf54l15bsim/nrf54l15/cpuapp build target provides support for the application core,
+on the simulated nRF54L15 SOC.
+
+.. note::
+
+   This simulated target does **not** yet support targeting the cpuflpr core.
+
+.. warning::
+
+   This target is experimental, and does not yet include models of the RADIO peripheral,
+   so the BLE and 802.15.4 stacks cannot be run on it yet.
+
+This boards include models of some of the nRF54L15 SOC peripherals:
+
+* DPPI (Distributed Programmable Peripheral Interconnect)
+* EGU (Event Generator Unit)
+* GRTC (Global Real-time Counter)
+* PPIB (PPI Bridge)
+* RTC (Real Time Counter)
+* TEMP (Temperature sensor)
+* TIMER
+
+and will use the same drivers as the nrf54l15pdk targets for these.
+For more information on what is modeled to which level of detail,
+check the `HW models implementation status`_.
+
+Note that unlike a real nrf54l15 device, the nrf54l15bsim boards have unlimited RAM and flash for
+code.
+
+.. _BabbleSim:
+   https://BabbleSim.github.io
+
+.. _native simulator:
+   https://github.com/BabbleSim/native_simulator/blob/main/docs/README.md
+
+.. _HW models implementation status:
+   https://github.com/BabbleSim/ext_nRF_hw_models/blob/main/docs/README_impl_status.md
+
+
+Building for, and using this board
+**********************************
+
+You can follow the instructions from the :ref:`nrf52_bsim board <nrf52bsim_build_and_run>`.
+Simply change the board/target appropriately when building.
+
+
+TrustZone, TF-M and other security considerations
+*************************************************
+
+ARM's TrustZone is not modeled in this board. This means that:
+
+* There is no differentiation between secure and non secure execution states or bus accesses.
+* All RAM, flash and peripherals are in principle accessible from all SW. Peripherals with their
+  own interconnect master ports can, in principle, access any other peripheral or RAM area.
+* There is no nrf54l15bsim/nrf54l15/cpuapp/ns board/build target, or possibility of mixing secure
+  and non-secure images.
+* Currently there is no model of the SPU, and therefore neither RRAM, RAM areas or peripherals
+  can be labeled as restricted for secure or non secure access.
+* TF-M cannot be used.
+
+Note that the CRACEN peripheral is not modeled. The mbedTLS library can still be used
+but with a SW crypto backend.

boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.dts

@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2024 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <mem.h>
+#include <arm/nordic/nrf54l15_cpuapp.dtsi>
+
+/ {
+	model = "Nordic NRF54L15 BSIM NRF54L15 Application";
+	compatible = "bsim,nrf54l15-bsim-nrf54l15-cpuapp", "bsim,nrf54";
+
+	chosen {
+	};
+
+	/delete-node/ cpus;
+	/delete-node/ clocks;
+	/delete-node/ sw-pwm;
+
+	soc {
+		/delete-node/ uicr@ffd000;
+		/delete-node/ ficr@ffc000;
+		/delete-node/ memory@20000000;
+		/delete-node/ memory@2002f000;
+		peripheral@50000000 {
+			/delete-node/ spi@4a000;
+			/delete-node/ uart@4a000;
+			/delete-node/ vpr@4c000;
+			/delete-node/ mailbox@0;
+			/delete-node/ interrupt-controller@f0000000;
+			/delete-node/ gpio@50400;
+			/delete-node/ radio@8a000;
+			/delete-node/ i2c@c6000;
+			/delete-node/ spi@c6000;
+			/delete-node/ uart@c6000;
+			/delete-node/ i2c@c7000;
+			/delete-node/ spi@c7000;
+			/delete-node/ uart@c7000;
+			/delete-node/ i2c@c8000;
+			/delete-node/ spi@c8000;
+			/delete-node/ uart@c8000;
+			/delete-node/ pwm@d2000;
+			/delete-node/ pwm@d3000;
+			/delete-node/ pwm@d4000;
+			/delete-node/ adc@d5000;
+			/delete-node/ nfct@d6000;
+			/delete-node/ gpio@d8200;
+			/delete-node/ gpiote@da000;
+			/delete-node/ i2s@dd000;
+			/delete-node/ qdec@e0000;
+			/delete-node/ qdec@e1000;
+			/delete-node/ i2c@104000;
+			/delete-node/ spi@104000;
+			/delete-node/ uart@104000;
+			/delete-node/ watchdog@108000;
+			/delete-node/ watchdog@109000;
+			/delete-node/ gpio@10a000;
+			/delete-node/ gpiote@10c000;
+			/delete-node/ clock@10e000;
+		};
+		/delete-node/ rram-controller@5004b000;
+		/delete-node/ spu@50003000;
+		/delete-node/ gpiote@5000d000;
+		/delete-node/ crypto@50844000;
+	};
+};
+
+&grtc {
+	owned-channels = <0 1 2 3 4 5 6 7 8 9 10 11>;
+	/* Channels 7-11 reserved for Zero Latency IRQs, 3-4 for FLPR */
+	child-owned-channels = <3 4 7 8 9 10 11>;
+	status = "okay";
+};
+
+&temp {
+	status = "okay";
+};

boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp.yaml

@@ -0,0 +1,15 @@
+identifier: nrf54l15bsim/nrf54l15/cpuapp
+name: NRF54L15 BabbleSim - Application Core target
+type: native
+arch: posix
+simulation: native
+env:
+  - BSIM_OUT_PATH
+toolchain:
+  - zephyr
+testing:
+  ignore_tags:
+    - gpio
+    - modem
+    - uart
+    - bsim_skip_CI

boards/native/nrf_bsim/nrf54l15bsim_nrf54l15_cpuapp_defconfig

@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: Apache-2.0
+# Copyright (c) 2023 Nordic Semiconductor ASA
+
+CONFIG_CONSOLE=y
+CONFIG_NO_OPTIMIZATIONS=y
+
+# Start SYSCOUNTER on driver init
+CONFIG_NRF_GRTC_START_SYSCOUNTER=y