drivers: i2s: code refactor
Declaration code for the I2S devices in the driver has too much duplicate code. This commit uses a help macro to save some work and some lines of code. Signed-off-by: Song Qiang <songqiang1304521@gmail.com>
This commit is contained in:
Song Qiang
Kumar Gala
parent
ff3889a051
commit
0b11de57cd
1 changed files with 59 additions and 334 deletions
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@ -818,352 +818,77 @@ static struct device *get_dev_from_tx_dma_channel(u32_t dma_channel)
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return active_dma_tx_channel[dma_channel];
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return active_dma_tx_channel[dma_channel];
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}
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}
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#ifdef CONFIG_I2S_1
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#define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap) \
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static struct device DEVICE_NAME_GET(i2s_stm32_1);
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.dir = { \
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.dma_channel = I2S##index##_DMA_CHAN_##dir_cap, \
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static void i2s_stm32_irq_config_func_1(struct device *dev);
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.dma_cfg = { \
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.block_count = 1, \
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static const struct i2s_stm32_cfg i2s_stm32_config_1 = {
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.dma_slot = I2S##index##_DMA_SLOT_##dir_cap, \
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.i2s = (SPI_TypeDef *) DT_I2S_1_BASE_ADDRESS,
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.channel_direction = PERIPHERAL_TO_MEMORY, \
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.pclken = {
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.source_data_size = 1, /* 16bit default */ \
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.enr = DT_I2S_1_CLOCK_BITS,
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.dest_data_size = 1, /* 16bit default */ \
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.bus = DT_I2S_1_CLOCK_BUS,
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.source_burst_length = 0, /* SINGLE transfer */ \
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},
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.dest_burst_length = 1, \
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.i2s_clk_sel = CLK_SEL_2,
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.dma_callback = dma_##dir##_callback, \
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.irq_config = i2s_stm32_irq_config_func_1,
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}, \
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};
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.stream_start = dir##_stream_start, \
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.stream_disable = dir##_stream_disable, \
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struct queue_item rx_1_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
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.queue_drop = dir##_queue_drop, \
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struct queue_item tx_1_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];
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.mem_block_queue.buf = dir##_##index##_ring_buf, \
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.mem_block_queue.len = ARRAY_SIZE(dir##_##index##_ring_buf), \
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static struct i2s_stm32_data i2s_stm32_data_1 = {
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.dma_name = I2S1_DMA_NAME,
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.rx = {
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.dma_channel = I2S1_DMA_CHAN_RX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S1_DMA_SLOT_RX,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 0, /* SINGLE transfer */
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.dest_burst_length = 1,
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.dma_callback = dma_rx_callback,
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},
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.stream_start = rx_stream_start,
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.stream_disable = rx_stream_disable,
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.queue_drop = rx_queue_drop,
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.mem_block_queue.buf = rx_1_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(rx_1_ring_buf),
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},
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.tx = {
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.dma_channel = I2S1_DMA_CHAN_TX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S1_DMA_SLOT_TX,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 1,
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.dest_burst_length = 0, /* SINGLE transfer */
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.dma_callback = dma_tx_callback,
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},
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.stream_start = tx_stream_start,
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.stream_disable = tx_stream_disable,
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.queue_drop = tx_queue_drop,
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.mem_block_queue.buf = tx_1_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(tx_1_ring_buf),
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},
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};
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DEVICE_AND_API_INIT(i2s_stm32_1, DT_I2S_1_NAME, &i2s_stm32_initialize,
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&i2s_stm32_data_1, &i2s_stm32_config_1, POST_KERNEL,
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CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
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static void i2s_stm32_irq_config_func_1(struct device *dev)
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{
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IRQ_CONNECT(DT_I2S_1_IRQ, DT_I2S_1_IRQ_PRI, i2s_stm32_isr,
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DEVICE_GET(i2s_stm32_1), 0);
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irq_enable(DT_I2S_1_IRQ);
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}
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}
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#define I2S_INIT(index, clk_sel) \
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static struct device DEVICE_NAME_GET(i2s_stm32_##index); \
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\
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static void i2s_stm32_irq_config_func_##index(struct device *dev); \
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\
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static const struct i2s_stm32_cfg i2s_stm32_config_##index = { \
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.i2s = (SPI_TypeDef *) DT_I2S_##index##_BASE_ADDRESS, \
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.pclken = { \
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.enr = DT_I2S_##index##_CLOCK_BITS, \
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.bus = DT_I2S_##index##_CLOCK_BUS, \
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}, \
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.i2s_clk_sel = CLK_SEL_##clk_sel, \
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.irq_config = i2s_stm32_irq_config_func_##index, \
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}; \
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\
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struct queue_item rx_##index##_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];\
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struct queue_item tx_##index##_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];\
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\
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static struct i2s_stm32_data i2s_stm32_data_##index = { \
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.dma_name = I2S##index##_DMA_CHAN_RX, \
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I2S_DMA_CHANNEL_INIT(index, rx, RX), \
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I2S_DMA_CHANNEL_INIT(index, tx, TX), \
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}; \
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DEVICE_AND_API_INIT(i2s_stm32_##index, DT_I2S_##index##_NAME, \
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&i2s_stm32_initialize, &i2s_stm32_data_##index, \
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&i2s_stm32_config_##index, POST_KERNEL, \
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CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api); \
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\
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static void i2s_stm32_irq_config_func_##index(struct device *dev) \
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{ \
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IRQ_CONNECT(DT_I2S_##index##_IRQ, DT_I2S_##index##_IRQ_PRI, \
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i2s_stm32_isr, DEVICE_GET(i2s_stm32_##index), 0); \
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irq_enable(DT_I2S_##index##_IRQ); \
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}
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#ifdef CONFIG_I2S_1
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I2S_INIT(1, 2)
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#endif /* CONFIG_I2S_1 */
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#endif /* CONFIG_I2S_1 */
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#ifdef CONFIG_I2S_2
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#ifdef CONFIG_I2S_2
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static struct device DEVICE_NAME_GET(i2s_stm32_2);
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I2S_INIT(2, 1)
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static void i2s_stm32_irq_config_func_2(struct device *dev);
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static const struct i2s_stm32_cfg i2s_stm32_config_2 = {
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.i2s = (SPI_TypeDef *) DT_I2S_2_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2S_2_CLOCK_BITS,
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.bus = DT_I2S_2_CLOCK_BUS,
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},
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.i2s_clk_sel = CLK_SEL_1,
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.irq_config = i2s_stm32_irq_config_func_2,
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};
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struct queue_item rx_2_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
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struct queue_item tx_2_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];
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static struct i2s_stm32_data i2s_stm32_data_2 = {
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.dma_name = I2S2_DMA_NAME,
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.rx = {
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.dma_channel = I2S2_DMA_CHAN_RX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S2_DMA_SLOT_RX,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 0, /* SINGLE transfer */
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.dest_burst_length = 1,
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.dma_callback = dma_rx_callback,
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},
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.stream_start = rx_stream_start,
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.stream_disable = rx_stream_disable,
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.queue_drop = rx_queue_drop,
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.mem_block_queue.buf = rx_2_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(rx_2_ring_buf),
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},
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.tx = {
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.dma_channel = I2S2_DMA_CHAN_TX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S2_DMA_SLOT_TX,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 1,
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.dest_burst_length = 0, /* SINGLE transfer */
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.dma_callback = dma_tx_callback,
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},
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.stream_start = tx_stream_start,
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.stream_disable = tx_stream_disable,
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.queue_drop = tx_queue_drop,
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.mem_block_queue.buf = tx_2_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(tx_2_ring_buf),
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},
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};
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DEVICE_AND_API_INIT(i2s_stm32_2, DT_I2S_2_NAME, &i2s_stm32_initialize,
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&i2s_stm32_data_2, &i2s_stm32_config_2, POST_KERNEL,
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CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
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static void i2s_stm32_irq_config_func_2(struct device *dev)
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{
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IRQ_CONNECT(DT_I2S_2_IRQ, DT_I2S_2_IRQ_PRI, i2s_stm32_isr,
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DEVICE_GET(i2s_stm32_2), 0);
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irq_enable(DT_I2S_2_IRQ);
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}
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#endif /* CONFIG_I2S_2 */
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#endif /* CONFIG_I2S_2 */
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#ifdef CONFIG_I2S_3
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#ifdef CONFIG_I2S_3
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static struct device DEVICE_NAME_GET(i2s_stm32_3);
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I2S_INIT(3, 1)
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static void i2s_stm32_irq_config_func_3(struct device *dev);
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static const struct i2s_stm32_cfg i2s_stm32_config_3 = {
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.i2s = (SPI_TypeDef *) DT_I2S_3_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2S_3_CLOCK_BITS,
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.bus = DT_I2S_3_CLOCK_BUS,
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},
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.i2s_clk_sel = CLK_SEL_1,
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.irq_config = i2s_stm32_irq_config_func_3,
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};
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struct queue_item rx_3_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
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struct queue_item tx_3_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];
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static struct i2s_stm32_data i2s_stm32_data_3 = {
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.dma_name = I2S3_DMA_NAME,
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.rx = {
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.dma_channel = I2S3_DMA_CHAN_RX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S3_DMA_SLOT_RX,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 0, /* SINGLE transfer */
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.dest_burst_length = 1,
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.dma_callback = dma_rx_callback,
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},
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.stream_start = rx_stream_start,
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.stream_disable = rx_stream_disable,
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.queue_drop = rx_queue_drop,
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.mem_block_queue.buf = rx_3_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(rx_3_ring_buf),
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},
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.tx = {
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.dma_channel = I2S3_DMA_CHAN_TX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S3_DMA_SLOT_TX,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 1,
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.dest_burst_length = 0, /* SINGLE transfer */
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.dma_callback = dma_tx_callback,
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},
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.stream_start = tx_stream_start,
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.stream_disable = tx_stream_disable,
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.queue_drop = tx_queue_drop,
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.mem_block_queue.buf = tx_3_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(tx_3_ring_buf),
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},
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};
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DEVICE_AND_API_INIT(i2s_stm32_3, DT_I2S_3_NAME, &i2s_stm32_initialize,
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&i2s_stm32_data_3, &i2s_stm32_config_3, POST_KERNEL,
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CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
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static void i2s_stm32_irq_config_func_3(struct device *dev)
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{
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IRQ_CONNECT(DT_I2S_3_IRQ, DT_I2S_3_IRQ_PRI, i2s_stm32_isr,
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DEVICE_GET(i2s_stm32_3), 0);
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irq_enable(DT_I2S_3_IRQ);
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}
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#endif /* CONFIG_I2S_3 */
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#endif /* CONFIG_I2S_3 */
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#ifdef CONFIG_I2S_4
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#ifdef CONFIG_I2S_4
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static struct device DEVICE_NAME_GET(i2s_stm32_4);
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I2S_INIT(4, 2)
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static void i2s_stm32_irq_config_func_4(struct device *dev);
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static const struct i2s_stm32_cfg i2s_stm32_config_4 = {
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.i2s = (SPI_TypeDef *) DT_I2S_4_BASE_ADDRESS,
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.pclken = {
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.enr = DT_I2S_4_CLOCK_BITS,
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.bus = DT_I2S_4_CLOCK_BUS,
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},
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.i2s_clk_sel = CLK_SEL_2,
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.irq_config = i2s_stm32_irq_config_func_4,
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};
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struct queue_item rx_4_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
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struct queue_item tx_4_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];
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static struct i2s_stm32_data i2s_stm32_data_4 = {
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.dma_name = I2S4_DMA_NAME,
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.rx = {
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.dma_channel = I2S4_DMA_CHAN_RX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S4_DMA_SLOT_RX,
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.channel_direction = PERIPHERAL_TO_MEMORY,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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.source_burst_length = 0, /* SINGLE transfer */
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.dest_burst_length = 1,
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.dma_callback = dma_rx_callback,
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},
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.stream_start = rx_stream_start,
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.stream_disable = rx_stream_disable,
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.queue_drop = rx_queue_drop,
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.mem_block_queue.buf = rx_4_ring_buf,
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.mem_block_queue.len = ARRAY_SIZE(rx_4_ring_buf),
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},
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.tx = {
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.dma_channel = I2S4_DMA_CHAN_TX,
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.dma_cfg = {
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.block_count = 1,
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.dma_slot = I2S4_DMA_SLOT_TX,
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.channel_direction = MEMORY_TO_PERIPHERAL,
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.source_data_size = 1, /* 16bit default */
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.dest_data_size = 1, /* 16bit default */
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|
||||||
.source_burst_length = 1,
|
|
||||||
.dest_burst_length = 0, /* SINGLE transfer */
|
|
||||||
.dma_callback = dma_tx_callback,
|
|
||||||
},
|
|
||||||
.stream_start = tx_stream_start,
|
|
||||||
.stream_disable = tx_stream_disable,
|
|
||||||
.queue_drop = tx_queue_drop,
|
|
||||||
.mem_block_queue.buf = tx_4_ring_buf,
|
|
||||||
.mem_block_queue.len = ARRAY_SIZE(tx_4_ring_buf),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
DEVICE_AND_API_INIT(i2s_stm32_4, DT_I2S_4_NAME, &i2s_stm32_initialize,
|
|
||||||
&i2s_stm32_data_4, &i2s_stm32_config_4, POST_KERNEL,
|
|
||||||
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
|
|
||||||
|
|
||||||
static void i2s_stm32_irq_config_func_4(struct device *dev)
|
|
||||||
{
|
|
||||||
IRQ_CONNECT(DT_I2S_4_IRQ, DT_I2S_4_IRQ_PRI, i2s_stm32_isr,
|
|
||||||
DEVICE_GET(i2s_stm32_4), 0);
|
|
||||||
irq_enable(DT_I2S_4_IRQ);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_I2S_4 */
|
#endif /* CONFIG_I2S_4 */
|
||||||
|
|
||||||
#ifdef CONFIG_I2S_5
|
#ifdef CONFIG_I2S_5
|
||||||
static struct device DEVICE_NAME_GET(i2s_stm32_5);
|
I2S_INIT(5, 2)
|
||||||
|
|
||||||
static void i2s_stm32_irq_config_func_5(struct device *dev);
|
|
||||||
|
|
||||||
static const struct i2s_stm32_cfg i2s_stm32_config_5 = {
|
|
||||||
.i2s = (SPI_TypeDef *) DT_I2S_5_BASE_ADDRESS,
|
|
||||||
.pclken = {
|
|
||||||
.enr = DT_I2S_5_CLOCK_BITS,
|
|
||||||
.bus = DT_I2S_5_CLOCK_BUS,
|
|
||||||
},
|
|
||||||
.i2s_clk_sel = CLK_SEL_2,
|
|
||||||
.irq_config = i2s_stm32_irq_config_func_5,
|
|
||||||
};
|
|
||||||
|
|
||||||
struct queue_item rx_5_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];
|
|
||||||
struct queue_item tx_5_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];
|
|
||||||
|
|
||||||
static struct i2s_stm32_data i2s_stm32_data_5 = {
|
|
||||||
.dma_name = I2S5_DMA_NAME,
|
|
||||||
.rx = {
|
|
||||||
.dma_channel = I2S5_DMA_CHAN_RX,
|
|
||||||
.dma_cfg = {
|
|
||||||
.block_count = 1,
|
|
||||||
.dma_slot = I2S5_DMA_SLOT_RX,
|
|
||||||
.channel_direction = PERIPHERAL_TO_MEMORY,
|
|
||||||
.source_data_size = 1, /* 16bit default */
|
|
||||||
.dest_data_size = 1, /* 16bit default */
|
|
||||||
.source_burst_length = 0, /* SINGLE transfer */
|
|
||||||
.dest_burst_length = 1,
|
|
||||||
.dma_callback = dma_rx_callback,
|
|
||||||
},
|
|
||||||
.stream_start = rx_stream_start,
|
|
||||||
.stream_disable = rx_stream_disable,
|
|
||||||
.queue_drop = rx_queue_drop,
|
|
||||||
.mem_block_queue.buf = rx_5_ring_buf,
|
|
||||||
.mem_block_queue.len = ARRAY_SIZE(rx_5_ring_buf),
|
|
||||||
},
|
|
||||||
.tx = {
|
|
||||||
.dma_channel = I2S5_DMA_CHAN_TX,
|
|
||||||
.dma_cfg = {
|
|
||||||
.block_count = 1,
|
|
||||||
.dma_slot = I2S5_DMA_SLOT_TX,
|
|
||||||
.channel_direction = MEMORY_TO_PERIPHERAL,
|
|
||||||
.source_data_size = 1, /* 16bit default */
|
|
||||||
.dest_data_size = 1, /* 16bit default */
|
|
||||||
.source_burst_length = 1,
|
|
||||||
.dest_burst_length = 0, /* SINGLE transfer */
|
|
||||||
.dma_callback = dma_tx_callback,
|
|
||||||
},
|
|
||||||
.stream_start = tx_stream_start,
|
|
||||||
.stream_disable = tx_stream_disable,
|
|
||||||
.queue_drop = tx_queue_drop,
|
|
||||||
.mem_block_queue.buf = tx_5_ring_buf,
|
|
||||||
.mem_block_queue.len = ARRAY_SIZE(tx_5_ring_buf),
|
|
||||||
},
|
|
||||||
};
|
|
||||||
DEVICE_AND_API_INIT(i2s_stm32_5, DT_I2S_5_NAME, &i2s_stm32_initialize,
|
|
||||||
&i2s_stm32_data_5, &i2s_stm32_config_5, POST_KERNEL,
|
|
||||||
CONFIG_I2S_INIT_PRIORITY, &i2s_stm32_driver_api);
|
|
||||||
|
|
||||||
static void i2s_stm32_irq_config_func_5(struct device *dev)
|
|
||||||
{
|
|
||||||
IRQ_CONNECT(DT_I2S_5_IRQ, DT_I2S_5_IRQ_PRI, i2s_stm32_isr,
|
|
||||||
DEVICE_GET(i2s_stm32_5), 0);
|
|
||||||
irq_enable(DT_I2S_5_IRQ);
|
|
||||||
}
|
|
||||||
|
|
||||||
#endif /* CONFIG_I2S_5 */
|
#endif /* CONFIG_I2S_5 */
|
||||||
|
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue