driver: timer: st_stm32: add lptimer management to stm32xx series
This patch introduces the support of the LowPower Timer for the STM32xx from STMicroelectronics. Signed-off-by: Francois Ramu <francois.ramu@st.com>
This commit is contained in:
Francois Ramu
Kumar Gala
parent
c704495807
commit
0ae7023405
6 changed files with 359 additions and 2 deletions
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@ -7,6 +7,7 @@ zephyr_sources_if_kconfig( loapic_timer.c)
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zephyr_sources_if_kconfig( apic_timer.c)
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zephyr_sources_ifdef(CONFIG_ALTERA_AVALON_TIMER altera_avalon_timer_hal.c)
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zephyr_sources_if_kconfig( nrf_rtc_timer.c)
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zephyr_sources_if_kconfig( stm32_lptim_timer.c)
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zephyr_sources_if_kconfig( riscv_machine_timer.c)
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zephyr_sources_if_kconfig( rv32m1_lptmr_timer.c)
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zephyr_sources_if_kconfig( cortex_m_systick.c)
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@ -140,6 +140,8 @@ config NRF_RTC_TIMER
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Counter NRF_RTC1 and provides the standard "system clock driver"
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interfaces.
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source "drivers/timer/Kconfig.stm32_lptim"
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config RISCV_MACHINE_TIMER
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bool "RISCV Machine Timer"
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depends on SOC_FAMILY_RISCV_PRIVILEGE
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44
drivers/timer/Kconfig.stm32_lptim
Normal file
44
drivers/timer/Kconfig.stm32_lptim
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@ -0,0 +1,44 @@
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# Kconfig - STM32 LPTIM configuration options
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#
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# Copyright (c) 2019 STMicroelectronics
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig STM32_LPTIM_TIMER
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bool "STM32 Low Power Timer"
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depends on SOC_SERIES_STM32L4X
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depends on CLOCK_CONTROL
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select TICKLESS_CAPABLE
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help
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This module implements a kernel device driver for the LowPower Timer
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and provides the standard "system clock driver" interfaces.
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if STM32_LPTIM_TIMER
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choice STM32_LPTIM_CLOCK
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prompt "LPTIM clock value configuration"
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config STM32_LPTIM_CLOCK_LSI
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bool "LSI"
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help
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Use LSI as LPTIM clock
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config STM32_LPTIM_CLOCK_LSE
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bool "LSE"
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help
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Use LSE as LPTIM clock
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endchoice
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config STM32_LPTIM_CLOCK
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int "LPTIM clock value"
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default 32000 if STM32_LPTIM_CLOCK_LSI
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default 32768 if STM32_LPTIM_CLOCK_LSE
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config STM32_LPTIM_TIMEBASE
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hex "LPTIM AutoReload value"
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default 0xF9FF if STM32_LPTIM_CLOCK_LSI
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default 0xFFFF if STM32_LPTIM_CLOCK_LSE
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endif # STM32_LPTIM_TIMER
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306
drivers/timer/stm32_lptim_timer.c
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306
drivers/timer/stm32_lptim_timer.c
Normal file
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@ -0,0 +1,306 @@
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/*
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* Copyright (c) 2018 Foundries.io Ltd
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* Copyright (c) 2019 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <drivers/clock_control.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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/*
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* Assumptions and limitations:
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*
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* - system clock based on an LPTIM1 instance, clocked by LSI or LSE
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* - prescaler is set to 1 (LL_LPTIM_PRESCALER_DIV1 in the related register)
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* - using LPTIM1 AutoReload capability to trig the IRQ (timeout irq)
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* - when timeout irq occurs the counter is already reset
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* - the maximum timeout duration is reached with the LPTIM_TIMEBASE value
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* - with prescaler of 1, the max timeout (LPTIM_TIMEBASE) is 2seconds
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*/
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#define LPTIM_CLOCK CONFIG_STM32_LPTIM_CLOCK
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#define LPTIM_TIMEBASE CONFIG_STM32_LPTIM_TIMEBASE
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/* nb of LPTIM counter unit per kernel tick */
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#define COUNT_PER_TICK (LPTIM_CLOCK / CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/* A 32bit value cannot exceed 0xFFFFFFFF/LPTIM_TIMEBASE counting cycles.
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* This is for example about of 65000 x 2000ms when clocked by LSI
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*/
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static u32_t accumulated_lptim_cnt;
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static struct k_spinlock lock;
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static void lptim_irq_handler(struct device *unused)
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{
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ARG_UNUSED(unused);
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if ((LL_LPTIM_IsActiveFlag_ARRM(LPTIM1) != 0)
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&& LL_LPTIM_IsEnabledIT_ARRM(LPTIM1) != 0) {
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* LPTIM1 CNT register is already reset after one autoreload */
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volatile u32_t lp_time = LL_LPTIM_GetCounter(LPTIM1);
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/* It should be noted that to read reliably the content
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* of the LPTIM_CNT register, two successive read accesses
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* must be performed and compared
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*/
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while (lp_time != LL_LPTIM_GetCounter(LPTIM1)) {
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lp_time = LL_LPTIM_GetCounter(LPTIM1);
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}
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lp_time += LL_LPTIM_GetAutoReload(LPTIM1) + 1;
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/* do not change ARR yet, z_clock_announce will do */
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LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
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/* increase the total nb of lptim count
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* used in the z_timer_cycle_get_32() function.
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* Reading the CNT register gives a reliable value
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*/
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accumulated_lptim_cnt += lp_time;
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k_spin_unlock(&lock, key);
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/* announce the elapsed time in ms (count register is 16bit) */
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u32_t dticks = (lp_time
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* CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/ LPTIM_CLOCK;
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z_clock_announce(IS_ENABLED(CONFIG_TICKLESS_KERNEL)
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? dticks : 1);
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}
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}
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int z_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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/* enable LPTIM clock source */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
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LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_LPTIM1);
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#if defined(CONFIG_STM32_LPTIM_CLOCK_LSI)
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/* enable LSI clock */
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#ifdef CONFIG_SOC_SERIES_STM32WBX
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LL_RCC_LSI1_Enable();
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while (!LL_RCC_LSI1_IsReady()) {
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#else
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LL_RCC_LSI_Enable();
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while (!LL_RCC_LSI_IsReady()) {
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#endif /* CONFIG_SOC_SERIES_STM32WBX */
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/* Wait for LSI ready */
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}
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LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_LSI);
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#else /* CONFIG_STM32_LPTIM_CLOCK_LSI */
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#if defined(LL_APB1_GRP1_PERIPH_PWR)
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#endif /* LL_APB1_GRP1_PERIPH_PWR */
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/* enable backup domain */
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LL_PWR_EnableBkUpAccess();
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LL_RCC_ForceBackupDomainReset();
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LL_RCC_ReleaseBackupDomainReset();
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/* enable LSE clock */
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LL_RCC_LSE_DisableBypass();
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LL_RCC_LSE_Enable();
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while (!LL_RCC_LSE_IsReady()) {
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/* Wait for LSE ready */
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}
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LL_RCC_SetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE_LSE);
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#endif /* CONFIG_STM32_LPTIM_CLOCK_LSI */
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/* Clear the event flag and possible pending interrupt */
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IRQ_CONNECT(DT_LPTIM_1_IRQ, DT_LPTIM_1_IRQ_PRI,
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lptim_irq_handler, 0, 0);
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irq_enable(DT_LPTIM_1_IRQ);
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/* configure the LPTIM1 counter */
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LL_LPTIM_SetClockSource(LPTIM1, LL_LPTIM_CLK_SOURCE_INTERNAL);
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/* configure the LPTIM1 prescaler with 1 */
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LL_LPTIM_SetPrescaler(LPTIM1, LL_LPTIM_PRESCALER_DIV1);
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LL_LPTIM_SetPolarity(LPTIM1, LL_LPTIM_OUTPUT_POLARITY_REGULAR);
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LL_LPTIM_SetUpdateMode(LPTIM1, LL_LPTIM_UPDATE_MODE_IMMEDIATE);
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LL_LPTIM_SetCounterMode(LPTIM1, LL_LPTIM_COUNTER_MODE_INTERNAL);
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LL_LPTIM_DisableTimeout(LPTIM1);
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/* counting start is initiated by software */
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LL_LPTIM_TrigSw(LPTIM1);
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/* LPTIM1 interrupt set-up before enabling */
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/* no Compare match Interrupt */
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LL_LPTIM_DisableIT_CMPM(LPTIM1);
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LL_LPTIM_ClearFLAG_CMPM(LPTIM1);
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/* Autoreload match Interrupt */
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LL_LPTIM_EnableIT_ARRM(LPTIM1);
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LL_LPTIM_ClearFLAG_ARRM(LPTIM1);
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/* ARROK bit validates the write operation to ARR register */
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LL_LPTIM_ClearFlag_ARROK(LPTIM1);
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accumulated_lptim_cnt = 0;
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/* Enable the LPTIM1 counter */
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LL_LPTIM_Enable(LPTIM1);
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/* Set the Autoreload value once the timer is enabled */
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if (IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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/* LPTIM1 is triggered on a LPTIM_TIMEBASE period */
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LL_LPTIM_SetAutoReload(LPTIM1, LPTIM_TIMEBASE);
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} else {
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/* LPTIM1 is triggered on a Tick period */
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LL_LPTIM_SetAutoReload(LPTIM1, COUNT_PER_TICK);
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}
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/* Start the LPTIM counter in continuous mode */
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LL_LPTIM_StartCounter(LPTIM1, LL_LPTIM_OPERATING_MODE_CONTINUOUS);
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#ifdef CONFIG_DEBUG
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/* stop LPTIM1 during DEBUG */
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LL_DBGMCU_APB1_GRP1_FreezePeriph(LL_DBGMCU_APB1_GRP1_LPTIM1_STOP);
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#endif
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return 0;
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}
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void z_clock_set_timeout(s32_t ticks, bool idle)
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{
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/* new LPTIM1 AutoReload value to set (aligned on Kernel ticks) */
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u32_t next_arr = 0;
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ARG_UNUSED(idle);
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/* ARROK bit validates previous write operation to ARR register */
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while (LL_LPTIM_IsActiveFlag_ARROK(LPTIM1) == 0) {
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}
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LL_LPTIM_ClearFlag_ARROK(LPTIM1);
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#ifdef CONFIG_TICKLESS_KERNEL
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if (ticks == K_FOREVER) {
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/* disable LPTIM */
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LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_LPTIM1);
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_LPTIM1);
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return;
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}
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/* passing ticks==1 means "announce the next tick",
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* ticks value of zero (or even negative) is legal and
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* treated identically: it simply indicates the kernel would like the
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* next tick announcement as soon as possible.
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*/
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if (ticks <= (s32_t)1) {
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ticks = 1;
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} else {
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ticks = (ticks - 1);
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}
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/* maximise Tick to keep next_arr on 32bit values,
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* in anycase the ARR cannot exceed LPTIM_TIMEBASE
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*/
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if (ticks > (s32_t)0xFFFF) {
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ticks = 0xFFFF;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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/* read current counter value (cannot exceed 16bit) */
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volatile u32_t lp_time = LL_LPTIM_GetCounter(LPTIM1);
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/* It should be noted that to read reliably the content
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* of the LPTIM_CNT register, two successive read accesses
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* must be performed and compared
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*/
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while (lp_time != LL_LPTIM_GetCounter(LPTIM1)) {
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lp_time = LL_LPTIM_GetCounter(LPTIM1);
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}
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/* calculate the next arr value (cannot exceed 16bit)
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* adjust the next ARR match value to align on Ticks
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* from the current counter value to first next Tick
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*/
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next_arr = (((lp_time * CONFIG_SYS_CLOCK_TICKS_PER_SEC)
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/ LPTIM_CLOCK) + 1) * LPTIM_CLOCK
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/ (CONFIG_SYS_CLOCK_TICKS_PER_SEC);
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/* add count unit from the expected nb of Ticks */
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next_arr = next_arr + ((u32_t)(ticks) * LPTIM_CLOCK)
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/ CONFIG_SYS_CLOCK_TICKS_PER_SEC + 1;
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/* maximise to TIMEBASE */
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if (next_arr > LPTIM_TIMEBASE) {
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next_arr = LPTIM_TIMEBASE;
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}
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/* run timer and wait for the reload match */
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LL_LPTIM_SetAutoReload(LPTIM1, next_arr);
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k_spin_unlock(&lock, key);
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#endif /* CONFIG_TICKLESS_KERNEL */
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}
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u32_t z_clock_elapsed(void)
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{
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if (!IS_ENABLED(CONFIG_TICKLESS_KERNEL)) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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volatile u32_t lp_time = LL_LPTIM_GetCounter(LPTIM1);
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/* It should be noted that to read reliably the content
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* of the LPTIM_CNT register, two successive read accesses
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* must be performed and compared
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*/
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while (lp_time != LL_LPTIM_GetCounter(LPTIM1)) {
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lp_time = LL_LPTIM_GetCounter(LPTIM1);
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}
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k_spin_unlock(&lock, key);
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/* gives the value of LPTIM1 counter (ms)
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* since the previous 'announce'
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*/
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u32_t ret = ((lp_time + 1) * 1000) / LPTIM_CLOCK;
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/* convert to ticks */
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return z_ms_to_ticks(ret);
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}
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u32_t z_timer_cycle_get_32(void)
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{
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/* just gives the accumulated count in a number of hw cycles */
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k_spinlock_key_t key = k_spin_lock(&lock);
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volatile u32_t lp_time = LL_LPTIM_GetCounter(LPTIM1);
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/* It should be noted that to read reliably the content
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* of the LPTIM_CNT register, two successive read accesses
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* must be performed and compared
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*/
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while (lp_time != LL_LPTIM_GetCounter(LPTIM1)) {
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lp_time = LL_LPTIM_GetCounter(LPTIM1);
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}
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lp_time += accumulated_lptim_cnt;
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k_spin_unlock(&lock, key);
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/* convert in hw cycles (keeping 32bit value) */
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return ((lp_time / (LPTIM_CLOCK / 1000))
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* (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / 1000));
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}
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@ -16,3 +16,6 @@ properties:
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clocks:
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required: true
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interrupts:
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required: false
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@ -7,9 +7,10 @@
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if SOC_FAMILY_STM32
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# SYSTICK is the default tick source on STM32 Socs
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config CORTEX_M_SYSTICK
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default y
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bool
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default n if STM32_LPTIM_TIMER
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default y if !STM32_LPTIM_TIMER
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if CLOCK_CONTROL
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