drivers: gpio: ite_it8xxx2: enable more gpio groups
This change enables A, C, D, E, G, H, I, J, K, and L groups, and fix gpio interrupt function. This change also pull (and rename) dt-bindings/irq.h to dt-bindings/interrupt-controller/ite-intc.h, because it is chip-specific. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
This commit is contained in:
Dino Li
Anas Nashif
parent
d93297b3d0
commit
0ab51ff657
10 changed files with 783 additions and 687 deletions
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@ -1,4 +1,4 @@
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/*
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/*
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* Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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* SPDX-License-Identifier: Apache-2.0
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*/
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@ -297,7 +297,6 @@
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* (11xxh) Interrupt controller (INTC)
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*
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*/
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#define MAX_ISR_REG_NUM 24
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#define ISR0 ECREG(EC_REG_BASE_ADDR + 0x3F00)
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#define ISR1 ECREG(EC_REG_BASE_ADDR + 0x3F01)
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#define ISR2 ECREG(EC_REG_BASE_ADDR + 0x3F02)
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@ -319,6 +318,9 @@
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#define ISR18 ECREG(EC_REG_BASE_ADDR + 0x3F4C)
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#define ISR19 ECREG(EC_REG_BASE_ADDR + 0x3F50)
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#define ISR20 ECREG(EC_REG_BASE_ADDR + 0x3F54)
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#define ISR21 ECREG(EC_REG_BASE_ADDR + 0x3F58)
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#define ISR22 ECREG(EC_REG_BASE_ADDR + 0x3F5C)
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#define ISR23 ECREG(EC_REG_BASE_ADDR + 0x3F90)
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#define IER0 ECREG(EC_REG_BASE_ADDR + 0x3F04)
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#define IER1 ECREG(EC_REG_BASE_ADDR + 0x3F05)
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@ -341,6 +343,9 @@
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#define IER18 ECREG(EC_REG_BASE_ADDR + 0x3F4D)
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#define IER19 ECREG(EC_REG_BASE_ADDR + 0x3F51)
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#define IER20 ECREG(EC_REG_BASE_ADDR + 0x3F55)
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#define IER21 ECREG(EC_REG_BASE_ADDR + 0x3F59)
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#define IER22 ECREG(EC_REG_BASE_ADDR + 0x3F5D)
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#define IER23 ECREG(EC_REG_BASE_ADDR + 0x3F91)
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#define IELMR0 ECREG(EC_REG_BASE_ADDR + 0x3F08)
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#define IELMR1 ECREG(EC_REG_BASE_ADDR + 0x3F09)
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@ -363,6 +368,9 @@
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#define IELMR18 ECREG(EC_REG_BASE_ADDR + 0x3F4E)
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#define IELMR19 ECREG(EC_REG_BASE_ADDR + 0x3F52)
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#define IELMR20 ECREG(EC_REG_BASE_ADDR + 0x3F56)
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#define IELMR21 ECREG(EC_REG_BASE_ADDR + 0x3F5A)
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#define IELMR22 ECREG(EC_REG_BASE_ADDR + 0x3F5E)
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#define IELMR23 ECREG(EC_REG_BASE_ADDR + 0x3F92)
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#define IPOLR0 ECREG(EC_REG_BASE_ADDR + 0x3F0C)
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#define IPOLR1 ECREG(EC_REG_BASE_ADDR + 0x3F0D)
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@ -385,217 +393,11 @@
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#define IPOLR18 ECREG(EC_REG_BASE_ADDR + 0x3F4F)
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#define IPOLR19 ECREG(EC_REG_BASE_ADDR + 0x3F53)
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#define IPOLR20 ECREG(EC_REG_BASE_ADDR + 0x3F57)
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#define IPOLR21 ECREG(EC_REG_BASE_ADDR + 0x3F5B)
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#define IPOLR22 ECREG(EC_REG_BASE_ADDR + 0x3F5F)
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#define IPOLR23 ECREG(EC_REG_BASE_ADDR + 0x3F93)
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#define IVECT0 ECREG(EC_REG_BASE_ADDR + 0x3F80)
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#define IVECT1 ECREG(EC_REG_BASE_ADDR + 0x3F81)
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#define IVECT2 ECREG(EC_REG_BASE_ADDR + 0x3F82)
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#define IVECT3 ECREG(EC_REG_BASE_ADDR + 0x3F83)
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#define IVECT4 ECREG(EC_REG_BASE_ADDR + 0x3F84)
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#define IVECT5 ECREG(EC_REG_BASE_ADDR + 0x3F85)
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#define IVECT6 ECREG(EC_REG_BASE_ADDR + 0x3F86)
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#define IVECT7 ECREG(EC_REG_BASE_ADDR + 0x3F87)
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#define IVECT8 ECREG(EC_REG_BASE_ADDR + 0x3F88)
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#define IVECT9 ECREG(EC_REG_BASE_ADDR + 0x3F89)
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#define IVECT10 ECREG(EC_REG_BASE_ADDR + 0x3F8A)
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#define IVECT11 ECREG(EC_REG_BASE_ADDR + 0x3F8B)
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#define IVECT12 ECREG(EC_REG_BASE_ADDR + 0x3F8C)
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#define IVECT13 ECREG(EC_REG_BASE_ADDR + 0x3F8D)
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#define IVECT14 ECREG(EC_REG_BASE_ADDR + 0x3F8E)
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#define IVECT15 ECREG(EC_REG_BASE_ADDR + 0x3F8F)
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#define IVECT ECREG(EC_REG_BASE_ADDR + 0x3F10)
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#define INT0ST ECREG(EC_REG_BASE_ADDR + 0x3F11)
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#define PFAILR ECREG(EC_REG_BASE_ADDR + 0x3F12)
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#define IGER0 ECREG(EC_REG_BASE_ADDR + 0x3F60)
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#define IGER1 ECREG(EC_REG_BASE_ADDR + 0x3F61)
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#define IGER2 ECREG(EC_REG_BASE_ADDR + 0x3F62)
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#define IGER3 ECREG(EC_REG_BASE_ADDR + 0x3F63)
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#define IGER4 ECREG(EC_REG_BASE_ADDR + 0x3F64)
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#define IGER5 ECREG(EC_REG_BASE_ADDR + 0x3F65)
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#define IGER6 ECREG(EC_REG_BASE_ADDR + 0x3F66)
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#define IGER7 ECREG(EC_REG_BASE_ADDR + 0x3F67)
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#define IGER8 ECREG(EC_REG_BASE_ADDR + 0x3F68)
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#define IGER9 ECREG(EC_REG_BASE_ADDR + 0x3F69)
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#define IGER10 ECREG(EC_REG_BASE_ADDR + 0x3F6A)
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#define IGER11 ECREG(EC_REG_BASE_ADDR + 0x3F6B)
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#define IGER12 ECREG(EC_REG_BASE_ADDR + 0x3F6C)
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#define IGER13 ECREG(EC_REG_BASE_ADDR + 0x3F6D)
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#define IGER14 ECREG(EC_REG_BASE_ADDR + 0x3F6E)
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#define IGER15 ECREG(EC_REG_BASE_ADDR + 0x3F6F)
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#define IGER16 ECREG(EC_REG_BASE_ADDR + 0x3F70)
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#define IGER17 ECREG(EC_REG_BASE_ADDR + 0x3F71)
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#define IGER18 ECREG(EC_REG_BASE_ADDR + 0x3F72)
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#define IGER19 ECREG(EC_REG_BASE_ADDR + 0x3F73)
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#define IGER20 ECREG(EC_REG_BASE_ADDR + 0x3F74)
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/* IER0 */
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#define INT_WKO20 BIT(1)
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#define INT_KBCOBFE BIT(2)
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#define INT_PMCOBFE BIT(3)
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#define INT_SMBUS3 BIT(4)
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#define INT_WKINTAD BIT(5)
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#define INT_WKO23 BIT(6)
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#define INT_PWM BIT(7)
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/* IER1 */
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#define INT_ADC BIT(0)
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#define INT_SMBUS0 BIT(1)
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#define INT_SMBUS1 BIT(2)
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#define INT_KB BIT(3)
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#define INT_WKO26 BIT(4)
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#define INT_WKINTC BIT(5)
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#define INT_WKO25 BIT(6)
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#define INT_CIR BIT(7)
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/* IER2 */
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#define INT_SMBUS2 BIT(0)
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#define INT_WKO24 BIT(1)
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#define INT_PS2_2 BIT(2)
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#define INT_PS2_1 BIT(3)
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#define INT_PS2_0 BIT(4)
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#define INT_WKO22 BIT(5)
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#define SMFIS BIT(6)
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/* IER3 */
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#define INT_KBCIBF BIT(0)
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#define INT_PMCIBF BIT(1)
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#define INT_PMC2OBE BIT(2)
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#define INT_PMC2IBF BIT(3)
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#define INT_GINT BIT(4)
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#define INT_EGPC BIT(5)
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#define INT_EXTIMER BIT(6)
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#define INT_WKO21 BIT(7)
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/* IER4 */
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#define INT_GPINT0 BIT(0)
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#define INT_GPINT1 BIT(1)
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#define INT_GPINT2 BIT(2)
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#define INT_GPINT3 BIT(3)
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#define INT_CIRGPINT BIT(4)
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#define INT_SSPI BIT(5)
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#define INT_UART1 BIT(6)
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#define INT_UART2 BIT(7)
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/* IER6 */
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#define INT_WKO60 BIT(0)
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#define INT_WKO61 BIT(1)
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#define INT_WKO62 BIT(2)
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#define INT_WKO63 BIT(3)
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#define INT_WKO64 BIT(4)
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#define INT_WKO65 BIT(5)
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#define INT_WKO66 BIT(6)
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#define INT_WKO67 BIT(7)
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/* IER7 */
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#define INT_RTCTALARM1 BIT(0)
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#define INT_RTCTALARM2 BIT(1)
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#define INT_ET2INTR BIT(2)
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#define INT_TMRINTA0 BIT(4)
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#define INT_TMRINTA1 BIT(5)
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#define INT_TMRINTB0 BIT(6)
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#define INT_TMRINTB1 BIT(7)
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/* IER8 */
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#define INT_PMC2EXOBE BIT(0)
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#define INT_PMC2EXIBF BIT(1)
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#define INT_PMC3OBE BIT(2)
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#define INT_PMC3IBF BIT(3)
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#define INT_PMC4OBE BIT(4)
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#define INT_PMC4IBF BIT(5)
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#define INT_I2BRAM BIT(7)
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/* IER9 */
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#define INT_WKO70 BIT(0)
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#define INT_WKO71 BIT(1)
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#define INT_WKO72 BIT(2)
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#define INT_WKO73 BIT(3)
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#define INT_WKO74 BIT(4)
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#define INT_WKO75 BIT(5)
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#define INT_WKO76 BIT(6)
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#define INT_WKO77 BIT(7)
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/* IER10 */
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#define INT_ET8INTR BIT(0)
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#define INT_SMBUSCHINER BIT(1)
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#define INT_CEC BIT(2)
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#define INT_H2RAMLPC BIT(3)
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#define INT_KBSDVINTR BIT(4)
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#define INT_WKO88 BIT(5)
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#define INT_WKO89 BIT(6)
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#define INT_WKO90 BIT(7)
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/* IER11 */
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#define INT_WKO80 BIT(0)
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#define INT_WKO81 BIT(1)
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#define INT_WKO82 BIT(2)
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#define INT_WKO83 BIT(3)
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#define INT_WKO84 BIT(4)
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#define INT_WKO85 BIT(5)
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#define INT_WKO86 BIT(6)
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#define INT_WKO87 BIT(7)
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/* IER12 */
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#define INT_WKO91 BIT(0)
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#define INT_WKO92 BIT(1)
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#define INT_WKO93 BIT(2)
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#define INT_WKO94 BIT(3)
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#define INT_WKO95 BIT(4)
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#define INT_WKO96 BIT(5)
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#define INT_WKO97 BIT(6)
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#define INT_WKO98 BIT(7)
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/* IER13 */
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#define INT_WKO99 BIT(0)
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#define INT_WKO100 BIT(1)
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#define INT_WKO101 BIT(2)
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#define INT_WKO102 BIT(3)
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#define INT_WKO103 BIT(4)
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#define INT_WKO104 BIT(5)
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#define INT_WKO105 BIT(6)
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#define INT_WKO106 BIT(7)
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/* IER14 */
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#define INT_WKO107 BIT(0)
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#define INT_WKO108 BIT(1)
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#define INT_WKO109 BIT(2)
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#define INT_WKO110 BIT(3)
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#define INT_WKO111 BIT(4)
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#define INT_WKO112 BIT(5)
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#define INT_WKO113 BIT(6)
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#define INT_WKO114 BIT(7)
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/* IER15 */
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#define INT_WKO115 BIT(0)
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#define INT_WKO116 BIT(1)
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#define INT_WKO117 BIT(2)
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#define INT_WKO118 BIT(3)
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#define INT_WKO119 BIT(4)
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#define INT_WKO120 BIT(5)
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#define INT_WKO121 BIT(6)
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#define INT_WKO122 BIT(7)
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/* IER16 */
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#define INT_WKO128 BIT(0)
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#define INT_WKO129 BIT(1)
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#define INT_WKO130 BIT(2)
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#define INT_WKO131 BIT(3)
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#define INT_WKO132 BIT(4)
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#define INT_WKO133 BIT(5)
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#define INT_WKO134 BIT(6)
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/* IER18 */
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#define INT_PMC5OBE BIT(5)
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#define INT_PMC5IBE BIT(6)
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#define INT_VCI BIT(7)
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/* IER19 */
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#define INT_SMBUSE BIT(0)
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#define INT_SMBUSF BIT(1)
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#define INT_OSCDMAINTER BIT(2)
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#define INT_ET3INTR BIT(3)
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#define INT_ET4INTR BIT(4)
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#define INT_ET5INTR BIT(5)
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#define INT_ET6INTR BIT(6)
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#define INT_ET7INTR BIT(7)
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/**
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*
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@ -855,105 +657,20 @@
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#define GCR19 ECREG(EC_REG_BASE_ADDR + 0x16E4)
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#define GCR20 ECREG(EC_REG_BASE_ADDR + 0x16E5)
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#define GCR21 ECREG(EC_REG_BASE_ADDR + 0x16E6)
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#define GPDRA ECREG(EC_REG_BASE_ADDR + 0x1601)
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#define GPDRB ECREG(EC_REG_BASE_ADDR + 0x1602)
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#define GPDRC ECREG(EC_REG_BASE_ADDR + 0x1603)
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#define GPDRD ECREG(EC_REG_BASE_ADDR + 0x1604)
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#define GPDRE ECREG(EC_REG_BASE_ADDR + 0x1605)
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#define GPDRF ECREG(EC_REG_BASE_ADDR + 0x1606)
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#define GPDRG ECREG(EC_REG_BASE_ADDR + 0x1607)
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#define GPDRH ECREG(EC_REG_BASE_ADDR + 0x1608)
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#define GPDRI ECREG(EC_REG_BASE_ADDR + 0x1609)
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#define GPDRJ ECREG(EC_REG_BASE_ADDR + 0x160A)
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#define GPDRM ECREG(EC_REG_BASE_ADDR + 0x160D)
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/*
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* TODO: use pinmux driver to enable uart function so we can remove these
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* registers' declaration.
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*/
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/* GPIO control register */
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#define GPCRA0 ECREG(EC_REG_BASE_ADDR + 0x1610)
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#define GPCRA1 ECREG(EC_REG_BASE_ADDR + 0x1611)
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#define GPCRA2 ECREG(EC_REG_BASE_ADDR + 0x1612)
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#define GPCRA3 ECREG(EC_REG_BASE_ADDR + 0x1613)
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#define GPCRA4 ECREG(EC_REG_BASE_ADDR + 0x1614)
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#define GPCRA5 ECREG(EC_REG_BASE_ADDR + 0x1615)
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#define GPCRA6 ECREG(EC_REG_BASE_ADDR + 0x1616)
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#define GPCRA7 ECREG(EC_REG_BASE_ADDR + 0x1617)
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#define GPCRB0 ECREG(EC_REG_BASE_ADDR + 0x1618)
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#define GPCRB1 ECREG(EC_REG_BASE_ADDR + 0x1619)
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#define GPCRB2 ECREG(EC_REG_BASE_ADDR + 0x161A)
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#define GPCRB3 ECREG(EC_REG_BASE_ADDR + 0x161B)
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#define GPCRB4 ECREG(EC_REG_BASE_ADDR + 0x161C)
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#define GPCRB5 ECREG(EC_REG_BASE_ADDR + 0x161D)
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#define GPCRB6 ECREG(EC_REG_BASE_ADDR + 0x161E)
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#define GPCRB7 ECREG(EC_REG_BASE_ADDR + 0x161F)
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#define GPCRC0 ECREG(EC_REG_BASE_ADDR + 0x1620)
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#define GPCRC1 ECREG(EC_REG_BASE_ADDR + 0x1621)
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#define GPCRC2 ECREG(EC_REG_BASE_ADDR + 0x1622)
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#define GPCRC3 ECREG(EC_REG_BASE_ADDR + 0x1623)
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#define GPCRC4 ECREG(EC_REG_BASE_ADDR + 0x1624)
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#define GPCRC5 ECREG(EC_REG_BASE_ADDR + 0x1625)
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#define GPCRC6 ECREG(EC_REG_BASE_ADDR + 0x1626)
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#define GPCRC7 ECREG(EC_REG_BASE_ADDR + 0x1627)
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#define GPCRD0 ECREG(EC_REG_BASE_ADDR + 0x1628)
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#define GPCRD1 ECREG(EC_REG_BASE_ADDR + 0x1629)
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#define GPCRD2 ECREG(EC_REG_BASE_ADDR + 0x162A)
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#define GPCRD3 ECREG(EC_REG_BASE_ADDR + 0x162B)
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#define GPCRD4 ECREG(EC_REG_BASE_ADDR + 0x162C)
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#define GPCRD5 ECREG(EC_REG_BASE_ADDR + 0x162D)
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#define GPCRD6 ECREG(EC_REG_BASE_ADDR + 0x162E)
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#define GPCRD7 ECREG(EC_REG_BASE_ADDR + 0x162F)
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#define GPCRE0 ECREG(EC_REG_BASE_ADDR + 0x1630)
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#define GPCRE1 ECREG(EC_REG_BASE_ADDR + 0x1631)
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#define GPCRE2 ECREG(EC_REG_BASE_ADDR + 0x1632)
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#define GPCRE3 ECREG(EC_REG_BASE_ADDR + 0x1633)
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#define GPCRE4 ECREG(EC_REG_BASE_ADDR + 0x1634)
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#define GPCRE5 ECREG(EC_REG_BASE_ADDR + 0x1635)
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#define GPCRE6 ECREG(EC_REG_BASE_ADDR + 0x1636)
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#define GPCRE7 ECREG(EC_REG_BASE_ADDR + 0x1637)
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#define GPCRF0 ECREG(EC_REG_BASE_ADDR + 0x1638)
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#define GPCRF1 ECREG(EC_REG_BASE_ADDR + 0x1639)
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#define GPCRF2 ECREG(EC_REG_BASE_ADDR + 0x163A)
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#define GPCRF3 ECREG(EC_REG_BASE_ADDR + 0x163B)
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#define GPCRF4 ECREG(EC_REG_BASE_ADDR + 0x163C)
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#define GPCRF5 ECREG(EC_REG_BASE_ADDR + 0x163D)
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#define GPCRF6 ECREG(EC_REG_BASE_ADDR + 0x163E)
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#define GPCRF7 ECREG(EC_REG_BASE_ADDR + 0x163F)
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#define GPCRG0 ECREG(EC_REG_BASE_ADDR + 0x1640)
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#define GPCRG1 ECREG(EC_REG_BASE_ADDR + 0x1641)
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#define GPCRG2 ECREG(EC_REG_BASE_ADDR + 0x1642)
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#define GPCRG3 ECREG(EC_REG_BASE_ADDR + 0x1643)
|
||||
#define GPCRG4 ECREG(EC_REG_BASE_ADDR + 0x1644)
|
||||
#define GPCRG5 ECREG(EC_REG_BASE_ADDR + 0x1645)
|
||||
#define GPCRG6 ECREG(EC_REG_BASE_ADDR + 0x1646)
|
||||
#define GPCRG7 ECREG(EC_REG_BASE_ADDR + 0x1647)
|
||||
#define GPCRH0 ECREG(EC_REG_BASE_ADDR + 0x1648)
|
||||
#define GPCRH1 ECREG(EC_REG_BASE_ADDR + 0x1649)
|
||||
#define GPCRH2 ECREG(EC_REG_BASE_ADDR + 0x164A)
|
||||
#define GPCRH3 ECREG(EC_REG_BASE_ADDR + 0x164B)
|
||||
#define GPCRH4 ECREG(EC_REG_BASE_ADDR + 0x164C)
|
||||
#define GPCRH5 ECREG(EC_REG_BASE_ADDR + 0x164D)
|
||||
#define GPCRH6 ECREG(EC_REG_BASE_ADDR + 0x164E)
|
||||
#define GPCRI0 ECREG(EC_REG_BASE_ADDR + 0x1650)
|
||||
#define GPCRI1 ECREG(EC_REG_BASE_ADDR + 0x1651)
|
||||
#define GPCRI2 ECREG(EC_REG_BASE_ADDR + 0x1652)
|
||||
#define GPCRI3 ECREG(EC_REG_BASE_ADDR + 0x1653)
|
||||
#define GPCRI4 ECREG(EC_REG_BASE_ADDR + 0x1654)
|
||||
#define GPCRI5 ECREG(EC_REG_BASE_ADDR + 0x1655)
|
||||
#define GPCRI6 ECREG(EC_REG_BASE_ADDR + 0x1656)
|
||||
#define GPCRI7 ECREG(EC_REG_BASE_ADDR + 0x1657)
|
||||
#define GPCRJ0 ECREG(EC_REG_BASE_ADDR + 0x1658)
|
||||
#define GPCRJ1 ECREG(EC_REG_BASE_ADDR + 0x1659)
|
||||
#define GPCRJ2 ECREG(EC_REG_BASE_ADDR + 0x165A)
|
||||
#define GPCRJ3 ECREG(EC_REG_BASE_ADDR + 0x165B)
|
||||
#define GPCRJ4 ECREG(EC_REG_BASE_ADDR + 0x165C)
|
||||
#define GPCRJ5 ECREG(EC_REG_BASE_ADDR + 0x165D)
|
||||
#define GPCRJ6 ECREG(EC_REG_BASE_ADDR + 0x165E)
|
||||
#define GPCRJ7 ECREG(EC_REG_BASE_ADDR + 0x165F)
|
||||
#define GPCRM0 ECREG(EC_REG_BASE_ADDR + 0x16A0)
|
||||
#define GPCRM1 ECREG(EC_REG_BASE_ADDR + 0x16A1)
|
||||
#define GPCRM2 ECREG(EC_REG_BASE_ADDR + 0x16A2)
|
||||
#define GPCRM3 ECREG(EC_REG_BASE_ADDR + 0x16A3)
|
||||
#define GPCRM4 ECREG(EC_REG_BASE_ADDR + 0x16A4)
|
||||
#define GPCRM5 ECREG(EC_REG_BASE_ADDR + 0x16A5)
|
||||
#define GPCRM6 ECREG(EC_REG_BASE_ADDR + 0x16A6)
|
||||
|
||||
/* Port Data Mirror Register */
|
||||
#define GPDMRA ECREG(EC_REG_BASE_ADDR + 0x1661)
|
||||
|
|
@ -967,13 +684,6 @@
|
|||
#define GPDMRI ECREG(EC_REG_BASE_ADDR + 0x1669)
|
||||
#define GPDMRJ ECREG(EC_REG_BASE_ADDR + 0x166A)
|
||||
#define GPDMRM ECREG(EC_REG_BASE_ADDR + 0x166D)
|
||||
#define GPOTA ECREG(EC_REG_BASE_ADDR + 0x1671)
|
||||
#define GPOTB ECREG(EC_REG_BASE_ADDR + 0x1672)
|
||||
#define GPOTD ECREG(EC_REG_BASE_ADDR + 0x1674)
|
||||
#define GPOTE ECREG(EC_REG_BASE_ADDR + 0x1675)
|
||||
#define GPOTF ECREG(EC_REG_BASE_ADDR + 0x1676)
|
||||
#define GPOTH ECREG(EC_REG_BASE_ADDR + 0x1678)
|
||||
#define GPOTJ ECREG(EC_REG_BASE_ADDR + 0x167A)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
@ -1137,61 +847,15 @@
|
|||
#define PORSREGA ECREG(EC_REG_BASE_ADDR + 0x1A14)
|
||||
#define PORSREGB ECREG(EC_REG_BASE_ADDR + 0x1A15)
|
||||
|
||||
/**
|
||||
*
|
||||
* (1Bxxh) Wack-Up control (WUC)
|
||||
*
|
||||
*/
|
||||
#define WUEMR1 ECREG(EC_REG_BASE_ADDR + 0x1B00)
|
||||
#define WUEMR2 ECREG(EC_REG_BASE_ADDR + 0x1B01)
|
||||
#define WUEMR3 ECREG(EC_REG_BASE_ADDR + 0x1B02)
|
||||
#define WUEMR4 ECREG(EC_REG_BASE_ADDR + 0x1B03)
|
||||
#define WUEMR6 ECREG(EC_REG_BASE_ADDR + 0x1B10)
|
||||
#define WUEMR7 ECREG(EC_REG_BASE_ADDR + 0x1B14)
|
||||
#define WUEMR8 ECREG(EC_REG_BASE_ADDR + 0x1B18)
|
||||
#define WUEMR9 ECREG(EC_REG_BASE_ADDR + 0x1B1C)
|
||||
#define WUEMR10 ECREG(EC_REG_BASE_ADDR + 0x1B20)
|
||||
#define WUEMR11 ECREG(EC_REG_BASE_ADDR + 0x1B24)
|
||||
#define WUEMR12 ECREG(EC_REG_BASE_ADDR + 0x1B28)
|
||||
#define WUEMR13 ECREG(EC_REG_BASE_ADDR + 0x1B2C)
|
||||
#define WUEMR14 ECREG(EC_REG_BASE_ADDR + 0x1B30)
|
||||
#define WUESR1 ECREG(EC_REG_BASE_ADDR + 0x1B04)
|
||||
#define WUESR2 ECREG(EC_REG_BASE_ADDR + 0x1B05)
|
||||
#define WUESR3 ECREG(EC_REG_BASE_ADDR + 0x1B06)
|
||||
#define WUESR4 ECREG(EC_REG_BASE_ADDR + 0x1B07)
|
||||
#define WUESR6 ECREG(EC_REG_BASE_ADDR + 0x1B11)
|
||||
#define WUESR7 ECREG(EC_REG_BASE_ADDR + 0x1B15)
|
||||
#define WUESR8 ECREG(EC_REG_BASE_ADDR + 0x1B19)
|
||||
#define WUESR9 ECREG(EC_REG_BASE_ADDR + 0x1B1D)
|
||||
#define WUESR10 ECREG(EC_REG_BASE_ADDR + 0x1B21)
|
||||
#define WUESR11 ECREG(EC_REG_BASE_ADDR + 0x1B25)
|
||||
#define WUESR12 ECREG(EC_REG_BASE_ADDR + 0x1B29)
|
||||
#define WUESR13 ECREG(EC_REG_BASE_ADDR + 0x1B2D)
|
||||
#define WUESR14 ECREG(EC_REG_BASE_ADDR + 0x1B31)
|
||||
#define WUENR1 ECREG(EC_REG_BASE_ADDR + 0x1B08)
|
||||
#define WUENR2 ECREG(EC_REG_BASE_ADDR + 0x1B09)
|
||||
#define WUENR3 ECREG(EC_REG_BASE_ADDR + 0x1B0A)
|
||||
#define WUENR4 ECREG(EC_REG_BASE_ADDR + 0x1B0B)
|
||||
#define WUENR6 ECREG(EC_REG_BASE_ADDR + 0x1B12)
|
||||
#define WUENR7 ECREG(EC_REG_BASE_ADDR + 0x1B16)
|
||||
#define WUENR8 ECREG(EC_REG_BASE_ADDR + 0x1B1A)
|
||||
#define WUENR9 ECREG(EC_REG_BASE_ADDR + 0x1B1E)
|
||||
/* --- Wake-Up Control (WUC) --- */
|
||||
#define IT8XXX2_WUC_BASE 0x00F01B00
|
||||
|
||||
#define WUEMR6_BASE (EC_REG_BASE_ADDR + 0x1B10)
|
||||
#define WUESR6_BASE (EC_REG_BASE_ADDR + 0x1B11)
|
||||
#define WUBEMR6 ECREG(EC_REG_BASE_ADDR + 0x1B13)
|
||||
#define WUEMR8_BASE (EC_REG_BASE_ADDR + 0x1B18)
|
||||
#define WUESR8_BASE (EC_REG_BASE_ADDR + 0x1B19)
|
||||
#define WUBEMR8 ECREG(EC_REG_BASE_ADDR + 0x1B1B)
|
||||
#define WUEMR9_BASE (EC_REG_BASE_ADDR + 0x1B1C)
|
||||
#define WUESR9_BASE (EC_REG_BASE_ADDR + 0x1B1D)
|
||||
#define WUBEMR9 ECREG(EC_REG_BASE_ADDR + 0x1B1F)
|
||||
#define WUEMR10_BASE (EC_REG_BASE_ADDR + 0x1B20)
|
||||
#define WUESR10_BASE (EC_REG_BASE_ADDR + 0x1B21)
|
||||
#define WUBEMR10 ECREG(EC_REG_BASE_ADDR + 0x1B23)
|
||||
#define WUEMR11_BASE (EC_REG_BASE_ADDR + 0x1B24)
|
||||
#define WUESR11_BASE (EC_REG_BASE_ADDR + 0x1B25)
|
||||
#define WUBEMR11 ECREG(EC_REG_BASE_ADDR + 0x1B27)
|
||||
#define IT8XXX2_WUC_WUEMR1 (IT8XXX2_WUC_BASE + 0x00)
|
||||
#define IT8XXX2_WUC_WUEMR5 (IT8XXX2_WUC_BASE + 0x0c)
|
||||
#define IT8XXX2_WUC_WUESR1 (IT8XXX2_WUC_BASE + 0x04)
|
||||
#define IT8XXX2_WUC_WUESR5 (IT8XXX2_WUC_BASE + 0x0d)
|
||||
#define IT8XXX2_WUC_WUBEMR1 (IT8XXX2_WUC_BASE + 0x3c)
|
||||
#define IT8XXX2_WUC_WUBEMR5 (IT8XXX2_WUC_BASE + 0x0f)
|
||||
|
||||
/**
|
||||
*
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue