drivers/spi: Removing QMSI driver as it does not support new API
Native DW driver is relevantly used instead. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
This commit is contained in:
Tomasz Bursztyka
Carles Cufí
parent
1ac6f4bd56
commit
0a43cac3bb
5 changed files with 0 additions and 940 deletions
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@ -3,8 +3,6 @@ if(CONFIG_SPI_LEGACY_API)
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zephyr_sources_ifdef(CONFIG_SPIS_NRF5 spis_nrf5_legacy.c)
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zephyr_sources_ifdef(CONFIG_SPIS_NRF5 spis_nrf5_legacy.c)
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zephyr_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_sources_ifdef(CONFIG_SPI_INTEL spi_intel.c)
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zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_sources_ifdef(CONFIG_SPI_MCUX_DSPI spi_mcux_dspi.c)
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zephyr_sources_ifdef(CONFIG_SPI_QMSI spi_qmsi.c)
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zephyr_sources_ifdef(CONFIG_SPI_QMSI_SS spi_qmsi_ss.c)
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else()
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else()
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zephyr_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
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zephyr_sources_ifdef(CONFIG_SPI_DW spi_dw.c)
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zephyr_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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zephyr_sources_ifdef(CONFIG_SPI_STM32 spi_ll_stm32.c)
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@ -299,8 +299,6 @@ config SPI_INTEL
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was formerly found on XScale chips. It can be found nowadays
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was formerly found on XScale chips. It can be found nowadays
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on CEXXXX Intel media controller and Quark CPU (2 of them).
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on CEXXXX Intel media controller and Quark CPU (2 of them).
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source "drivers/spi/Kconfig.qmsi"
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source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.mcux_dspi"
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source "drivers/spi/Kconfig.nrf5_legacy"
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source "drivers/spi/Kconfig.nrf5_legacy"
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@ -1,92 +0,0 @@
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# Kconfig.qmsi - QMSI SPI shim driver configuration options
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#
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# Copyright (c) 2017 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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menuconfig SPI_QMSI
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bool "QMSI driver for SPI controller"
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depends on QMSI
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default n
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help
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SPI driver implementation using QMSI library. QMSI is the
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Quark Microcontroller Software Interface, providing a common
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interface to the Quark family of microcontrollers.
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config SPI_QMSI_SS
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bool "QMSI driver for SPI controller on Sensor Subsystem"
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depends on QMSI
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default n
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help
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SPI driver implementation using QMSI library. This instance is
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for the Sensor Subsystem.
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if QMSI_SS
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config SPI_SS_INIT_PRIORITY
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int "Init priority"
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default 70
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help
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Device driver initialization priority.
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config SPI_SS_CS_GPIO
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bool "SPI port CS pin is controlled via a GPIO port"
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select GPIO
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default n
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config SPI_SS_0
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bool "SPI SS port 0"
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default n
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help
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Enable SPI controller port 0.
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if SPI_SS_0
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config SPI_SS_0_NAME
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string "SPI SS port 0 device name"
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default "SPI_SS_0"
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config SPI_SS_0_IRQ_PRI
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int "Port 0 interrupt priority"
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config SPI_SS_0_CS_GPIO_PORT
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string "The GPIO port which is used to control CS"
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depends on SPI_SS_CS_GPIO
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default "GPIO_0"
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config SPI_SS_0_CS_GPIO_PIN
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int "The GPIO PIN which is used to act as a CS pin"
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depends on SPI_SS_CS_GPIO
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default 0
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endif # SPI_SS_0
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config SPI_SS_1
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bool "SPI SS port 1"
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default n
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help
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Enable SPI controller port 1.
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if SPI_SS_1
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config SPI_SS_1_NAME
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string "SPI port 1 device name"
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default "SPI_SS_1"
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config SPI_SS_1_IRQ_PRI
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int "Port 0 interrupt priority"
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config SPI_SS_1_CS_GPIO_PORT
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string "The GPIO port which is used to control CS"
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depends on SPI_SS_CS_GPIO
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default "GPIO_0"
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config SPI_SS_1_CS_GPIO_PIN
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int "The GPIO PIN which is used to act as a CS pin"
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depends on SPI_SS_CS_GPIO
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default 0
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endif # SPI_SS_1
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endif # QMSI_SS
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@ -1,384 +0,0 @@
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/*
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* Copyright (c) 2016 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/ioapic.h>
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#include <init.h>
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#include <kernel.h>
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#include <spi.h>
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#include <gpio.h>
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#include <power.h>
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#include "qm_spi.h"
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#include "clk.h"
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#include "qm_isr.h"
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#include "soc.h"
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struct pending_transfer {
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struct device *dev;
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qm_spi_async_transfer_t xfer;
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};
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static struct pending_transfer pending_transfers[QM_SPI_NUM];
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struct spi_qmsi_config {
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qm_spi_t spi;
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char *cs_port;
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u32_t cs_pin;
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};
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struct spi_qmsi_runtime {
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struct device *gpio_cs;
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struct k_sem device_sync_sem;
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qm_spi_config_t cfg;
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int rc;
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bool loopback;
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struct k_sem sem;
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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u32_t device_power_state;
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qm_spi_context_t spi_ctx;
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#endif
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};
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static inline qm_spi_bmode_t config_to_bmode(u8_t mode)
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{
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switch (mode) {
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case SPI_MODE_CPHA:
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return QM_SPI_BMODE_1;
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case SPI_MODE_CPOL:
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return QM_SPI_BMODE_2;
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case SPI_MODE_CPOL | SPI_MODE_CPHA:
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return QM_SPI_BMODE_3;
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default:
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return QM_SPI_BMODE_0;
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}
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}
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static void spi_control_cs(struct device *dev, bool active)
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{
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struct spi_qmsi_runtime *context = dev->driver_data;
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const struct spi_qmsi_config *config = dev->config->config_info;
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struct device *gpio = context->gpio_cs;
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if (!gpio) {
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return;
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}
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gpio_pin_write(gpio, config->cs_pin, !active);
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}
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static int spi_qmsi_configure(struct device *dev,
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struct spi_config *config)
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{
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struct spi_qmsi_runtime *context = dev->driver_data;
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qm_spi_config_t *cfg = &context->cfg;
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cfg->frame_size = SPI_WORD_SIZE_GET(config->config) - 1;
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cfg->bus_mode = config_to_bmode(SPI_MODE(config->config));
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/* As loopback is implemented inside the controller,
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* the bus mode doesn't matter.
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*/
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context->loopback = SPI_MODE(config->config) & SPI_MODE_LOOP;
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cfg->clk_divider = config->max_sys_freq;
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/* Will set the configuration before the transfer starts */
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return 0;
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}
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static void transfer_complete(void *data, int error, qm_spi_status_t status,
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u16_t len)
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{
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const struct spi_qmsi_config *spi_config =
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((struct device *)data)->config->config_info;
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qm_spi_t spi = spi_config->spi;
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struct pending_transfer *pending = &pending_transfers[spi];
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struct device *dev = pending->dev;
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struct spi_qmsi_runtime *context;
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if (!dev) {
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return;
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}
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context = dev->driver_data;
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spi_control_cs(dev, false);
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pending->dev = NULL;
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context->rc = error;
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k_sem_give(&context->device_sync_sem);
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}
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static int spi_qmsi_slave_select(struct device *dev, u32_t slave)
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{
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const struct spi_qmsi_config *spi_config = dev->config->config_info;
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qm_spi_t spi = spi_config->spi;
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return qm_spi_slave_select(spi, 1 << (slave - 1)) ? -EIO : 0;
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}
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static inline u8_t frame_size_to_dfs(qm_spi_frame_size_t frame_size)
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{
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if (frame_size <= QM_SPI_FRAME_SIZE_8_BIT) {
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return 1;
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}
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if (frame_size <= QM_SPI_FRAME_SIZE_16_BIT) {
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return 2;
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}
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if (frame_size <= QM_SPI_FRAME_SIZE_32_BIT) {
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return 4;
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}
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/* This should never happen, it will crash later on. */
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return 0;
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}
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static int spi_qmsi_transceive(struct device *dev,
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const void *tx_buf, u32_t tx_buf_len,
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void *rx_buf, u32_t rx_buf_len)
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{
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const struct spi_qmsi_config *spi_config = dev->config->config_info;
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qm_spi_t spi = spi_config->spi;
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struct spi_qmsi_runtime *context = dev->driver_data;
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qm_spi_config_t *cfg = &context->cfg;
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u8_t dfs = frame_size_to_dfs(cfg->frame_size);
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qm_spi_async_transfer_t *xfer;
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int rc;
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k_sem_take(&context->sem, K_FOREVER);
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if (pending_transfers[spi].dev) {
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k_sem_give(&context->sem);
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return -EBUSY;
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}
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pending_transfers[spi].dev = dev;
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k_sem_give(&context->sem);
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device_busy_set(dev);
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xfer = &pending_transfers[spi].xfer;
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xfer->rx = rx_buf;
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xfer->rx_len = rx_buf_len / dfs;
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/* This cast is necessary to drop the "const" modifier, since QMSI xfer
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* does not take a const pointer.
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*/
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xfer->tx = (u8_t *)tx_buf;
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xfer->tx_len = tx_buf_len / dfs;
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xfer->callback_data = dev;
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xfer->callback = transfer_complete;
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if (tx_buf_len == 0) {
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cfg->transfer_mode = QM_SPI_TMOD_RX;
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} else if (rx_buf_len == 0) {
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cfg->transfer_mode = QM_SPI_TMOD_TX;
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} else {
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/* FIXME: QMSI expects rx_buf_len and tx_buf_len to
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* have the same size.
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*/
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cfg->transfer_mode = QM_SPI_TMOD_TX_RX;
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}
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if (context->loopback) {
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QM_SPI[spi]->ctrlr0 |= BIT(11);
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}
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rc = qm_spi_set_config(spi, cfg);
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if (rc != 0) {
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device_busy_clear(dev);
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return -EINVAL;
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}
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spi_control_cs(dev, true);
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rc = qm_spi_irq_transfer(spi, xfer);
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if (rc != 0) {
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spi_control_cs(dev, false);
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device_busy_clear(dev);
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return -EIO;
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}
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k_sem_take(&context->device_sync_sem, K_FOREVER);
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device_busy_clear(dev);
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return context->rc ? -EIO : 0;
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}
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static const struct spi_driver_api spi_qmsi_api = {
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.configure = spi_qmsi_configure,
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.slave_select = spi_qmsi_slave_select,
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.transceive = spi_qmsi_transceive,
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};
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static struct device *gpio_cs_init(const struct spi_qmsi_config *config)
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{
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struct device *gpio;
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if (!config->cs_port) {
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return NULL;
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}
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gpio = device_get_binding(config->cs_port);
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if (!gpio) {
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return NULL;
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}
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if (gpio_pin_configure(gpio, config->cs_pin, GPIO_DIR_OUT) != 0) {
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return NULL;
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}
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if (gpio_pin_write(gpio, config->cs_pin, 1) != 0) {
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return NULL;
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}
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return gpio;
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}
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#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
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static void spi_master_set_power_state(struct device *dev, u32_t power_state)
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{
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struct spi_qmsi_runtime *context = dev->driver_data;
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context->device_power_state = power_state;
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}
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static u32_t spi_master_get_power_state(struct device *dev)
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{
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struct spi_qmsi_runtime *context = dev->driver_data;
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return context->device_power_state;
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}
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#else
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#define spi_master_set_power_state(...)
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#endif
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static int spi_qmsi_init(struct device *dev)
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{
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const struct spi_qmsi_config *spi_config = dev->config->config_info;
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struct spi_qmsi_runtime *context = dev->driver_data;
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switch (spi_config->spi) {
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case QM_SPI_MST_0:
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IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT),
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CONFIG_SPI_0_IRQ_PRI, qm_spi_master_0_isr,
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0, IOAPIC_LEVEL | IOAPIC_HIGH);
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irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_0_INT));
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clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M0_REGISTER);
|
|
||||||
QM_IR_UNMASK_INTERRUPTS(
|
|
||||||
QM_INTERRUPT_ROUTER->spi_master_0_int_mask);
|
|
||||||
break;
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_1
|
|
||||||
case QM_SPI_MST_1:
|
|
||||||
IRQ_CONNECT(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT),
|
|
||||||
CONFIG_SPI_1_IRQ_PRI, qm_spi_master_1_isr,
|
|
||||||
0, IOAPIC_LEVEL | IOAPIC_HIGH);
|
|
||||||
irq_enable(IRQ_GET_NUMBER(QM_IRQ_SPI_MASTER_1_INT));
|
|
||||||
clk_periph_enable(CLK_PERIPH_CLK | CLK_PERIPH_SPI_M1_REGISTER);
|
|
||||||
QM_IR_UNMASK_INTERRUPTS(
|
|
||||||
QM_INTERRUPT_ROUTER->spi_master_1_int_mask);
|
|
||||||
break;
|
|
||||||
#endif /* CONFIG_SPI_1 */
|
|
||||||
|
|
||||||
default:
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
context->gpio_cs = gpio_cs_init(spi_config);
|
|
||||||
|
|
||||||
k_sem_init(&context->device_sync_sem, 0, UINT_MAX);
|
|
||||||
k_sem_init(&context->sem, 1, UINT_MAX);
|
|
||||||
|
|
||||||
spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
|
|
||||||
|
|
||||||
dev->driver_api = &spi_qmsi_api;
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
||||||
static int spi_master_suspend_device(struct device *dev)
|
|
||||||
{
|
|
||||||
if (device_busy_check(dev)) {
|
|
||||||
return -EBUSY;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct spi_qmsi_config *config = dev->config->config_info;
|
|
||||||
struct spi_qmsi_runtime *drv_data = dev->driver_data;
|
|
||||||
|
|
||||||
qm_spi_save_context(config->spi, &drv_data->spi_ctx);
|
|
||||||
|
|
||||||
spi_master_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int spi_master_resume_device_from_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
const struct spi_qmsi_config *config = dev->config->config_info;
|
|
||||||
struct spi_qmsi_runtime *drv_data = dev->driver_data;
|
|
||||||
|
|
||||||
qm_spi_restore_context(config->spi, &drv_data->spi_ctx);
|
|
||||||
|
|
||||||
spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Implements the driver control management functionality
|
|
||||||
* the *context may include IN data or/and OUT data
|
|
||||||
*/
|
|
||||||
static int spi_master_qmsi_device_ctrl(struct device *port,
|
|
||||||
u32_t ctrl_command, void *context)
|
|
||||||
{
|
|
||||||
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
|
|
||||||
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
|
|
||||||
return spi_master_suspend_device(port);
|
|
||||||
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
|
|
||||||
return spi_master_resume_device_from_suspend(port);
|
|
||||||
}
|
|
||||||
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
|
|
||||||
*((u32_t *)context) = spi_master_get_power_state(port);
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_0
|
|
||||||
static const struct spi_qmsi_config spi_qmsi_mst_0_config = {
|
|
||||||
.spi = QM_SPI_MST_0,
|
|
||||||
#ifdef CONFIG_SPI_CS_GPIO
|
|
||||||
.cs_port = CONFIG_SPI_0_CS_GPIO_PORT,
|
|
||||||
.cs_pin = CONFIG_SPI_0_CS_GPIO_PIN,
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct spi_qmsi_runtime spi_qmsi_mst_0_runtime;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(spi_master_0, CONFIG_SPI_0_NAME, spi_qmsi_init,
|
|
||||||
spi_master_qmsi_device_ctrl, &spi_qmsi_mst_0_runtime,
|
|
||||||
&spi_qmsi_mst_0_config, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
|
||||||
NULL);
|
|
||||||
#endif /* CONFIG_SPI_0 */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_1
|
|
||||||
static const struct spi_qmsi_config spi_qmsi_mst_1_config = {
|
|
||||||
.spi = QM_SPI_MST_1,
|
|
||||||
#ifdef CONFIG_SPI_CS_GPIO
|
|
||||||
.cs_port = CONFIG_SPI_1_CS_GPIO_PORT,
|
|
||||||
.cs_pin = CONFIG_SPI_1_CS_GPIO_PIN,
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct spi_qmsi_runtime spi_qmsi_mst_1_runtime;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(spi_master_1, CONFIG_SPI_1_NAME, spi_qmsi_init,
|
|
||||||
spi_master_qmsi_device_ctrl, &spi_qmsi_mst_1_runtime,
|
|
||||||
&spi_qmsi_mst_1_config, POST_KERNEL, CONFIG_SPI_INIT_PRIORITY,
|
|
||||||
NULL);
|
|
||||||
#endif /* CONFIG_SPI_1 */
|
|
||||||
|
|
@ -1,460 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright (c) 2016 Intel Corporation.
|
|
||||||
*
|
|
||||||
* SPDX-License-Identifier: Apache-2.0
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <errno.h>
|
|
||||||
|
|
||||||
#include <device.h>
|
|
||||||
#include <spi.h>
|
|
||||||
#include <gpio.h>
|
|
||||||
#include <board.h>
|
|
||||||
|
|
||||||
#include "qm_ss_spi.h"
|
|
||||||
#include "qm_ss_isr.h"
|
|
||||||
#include "ss_clk.h"
|
|
||||||
|
|
||||||
struct ss_pending_transfer {
|
|
||||||
struct device *dev;
|
|
||||||
qm_ss_spi_async_transfer_t xfer;
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct ss_pending_transfer pending_transfers[2];
|
|
||||||
|
|
||||||
struct ss_spi_qmsi_config {
|
|
||||||
qm_ss_spi_t spi;
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
char *cs_port;
|
|
||||||
u32_t cs_pin;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
struct ss_spi_qmsi_runtime {
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
struct device *gpio_cs;
|
|
||||||
#endif
|
|
||||||
struct k_sem device_sync_sem;
|
|
||||||
struct k_sem sem;
|
|
||||||
qm_ss_spi_config_t cfg;
|
|
||||||
int rc;
|
|
||||||
bool loopback;
|
|
||||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
||||||
u32_t device_power_state;
|
|
||||||
qm_ss_spi_context_t spi_ctx;
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static inline qm_ss_spi_bmode_t config_to_bmode(u8_t mode)
|
|
||||||
{
|
|
||||||
switch (mode) {
|
|
||||||
case SPI_MODE_CPHA:
|
|
||||||
return QM_SS_SPI_BMODE_1;
|
|
||||||
case SPI_MODE_CPOL:
|
|
||||||
return QM_SS_SPI_BMODE_2;
|
|
||||||
case SPI_MODE_CPOL | SPI_MODE_CPHA:
|
|
||||||
return QM_SS_SPI_BMODE_3;
|
|
||||||
default:
|
|
||||||
return QM_SS_SPI_BMODE_0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
static void spi_control_cs(struct device *dev, bool active)
|
|
||||||
{
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
const struct ss_spi_qmsi_config *config = dev->config->config_info;
|
|
||||||
struct device *gpio = context->gpio_cs;
|
|
||||||
|
|
||||||
if (!gpio)
|
|
||||||
return;
|
|
||||||
|
|
||||||
gpio_pin_write(gpio, config->cs_pin, !active);
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static int ss_spi_qmsi_configure(struct device *dev,
|
|
||||||
struct spi_config *config)
|
|
||||||
{
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
qm_ss_spi_config_t *cfg = &context->cfg;
|
|
||||||
|
|
||||||
cfg->frame_size = SPI_WORD_SIZE_GET(config->config) - 1;
|
|
||||||
cfg->bus_mode = config_to_bmode(SPI_MODE(config->config));
|
|
||||||
/* As loopback is implemented inside the controller,
|
|
||||||
* the bus mode doesn't matter.
|
|
||||||
*/
|
|
||||||
context->loopback = SPI_MODE(config->config) & SPI_MODE_LOOP;
|
|
||||||
cfg->clk_divider = config->max_sys_freq;
|
|
||||||
|
|
||||||
/* Will set the configuration before the transfer starts */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static void spi_qmsi_callback(void *data, int error, qm_ss_spi_status_t status,
|
|
||||||
u16_t len)
|
|
||||||
{
|
|
||||||
const struct ss_spi_qmsi_config *spi_config =
|
|
||||||
((struct device *)data)->config->config_info;
|
|
||||||
qm_ss_spi_t spi_id = spi_config->spi;
|
|
||||||
struct ss_pending_transfer *pending = &pending_transfers[spi_id];
|
|
||||||
struct device *dev = pending->dev;
|
|
||||||
struct ss_spi_qmsi_runtime *context;
|
|
||||||
|
|
||||||
if (!dev)
|
|
||||||
return;
|
|
||||||
|
|
||||||
context = dev->driver_data;
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
spi_control_cs(dev, false);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
pending->dev = NULL;
|
|
||||||
context->rc = error;
|
|
||||||
k_sem_give(&context->device_sync_sem);
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ss_spi_qmsi_slave_select(struct device *dev, u32_t slave)
|
|
||||||
{
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
qm_ss_spi_t spi_id = spi_config->spi;
|
|
||||||
|
|
||||||
return qm_ss_spi_slave_select(spi_id, 1 << (slave - 1)) ? -EIO : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static inline u8_t frame_size_to_dfs(qm_ss_spi_frame_size_t frame_size)
|
|
||||||
{
|
|
||||||
if (frame_size <= QM_SS_SPI_FRAME_SIZE_8_BIT) {
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (frame_size <= QM_SS_SPI_FRAME_SIZE_16_BIT) {
|
|
||||||
return 2;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* This should never happen, it will crash later on. */
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ss_spi_qmsi_transceive(struct device *dev,
|
|
||||||
const void *tx_buf, u32_t tx_buf_len,
|
|
||||||
void *rx_buf, u32_t rx_buf_len)
|
|
||||||
{
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
qm_ss_spi_t spi_id = spi_config->spi;
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
qm_ss_spi_config_t *cfg = &context->cfg;
|
|
||||||
u8_t dfs = frame_size_to_dfs(cfg->frame_size);
|
|
||||||
qm_ss_spi_async_transfer_t *xfer;
|
|
||||||
int rc;
|
|
||||||
|
|
||||||
k_sem_take(&context->sem, K_FOREVER);
|
|
||||||
if (pending_transfers[spi_id].dev) {
|
|
||||||
k_sem_give(&context->sem);
|
|
||||||
return -EBUSY;
|
|
||||||
}
|
|
||||||
pending_transfers[spi_id].dev = dev;
|
|
||||||
k_sem_give(&context->sem);
|
|
||||||
|
|
||||||
device_busy_set(dev);
|
|
||||||
|
|
||||||
xfer = &pending_transfers[spi_id].xfer;
|
|
||||||
|
|
||||||
xfer->rx = rx_buf;
|
|
||||||
xfer->rx_len = rx_buf_len / dfs;
|
|
||||||
xfer->tx = (u8_t *)tx_buf;
|
|
||||||
xfer->tx_len = tx_buf_len / dfs;
|
|
||||||
xfer->callback_data = dev;
|
|
||||||
xfer->callback = spi_qmsi_callback;
|
|
||||||
|
|
||||||
if (tx_buf_len == 0) {
|
|
||||||
cfg->transfer_mode = QM_SS_SPI_TMOD_RX;
|
|
||||||
} else if (rx_buf_len == 0) {
|
|
||||||
cfg->transfer_mode = QM_SS_SPI_TMOD_TX;
|
|
||||||
} else {
|
|
||||||
cfg->transfer_mode = QM_SS_SPI_TMOD_TX_RX;
|
|
||||||
}
|
|
||||||
|
|
||||||
if (context->loopback) {
|
|
||||||
u32_t ctrl;
|
|
||||||
|
|
||||||
if (spi_id == 0) {
|
|
||||||
ctrl = __builtin_arc_lr(QM_SS_SPI_0_BASE +
|
|
||||||
QM_SS_SPI_CTRL);
|
|
||||||
ctrl |= BIT(11);
|
|
||||||
__builtin_arc_sr(ctrl, QM_SS_SPI_0_BASE +
|
|
||||||
QM_SS_SPI_CTRL);
|
|
||||||
} else {
|
|
||||||
ctrl = __builtin_arc_lr(QM_SS_SPI_1_BASE +
|
|
||||||
QM_SS_SPI_CTRL);
|
|
||||||
ctrl |= BIT(11);
|
|
||||||
__builtin_arc_sr(ctrl, QM_SS_SPI_1_BASE +
|
|
||||||
QM_SS_SPI_CTRL);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
rc = qm_ss_spi_set_config(spi_id, cfg);
|
|
||||||
if (rc != 0) {
|
|
||||||
device_busy_clear(dev);
|
|
||||||
return -EINVAL;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
spi_control_cs(dev, true);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
rc = qm_ss_spi_irq_transfer(spi_id, xfer);
|
|
||||||
if (rc != 0) {
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
spi_control_cs(dev, false);
|
|
||||||
#endif
|
|
||||||
device_busy_clear(dev);
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
k_sem_take(&context->device_sync_sem, K_FOREVER);
|
|
||||||
|
|
||||||
device_busy_clear(dev);
|
|
||||||
return context->rc ? -EIO : 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static const struct spi_driver_api ss_spi_qmsi_api = {
|
|
||||||
.configure = ss_spi_qmsi_configure,
|
|
||||||
.slave_select = ss_spi_qmsi_slave_select,
|
|
||||||
.transceive = ss_spi_qmsi_transceive,
|
|
||||||
};
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
static struct device *gpio_cs_init(const struct ss_spi_qmsi_config *config)
|
|
||||||
{
|
|
||||||
struct device *gpio;
|
|
||||||
|
|
||||||
if (!config->cs_port)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
gpio = device_get_binding(config->cs_port);
|
|
||||||
if (!gpio)
|
|
||||||
return NULL;
|
|
||||||
|
|
||||||
gpio_pin_configure(gpio, config->cs_pin, GPIO_DIR_OUT);
|
|
||||||
gpio_pin_write(gpio, config->cs_pin, 1);
|
|
||||||
|
|
||||||
return gpio;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static int ss_spi_qmsi_init(struct device *dev);
|
|
||||||
|
|
||||||
|
|
||||||
#ifdef CONFIG_DEVICE_POWER_MANAGEMENT
|
|
||||||
static void ss_spi_master_set_power_state(struct device *dev,
|
|
||||||
u32_t power_state)
|
|
||||||
{
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
|
|
||||||
context->device_power_state = power_state;
|
|
||||||
}
|
|
||||||
|
|
||||||
static u32_t ss_spi_master_get_power_state(struct device *dev)
|
|
||||||
{
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
|
|
||||||
return context->device_power_state;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ss_spi_master_suspend_device(struct device *dev)
|
|
||||||
{
|
|
||||||
if (device_busy_check(dev)) {
|
|
||||||
return -EBUSY;
|
|
||||||
}
|
|
||||||
|
|
||||||
const struct ss_spi_qmsi_config *config = dev->config->config_info;
|
|
||||||
struct ss_spi_qmsi_runtime *drv_data = dev->driver_data;
|
|
||||||
|
|
||||||
qm_ss_spi_save_context(config->spi, &drv_data->spi_ctx);
|
|
||||||
|
|
||||||
ss_spi_master_set_power_state(dev, DEVICE_PM_SUSPEND_STATE);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ss_spi_master_resume_device_from_suspend(struct device *dev)
|
|
||||||
{
|
|
||||||
const struct ss_spi_qmsi_config *config = dev->config->config_info;
|
|
||||||
struct ss_spi_qmsi_runtime *drv_data = dev->driver_data;
|
|
||||||
|
|
||||||
qm_ss_spi_restore_context(config->spi, &drv_data->spi_ctx);
|
|
||||||
|
|
||||||
ss_spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Implements the driver control management functionality
|
|
||||||
* the *context may include IN data or/and OUT data
|
|
||||||
*/
|
|
||||||
static int ss_spi_master_qmsi_device_ctrl(struct device *port,
|
|
||||||
u32_t ctrl_command, void *context)
|
|
||||||
{
|
|
||||||
if (ctrl_command == DEVICE_PM_SET_POWER_STATE) {
|
|
||||||
if (*((u32_t *)context) == DEVICE_PM_SUSPEND_STATE) {
|
|
||||||
return ss_spi_master_suspend_device(port);
|
|
||||||
} else if (*((u32_t *)context) == DEVICE_PM_ACTIVE_STATE) {
|
|
||||||
return ss_spi_master_resume_device_from_suspend(port);
|
|
||||||
}
|
|
||||||
} else if (ctrl_command == DEVICE_PM_GET_POWER_STATE) {
|
|
||||||
*((u32_t *)context) = ss_spi_master_get_power_state(port);
|
|
||||||
}
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#else
|
|
||||||
#define ss_spi_master_set_power_state(...)
|
|
||||||
#endif /* CONFIG_DEVICE_POWER_MANAGEMENT */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_0
|
|
||||||
static const struct ss_spi_qmsi_config spi_qmsi_mst_0_config = {
|
|
||||||
.spi = QM_SS_SPI_0,
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
.cs_port = CONFIG_SPI_SS_0_CS_GPIO_PORT,
|
|
||||||
.cs_pin = CONFIG_SPI_SS_0_CS_GPIO_PIN,
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct ss_spi_qmsi_runtime spi_qmsi_mst_0_runtime;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(ss_spi_master_0, CONFIG_SPI_SS_0_NAME, ss_spi_qmsi_init,
|
|
||||||
ss_spi_master_qmsi_device_ctrl, &spi_qmsi_mst_0_runtime,
|
|
||||||
&spi_qmsi_mst_0_config, POST_KERNEL, CONFIG_SPI_SS_INIT_PRIORITY,
|
|
||||||
NULL);
|
|
||||||
#endif /* CONFIG_SPI_SS_0 */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_1
|
|
||||||
static const struct ss_spi_qmsi_config spi_qmsi_mst_1_config = {
|
|
||||||
.spi = QM_SS_SPI_1,
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
.cs_port = CONFIG_SPI_SS_1_CS_GPIO_PORT,
|
|
||||||
.cs_pin = CONFIG_SPI_SS_1_CS_GPIO_PIN,
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
static struct ss_spi_qmsi_runtime spi_qmsi_mst_1_runtime;
|
|
||||||
|
|
||||||
DEVICE_DEFINE(ss_spi_master_1, CONFIG_SPI_SS_1_NAME, ss_spi_qmsi_init,
|
|
||||||
ss_spi_master_qmsi_device_ctrl, &spi_qmsi_mst_1_runtime,
|
|
||||||
&spi_qmsi_mst_1_config, POST_KERNEL, CONFIG_SPI_SS_INIT_PRIORITY,
|
|
||||||
NULL);
|
|
||||||
#endif /* CONFIG_SPI_SS_1 */
|
|
||||||
|
|
||||||
static void ss_spi_err_isr(void *arg)
|
|
||||||
{
|
|
||||||
struct device *dev = arg;
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
|
|
||||||
if (spi_config->spi == QM_SS_SPI_0) {
|
|
||||||
qm_ss_spi_0_error_isr(NULL);
|
|
||||||
} else {
|
|
||||||
qm_ss_spi_1_error_isr(NULL);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ss_spi_rx_isr(void *arg)
|
|
||||||
{
|
|
||||||
struct device *dev = arg;
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
|
|
||||||
if (spi_config->spi == QM_SS_SPI_0) {
|
|
||||||
qm_ss_spi_0_rx_avail_isr(NULL);
|
|
||||||
} else {
|
|
||||||
qm_ss_spi_1_rx_avail_isr(NULL);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static void ss_spi_tx_isr(void *arg)
|
|
||||||
{
|
|
||||||
struct device *dev = arg;
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
|
|
||||||
if (spi_config->spi == QM_SS_SPI_0) {
|
|
||||||
qm_ss_spi_0_tx_req_isr(NULL);
|
|
||||||
} else {
|
|
||||||
qm_ss_spi_1_tx_req_isr(NULL);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
static int ss_spi_qmsi_init(struct device *dev)
|
|
||||||
{
|
|
||||||
const struct ss_spi_qmsi_config *spi_config = dev->config->config_info;
|
|
||||||
struct ss_spi_qmsi_runtime *context = dev->driver_data;
|
|
||||||
u32_t *scss_intmask = NULL;
|
|
||||||
|
|
||||||
switch (spi_config->spi) {
|
|
||||||
#ifdef CONFIG_SPI_SS_0
|
|
||||||
case QM_SS_SPI_0:
|
|
||||||
IRQ_CONNECT(IRQ_SPI0_ERR_INT, CONFIG_SPI_SS_0_IRQ_PRI,
|
|
||||||
ss_spi_err_isr, DEVICE_GET(ss_spi_master_0), 0);
|
|
||||||
irq_enable(IRQ_SPI0_ERR_INT);
|
|
||||||
|
|
||||||
IRQ_CONNECT(IRQ_SPI0_RX_AVAIL, CONFIG_SPI_SS_0_IRQ_PRI,
|
|
||||||
ss_spi_rx_isr, DEVICE_GET(ss_spi_master_0), 0);
|
|
||||||
irq_enable(IRQ_SPI0_RX_AVAIL);
|
|
||||||
|
|
||||||
IRQ_CONNECT(IRQ_SPI0_TX_REQ, CONFIG_SPI_SS_0_IRQ_PRI,
|
|
||||||
ss_spi_tx_isr, DEVICE_GET(ss_spi_master_0), 0);
|
|
||||||
irq_enable(IRQ_SPI0_TX_REQ);
|
|
||||||
|
|
||||||
ss_clk_spi_enable(0);
|
|
||||||
|
|
||||||
/* Route SPI interrupts to Sensor Subsystem */
|
|
||||||
scss_intmask = (u32_t *)&QM_INTERRUPT_ROUTER->ss_spi_0_int;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
scss_intmask++;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
scss_intmask++;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
break;
|
|
||||||
#endif /* CONFIG_SPI_SS_0 */
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_1
|
|
||||||
case QM_SS_SPI_1:
|
|
||||||
IRQ_CONNECT(IRQ_SPI1_ERR_INT, CONFIG_SPI_SS_1_IRQ_PRI,
|
|
||||||
ss_spi_err_isr, DEVICE_GET(ss_spi_master_1), 0);
|
|
||||||
irq_enable(IRQ_SPI1_ERR_INT);
|
|
||||||
|
|
||||||
IRQ_CONNECT(IRQ_SPI1_RX_AVAIL, CONFIG_SPI_SS_1_IRQ_PRI,
|
|
||||||
ss_spi_rx_isr, DEVICE_GET(ss_spi_master_1), 0);
|
|
||||||
irq_enable(IRQ_SPI1_RX_AVAIL);
|
|
||||||
|
|
||||||
IRQ_CONNECT(IRQ_SPI1_TX_REQ, CONFIG_SPI_SS_1_IRQ_PRI,
|
|
||||||
ss_spi_tx_isr, DEVICE_GET(ss_spi_master_1), 0);
|
|
||||||
irq_enable(IRQ_SPI1_TX_REQ);
|
|
||||||
|
|
||||||
ss_clk_spi_enable(1);
|
|
||||||
|
|
||||||
/* Route SPI interrupts to Sensor Subsystem */
|
|
||||||
scss_intmask = (u32_t *)&QM_INTERRUPT_ROUTER->ss_spi_1_int;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
scss_intmask++;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
scss_intmask++;
|
|
||||||
*scss_intmask &= ~BIT(8);
|
|
||||||
break;
|
|
||||||
#endif /* CONFIG_SPI_SS_1 */
|
|
||||||
|
|
||||||
default:
|
|
||||||
return -EIO;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPI_SS_CS_GPIO
|
|
||||||
context->gpio_cs = gpio_cs_init(spi_config);
|
|
||||||
#endif
|
|
||||||
k_sem_init(&context->device_sync_sem, 0, UINT_MAX);
|
|
||||||
k_sem_init(&context->sem, 1, UINT_MAX);
|
|
||||||
|
|
||||||
ss_spi_master_set_power_state(dev, DEVICE_PM_ACTIVE_STATE);
|
|
||||||
|
|
||||||
dev->driver_api = &ss_spi_qmsi_api;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
Loading…
Add table
Add a link
Reference in a new issue