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cavs: fix shim register location on 1.8 and above

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Shim register location on cAVS 1.5 is different than on 1.8 and up,
fix it.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
This commit is contained in:
Guennadi Liakhovetski 2020-10-07 09:40:33 +02:00 • committed by Anas Nashif
commit 0a3fa97fbe
1 changed files with 7 additions and 1 deletions
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8
soc/xtensa/intel_adsp/common/include/soc.h
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@ -7,6 +7,8 @@
#include <string.h>
#include <errno.h>
#include <cavs/version.h>
#include <sys/sys_io.h>
#include <adsp/cache.h>
@ -61,10 +63,14 @@
#define SSP_MN_DIV_BASE(x) \
(0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
#define PDM_BASE 0x00010000
#define PDM_BASE DMIC_BASE
/* SOC DSP SHIM Registers */
#if CAVS_VERSION == CAVS_VERSION_1_5
#define SOC_DSP_SHIM_REG_BASE 0x00001000
#else
#define SOC_DSP_SHIM_REG_BASE 0x00071f00
#endif
/* SOC DSP SHIM Register - Clock Control */
#define SOC_CLKCTL_REQ_AUDIO_PLL_CLK BIT(31)