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ext: update nxp mcux lpc sdk

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Update to latest MCUXpresso SDK 2.5.1 for LPC family.
Added LPC55S69 device.

Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
This commit is contained in:
Andrei Gansari 2019-05-15 14:49:27 +03:00 • committed by Maureen Helm
commit 09fdce9aab
70 changed files with 237740 additions and 1004 deletions
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11
ext/hal/nxp/mcux/CMakeLists.txt
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@ -7,6 +7,12 @@ if("${MCUX_DEVICE}" STREQUAL "LPC54114")
elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0") elseif("${MCUX_DEVICE}" STREQUAL "LPC54114_M0")
set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus) set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm0plus)
set(MCUX_DEVICE LPC54114) set(MCUX_DEVICE LPC54114)
elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU0")
set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core0)
set(MCUX_DEVICE LPC55S69)
elseif("${MCUX_DEVICE}" STREQUAL "LPC55S69_CPU1")
set(MCUX_CPU CPU_${CONFIG_SOC_PART_NUMBER}_cm33_core1)
set(MCUX_DEVICE LPC55S69)
elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052") elseif("${MCUX_DEVICE}" STREQUAL "MIMXRT1052")
string(REGEX REPLACE "(.*)[AB]$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER}) string(REGEX REPLACE "(.*)[AB]$" "CPU_\\1B" MCUX_CPU ${CONFIG_SOC_PART_NUMBER})
else() else()
@ -26,6 +32,11 @@ zephyr_compile_definitions(${MCUX_CPU})
# practice, drilling down like this avoids the need for repetitive # practice, drilling down like this avoids the need for repetitive
# build scripts for every mcux device. # build scripts for every mcux device.
zephyr_sources(devices/${MCUX_DEVICE}/fsl_clock.c) zephyr_sources(devices/${MCUX_DEVICE}/fsl_clock.c)
if (${MCUX_DEVICE} MATCHES "LPC")
zephyr_sources(devices/${MCUX_DEVICE}/fsl_power.c)
zephyr_sources(devices/${MCUX_DEVICE}/fsl_reset.c)
endif()
# Build mcux drivers that can be used for multiple SoC's. # Build mcux drivers that can be used for multiple SoC's.
add_subdirectory(boards) add_subdirectory(boards)

1
ext/hal/nxp/mcux/README
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@ -17,6 +17,7 @@ Status:
---------------------------------------------------------------------------- ----------------------------------------------------------------------------
MIMXRT1015 SDK 2.5.0 (2019-03-11) REL_2.5.0_RT1015_RFP MIMXRT1015 SDK 2.5.0 (2019-03-11) REL_2.5.0_RT1015_RFP
LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 LPC54114 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
LPC55S69 SDK 2.5.1 (2019-04-18) 207 2019-04-18
MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MIMXRT1051 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MIMXRT1052 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1
MIMXRT1061 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1 MIMXRT1061 SDK 2.5.0 (2018-12-17) REL_2.5.0_REL9_RFP_RC3_7_1

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ext/hal/nxp/mcux/devices/LPC55S69/LPC55S69_cm33_core0.h Normal file
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ext/hal/nxp/mcux/devices/LPC55S69/LPC55S69_cm33_core0_features.h Normal file
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@ -0,0 +1,292 @@
/*
** ###################################################################
** Version: rev. 1.0, 2018-08-22
** Build: b190122
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
#ifndef _LPC55S69_cm33_core0_FEATURES_H_
#define _LPC55S69_cm33_core0_FEATURES_H_
/* SOC module features */
/* @brief CASPER availability on the SoC. */
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (2)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (2)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
/* @brief SECGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
/* @brief HASHCRYPT availability on the SoC. */
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (8)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (8)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (1)
/* @brief OSTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief SECPINT availability on the SoC. */
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief POWERQUAD availability on the SoC. */
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
/* @brief RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (1)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (9)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief SYSCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (8)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* LPADC module features */
/* @brief FIFO availability on the SoC. */
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
/* @brief Has calibration (bitfield CFG[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
/* @brief Has offset trim (register OFSTRIM). */
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
/* @brief Interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
/* HASHCRYPT module features */
/* @brief the address of alias offset */
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
/* I2S module features */
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
/* IOCON module features */
/* @brief Func bit field width */
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
/* MAILBOX module features */
/* @brief Mailbox side for current core */
#define FSL_FEATURE_MAILBOX_SIDE_A (1)
/* MRT module features */
/* @brief number of channels. */
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
/* POWERLIB module features */
/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
/* POWERQUAD module features */
/* @brief Sine and Cossine fix errata */
#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
/* PUF module features */
/* @brief Number of PUF key slots available on device. */
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
/* SCT module features */
/* @brief Number of events */
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
/* @brief Number of states */
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
/* @brief Number of outputs */
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
/* SDIF module features */
/* @brief FIFO depth, every location is a WORD */
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
/* @brief Max DMA buffer size */
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
/* @brief Max source clock in HZ */
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
/* @brief support 2 cards */
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
/* SECPINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
/* SYSCON module features */
/* @brief Pointer to ROM IAP entry functions */
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
/* @brief Has Power Down mode */
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* USB module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USB version */
#define FSL_FEATURE_USB_VERSION (200)
/* @brief Number of the endpoint in USB FS */
#define FSL_FEATURE_USB_EP_NUM (5)
/* USBFSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBFSH version */
#define FSL_FEATURE_USBFSH_VERSION (200)
/* USBHSD module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBHSD_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBHSD_EP_NUM (6)
/* USBHSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
/* UTICK module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* WWDT module features */
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
/* @brief WWDT does not support power down configure */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
#endif /* _LPC55S69_cm33_core0_FEATURES_H_ */

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@ -0,0 +1,292 @@
/*
** ###################################################################
** Version: rev. 1.0, 2018-08-22
** Build: b190122
**
** Abstract:
** Chip specific module features.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2019 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
#ifndef _LPC55S69_cm33_core1_FEATURES_H_
#define _LPC55S69_cm33_core1_FEATURES_H_
/* SOC module features */
/* @brief CASPER availability on the SoC. */
#define FSL_FEATURE_SOC_CASPER_COUNT (1)
/* @brief CRC availability on the SoC. */
#define FSL_FEATURE_SOC_CRC_COUNT (1)
/* @brief CTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_CTIMER_COUNT (5)
/* @brief DMA availability on the SoC. */
#define FSL_FEATURE_SOC_DMA_COUNT (2)
/* @brief FLASH availability on the SoC. */
#define FSL_FEATURE_SOC_FLASH_COUNT (1)
/* @brief FLEXCOMM availability on the SoC. */
#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (9)
/* @brief GINT availability on the SoC. */
#define FSL_FEATURE_SOC_GINT_COUNT (2)
/* @brief GPIO availability on the SoC. */
#define FSL_FEATURE_SOC_GPIO_COUNT (1)
/* @brief SECGPIO availability on the SoC. */
#define FSL_FEATURE_SOC_SECGPIO_COUNT (1)
/* @brief HASHCRYPT availability on the SoC. */
#define FSL_FEATURE_SOC_HASHCRYPT_COUNT (1)
/* @brief I2C availability on the SoC. */
#define FSL_FEATURE_SOC_I2C_COUNT (8)
/* @brief I2S availability on the SoC. */
#define FSL_FEATURE_SOC_I2S_COUNT (8)
/* @brief INPUTMUX availability on the SoC. */
#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1)
/* @brief IOCON availability on the SoC. */
#define FSL_FEATURE_SOC_IOCON_COUNT (1)
/* @brief LPADC availability on the SoC. */
#define FSL_FEATURE_SOC_LPADC_COUNT (1)
/* @brief MAILBOX availability on the SoC. */
#define FSL_FEATURE_SOC_MAILBOX_COUNT (1)
/* @brief MRT availability on the SoC. */
#define FSL_FEATURE_SOC_MRT_COUNT (1)
/* @brief OSTIMER availability on the SoC. */
#define FSL_FEATURE_SOC_OSTIMER_COUNT (1)
/* @brief PINT availability on the SoC. */
#define FSL_FEATURE_SOC_PINT_COUNT (1)
/* @brief SECPINT availability on the SoC. */
#define FSL_FEATURE_SOC_SECPINT_COUNT (1)
/* @brief PMC availability on the SoC. */
#define FSL_FEATURE_SOC_PMC_COUNT (1)
/* @brief POWERQUAD availability on the SoC. */
#define FSL_FEATURE_SOC_POWERQUAD_COUNT (1)
/* @brief PUF availability on the SoC. */
#define FSL_FEATURE_SOC_PUF_COUNT (1)
/* @brief RNG1 availability on the SoC. */
#define FSL_FEATURE_SOC_LPC_RNG1_COUNT (1)
/* @brief RTC availability on the SoC. */
#define FSL_FEATURE_SOC_RTC_COUNT (1)
/* @brief SCT availability on the SoC. */
#define FSL_FEATURE_SOC_SCT_COUNT (1)
/* @brief SDIF availability on the SoC. */
#define FSL_FEATURE_SOC_SDIF_COUNT (1)
/* @brief SPI availability on the SoC. */
#define FSL_FEATURE_SOC_SPI_COUNT (9)
/* @brief SYSCON availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCON_COUNT (1)
/* @brief SYSCTL1 availability on the SoC. */
#define FSL_FEATURE_SOC_SYSCTL1_COUNT (1)
/* @brief USART availability on the SoC. */
#define FSL_FEATURE_SOC_USART_COUNT (8)
/* @brief USB availability on the SoC. */
#define FSL_FEATURE_SOC_USB_COUNT (1)
/* @brief USBFSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBFSH_COUNT (1)
/* @brief USBHSD availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSD_COUNT (1)
/* @brief USBHSH availability on the SoC. */
#define FSL_FEATURE_SOC_USBHSH_COUNT (1)
/* @brief USBPHY availability on the SoC. */
#define FSL_FEATURE_SOC_USBPHY_COUNT (1)
/* @brief UTICK availability on the SoC. */
#define FSL_FEATURE_SOC_UTICK_COUNT (1)
/* @brief WWDT availability on the SoC. */
#define FSL_FEATURE_SOC_WWDT_COUNT (1)
/* LPADC module features */
/* @brief FIFO availability on the SoC. */
#define FSL_FEATURE_LPADC_FIFO_COUNT (2)
/* @brief Has differential mode (bitfield CMDLn[DIFF]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_DIFF (0)
/* @brief Has channel scale (bitfield CMDLn[CSCALE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CSCALE (0)
/* @brief Has conversion type select (bitfield CMDLn[CTYPE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_CTYPE (1)
/* @brief Has conversion resolution select (bitfield CMDLn[MODE]). */
#define FSL_FEATURE_LPADC_HAS_CMDL_MODE (1)
/* @brief Has compare function enable (bitfield CMDHn[CMPEN]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_CMPEN (1)
/* @brief Has Wait for trigger assertion before execution (bitfield CMDHn[WAIT_TRIG]). */
#define FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG (1)
/* @brief Has offset calibration (bitfield CTRL[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CALOFS (1)
/* @brief Has gain calibration (bitfield CTRL[CAL_REQ]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ (1)
/* @brief Has calibration average (bitfield CTRL[CAL_AVGS]). */
#define FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS (1)
/* @brief Has internal clock (bitfield CFG[ADCKEN]). */
#define FSL_FEATURE_LPADC_HAS_CFG_ADCKEN (0)
/* @brief Enable support for low voltage reference on option 1 reference (bitfield CFG[VREF1RNG]). */
#define FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG (0)
/* @brief Has calibration (bitfield CFG[CALOFS]). */
#define FSL_FEATURE_LPADC_HAS_CFG_CALOFS (0)
/* @brief Has offset trim (register OFSTRIM). */
#define FSL_FEATURE_LPADC_HAS_OFSTRIM (1)
/* CASPER module features */
/* @brief Base address of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_BASE_ADDRESS (0x04000000)
/* @brief Interleaving of the CASPER dedicated RAM */
#define FSL_FEATURE_CASPER_RAM_IS_INTERLEAVED (1)
/* DMA module features */
/* @brief Number of channels */
#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30)
/* HASHCRYPT module features */
/* @brief the address of alias offset */
#define FSL_FEATURE_HASHCRYPT_ALIAS_OFFSET (0x00000000)
/* I2S module features */
/* @brief I2S support dual channel transfer. */
#define FSL_FEATURE_I2S_SUPPORT_SECONDARY_CHANNEL (1)
/* IOCON module features */
/* @brief Func bit field width */
#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4)
/* MAILBOX module features */
/* @brief Mailbox side for current core */
#define FSL_FEATURE_MAILBOX_SIDE_B (1)
/* MRT module features */
/* @brief number of channels. */
#define FSL_FEATURE_MRT_NUMBER_OF_CHANNELS (4)
/* PINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (10)
/* POWERLIB module features */
/* @brief Niobe4's Powerlib API is different with other LPC series devices. */
#define FSL_FEATURE_POWERLIB_NIOBE4_EXTEND (1)
/* POWERQUAD module features */
/* @brief Sine and Cossine fix errata */
#define FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA (1)
/* PUF module features */
/* @brief Number of PUF key slots available on device. */
#define FSL_FEATURE_PUF_HAS_KEYSLOTS (4)
/* @brief the shift status value */
#define FSL_FEATURE_PUF_HAS_SHIFT_STATUS (1)
/* SCT module features */
/* @brief Number of events */
#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (16)
/* @brief Number of states */
#define FSL_FEATURE_SCT_NUMBER_OF_STATES (32)
/* @brief Number of match capture */
#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (16)
/* @brief Number of outputs */
#define FSL_FEATURE_SCT_NUMBER_OF_OUTPUTS (10)
/* SDIF module features */
/* @brief FIFO depth, every location is a WORD */
#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64)
/* @brief Max DMA buffer size */
#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096)
/* @brief Max source clock in HZ */
#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000)
/* @brief support 2 cards */
#define FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD (1)
/* SECPINT module features */
/* @brief Number of connected outputs */
#define FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS (2)
/* SYSCON module features */
/* @brief Pointer to ROM IAP entry functions */
#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205)
/* @brief Flash page size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (512)
/* @brief Flash sector size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768)
/* @brief Flash size in bytes */
#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (622592)
/* @brief Has Power Down mode */
#define FSL_FEATURE_SYSCON_HAS_POWERDOWN_MODE (1)
/* @brief CCM_ANALOG availability on the SoC. */
#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (1)
/* USB module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USB version */
#define FSL_FEATURE_USB_VERSION (200)
/* @brief Number of the endpoint in USB FS */
#define FSL_FEATURE_USB_EP_NUM (5)
/* USBFSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBFSH version */
#define FSL_FEATURE_USBFSH_VERSION (200)
/* USBHSD module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSD version */
#define FSL_FEATURE_USBHSD_VERSION (300)
/* @brief Number of the endpoint in USB HS */
#define FSL_FEATURE_USBHSD_EP_NUM (6)
/* USBHSH module features */
/* @brief Size of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM (0x00004000)
/* @brief Base address of the USB dedicated RAM */
#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000)
/* @brief USBHSH version */
#define FSL_FEATURE_USBHSH_VERSION (300)
/* UTICK module features */
/* @brief UTICK does not support PD configure. */
#define FSL_FEATURE_UTICK_HAS_NO_PDCFG (1)
/* WWDT module features */
/* @brief WWDT does not support oscillator lock. */
#define FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK (1)
/* @brief WWDT does not support power down configure */
#define FSL_FEATURE_WWDT_HAS_NO_PDCFG (1)
#endif /* _LPC55S69_cm33_core1_FEATURES_H_ */

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/*
* Copyright 2014-2016 Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef __FSL_DEVICE_REGISTERS_H__
#define __FSL_DEVICE_REGISTERS_H__
/*
* Include the cpu specific register header files.
*
* The CPU macro should be declared in the project or makefile.
*/
#if (defined(CPU_LPC55S69JBD100_cm33_core0) || defined(CPU_LPC55S69JET98_cm33_core0))
#define LPC55S69_cm33_core0_SERIES
/* CMSIS-style register definitions */
#include "LPC55S69_cm33_core0.h"
/* CPU specific feature definitions */
#include "LPC55S69_cm33_core0_features.h"
#elif (defined(CPU_LPC55S69JBD100_cm33_core1) || defined(CPU_LPC55S69JET98_cm33_core1))
#define LPC55S69_cm33_core1_SERIES
/* CMSIS-style register definitions */
#include "LPC55S69_cm33_core1.h"
/* CPU specific feature definitions */
#include "LPC55S69_cm33_core1_features.h"
#else
#error "No valid CPU defined!"
#endif
#endif /* __FSL_DEVICE_REGISTERS_H__ */
/*******************************************************************************
* EOF
******************************************************************************/

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_power.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.power"
#endif
/*******************************************************************************
* Code
******************************************************************************/
/* Empty file since implementation is in header file and power library */

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/*
* Copyright (c) 2017, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_POWER_H_
#define _FSL_POWER_H_
#include "fsl_common.h"
#include "fsl_device_registers.h"
#include <stdint.h>
/*!
* @addtogroup power
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief power driver version 1.0.0. */
#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
/*@}*/
/** @brief Low Power main structure */
typedef enum
{
VD_AON = 0x0, /*!< Digital Always On power domain */
VD_MEM = 0x1, /*!< Memories (SRAM) power domain */
VD_DCDC = 0x2, /*!< Core logic power domain */
VD_DEEPSLEEP = 0x3 /*!< Core logic power domain */
} LPC_POWER_DOMAIN_T;
/** @brief Low Power main structure */
typedef struct
{ /* */
__IO uint32_t CFG; /*!< Low Power Mode Configuration, and miscallenous options */
__IO uint32_t PDCTRL0; /*!< Power Down control : controls power of various modules
in the different Low power modes, including ROM */
__IO uint32_t SRAMRETCTRL; /*!< Power Down control : controls power SRAM instances
in the different Low power modes */
__IO uint32_t CPURETCTRL; /*!< CPU0 retention control : controls CPU retention parameters in POWER DOWN modes */
__IO uint64_t VOLTAGE; /*!< Voltage control in Low Power Modes */
__IO uint64_t WAKEUPSRC; /*!< Wake up sources control for sleepcon */
__IO uint64_t WAKEUPINT; /*!< Wake up sources control for ARM */
__IO uint32_t HWWAKE; /*!< Interrupt that can postpone power down modes
in case an interrupt is pending when the processor request deepsleep */
__IO uint32_t WAKEUPIOSRC; /*!< Wake up I/O sources in DEEP POWER DOWN mode */
__IO uint32_t TIMERCFG; /*!< Wake up timers configuration */
__IO uint32_t TIMERCOUNT; /*!< Wake up Timer count*/
__IO uint32_t POWERCYCLE; /*!< Cancels entry in Low Power mode if set with 0xDEADABBA (might be used by some
interrupt handlers)*/
} LPC_LOWPOWER_T;
/* */
#define LOWPOWER_POWERCYCLE_CANCELLED 0xDEADABBA /*!< */
/* Low Power modes */
#define LOWPOWER_CFG_LPMODE_INDEX 0
#define LOWPOWER_CFG_LPMODE_MASK (0x3UL << LOWPOWER_CFG_LPMODE_INDEX)
#define LOWPOWER_CFG_SELCLOCK_INDEX 2
#define LOWPOWER_CFG_SELCLOCK_MASK (0x1UL << LOWPOWER_CFG_SELCLOCK_INDEX)
#define LOWPOWER_CFG_SELMEMSUPPLY_INDEX 3
#define LOWPOWER_CFG_SELMEMSUPPLY_MASK (0x1UL << LOWPOWER_CFG_SELMEMSUPPLY_INDEX)
#define LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX 4
#define LOWPOWER_CFG_MEMLOWPOWERMODE_MASK (0x1UL << LOWPOWER_CFG_MEMLOWPOWERMODE_INDEX)
#define LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX 5
#define LOWPOWER_CFG_LDODEEPSLEEPREF_MASK (0x1UL << LOWPOWER_CFG_LDODEEPSLEEPREF_INDEX)
#define LOWPOWER_CFG_LPMODE_ACTIVE 0 /*!< ACTIVE mode */
#define LOWPOWER_CFG_LPMODE_DEEPSLEEP 1 /*!< DEEP SLEEP mode */
#define LOWPOWER_CFG_LPMODE_POWERDOWN 2 /*!< POWER DOWN mode */
#define LOWPOWER_CFG_LPMODE_DEEPPOWERDOWN 3 /*!< DEEP POWER DOWN mode */
#define LOWPOWER_CFG_LPMODE_SLEEP 4 /*!< SLEEP mode */
#define LOWPOWER_CFG_SELCLOCK_1MHZ 0 /*!< The 1 MHz clock is used during the configuration of the PMC */
#define LOWPOWER_CFG_SELCLOCK_12MHZ 1 /*!< The 12 MHz clock is used during the configuration of the PMC (to speed up PMC configuration process)*/
#define LOWPOWER_CFG_SELMEMSUPPLY_LDOMEM 0 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_MEM */
#define LOWPOWER_CFG_SELMEMSUPPLY_LDODEEPSLEEP 1 /*!< In DEEP SLEEP power mode, the Memories are supplied by the LDO_DEEP_SLEEP (or DCDC) */
#define LOWPOWER_CFG_MEMLOWPOWERMODE_SOURCEBIASING 0 /*!< All SRAM instances use "Source Biasing" as low power mode technic (it is recommended to set LDO_MEM as high as possible -- 1.1V typical -- during low power mode) */
#define LOWPOWER_CFG_MEMLOWPOWERMODE_VOLTAGESCALING 1 /*!< All SRAM instances use "Voltage Scaling" as low power mode technic (it is recommended to set LDO_MEM as low as possible -- down to 0.7V -- during low power mode) */
#define LOWPOWER_CFG_LDODEEPSLEEPREF_FLASHBUFFER 0 /*!< LDO DEEP SLEEP uses Flash Buffer as reference */
#define LOWPOWER_CFG_LDODEEPSLEEPREF_BANDGAG0P8V 1 /*!< LDO DEEP SLEEP uses Band Gap 0.8V as reference */
/* CPU Retention Control*/
#define LOWPOWER_CPURETCTRL_ENA_INDEX 0
#define LOWPOWER_CPURETCTRL_ENA_MASK (0x1UL << LOWPOWER_CPURETCTRL_ENA_INDEX)
#define LOWPOWER_CPURETCTRL_MEMBASE_INDEX 1
#define LOWPOWER_CPURETCTRL_MEMBASE_MASK (0x1FFF << LOWPOWER_CPURETCTRL_MEMBASE_INDEX)
#define LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX 14
#define LOWPOWER_CPURETCTRL_RETDATALENGTH_MASK (0x3FFUL << LOWPOWER_CPURETCTRL_RETDATALENGTH_INDEX)
#define LOWPOWER_CPURETCTRL_ENA_DISABLE 0 /*!< In POWER DOWN mode, CPU Retention is disabled */
#define LOWPOWER_CPURETCTRL_ENA_ENABLE 1 /*!< In POWER DOWN mode, CPU Retention is enabled */
/**
* @brief Analog components power modes control during low power modes
*/
typedef enum pd_bits
{
kPDRUNCFG_PD_DCDC = (1UL << 0),
kPDRUNCFG_PD_BIAS = (1UL << 1),
kPDRUNCFG_PD_BODCORE = (1UL << 2),
kPDRUNCFG_PD_BODVBAT = (1UL << 3),
kPDRUNCFG_PD_FRO1M = (1UL << 4),
kPDRUNCFG_PD_FRO192M = (1UL << 5),
kPDRUNCFG_PD_FRO32K = (1UL << 6),
kPDRUNCFG_PD_XTAL32K = (1UL << 7),
kPDRUNCFG_PD_XTAL32M = (1UL << 8),
kPDRUNCFG_PD_PLL0 = (1UL << 9),
kPDRUNCFG_PD_PLL1 = (1UL << 10),
kPDRUNCFG_PD_USB0_PHY = (1UL << 11),
kPDRUNCFG_PD_USB1_PHY = (1UL << 12),
kPDRUNCFG_PD_COMP = (1UL << 13),
kPDRUNCFG_PD_TEMPSENS = (1UL << 14),
kPDRUNCFG_PD_GPADC = (1UL << 15),
kPDRUNCFG_PD_LDOMEM = (1UL << 16),
kPDRUNCFG_PD_LDODEEPSLEEP = (1UL << 17),
kPDRUNCFG_PD_LDOUSBHS = (1UL << 18),
kPDRUNCFG_PD_LDOGPADC = (1UL << 19),
kPDRUNCFG_PD_LDOXO32M = (1UL << 20),
kPDRUNCFG_PD_LDOFLASHNV = (1UL << 21),
kPDRUNCFG_PD_RNG = (1UL << 22),
kPDRUNCFG_PD_PLL0_SSCG = (1UL << 23),
kPDRUNCFG_PD_ROM = (1UL << 24),
/*
This enum member has no practical meaning,it is used to avoid MISRA issue,
user should not trying to use it.
*/
kPDRUNCFG_ForceUnsigned = 0x80000000U,
} pd_bit_t;
/**
* @brief SRAM instances retention control during low power modes
*/
#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX0 (1UL << 0) /*!< Enable SRAMX_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX1 (1UL << 1) /*!< Enable SRAMX_1 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX2 (1UL << 2) /*!< Enable SRAMX_2 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAMX3 (1UL << 3) /*!< Enable SRAMX_3 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM00 (1UL << 4) /*!< Enable SRAM0_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM01 (1UL << 5) /*!< Enable SRAM0_1 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM10 (1UL << 6) /*!< Enable SRAM1_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM20 (1UL << 7) /*!< Enable SRAM2_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM30 (1UL << 8) /*!< Enable SRAM3_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM31 (1UL << 9) /*!< Enable SRAM3_1 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM40 (1UL << 10) /*!< Enable SRAM4_0 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM41 (1UL << 11) /*!< Enable SRAM4_1 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM42 (1UL << 12) /*!< Enable SRAM4_2 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM43 (1UL << 13) /*!< Enable SRAM4_3 retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_USB_HS (1UL << 14) /*!< Enable SRAM USB HS retention when entering in Low power modes */
#define LOWPOWER_SRAMRETCTRL_RETEN_RAM_PUF (1UL << 15) /*!< Enable SRAM PUFF retention when entering in Low power modes */
/**
* @brief SRAM Low Power Modes
*/
#define LOWPOWER_SRAM_LPMODE_MASK (0xFUL)
#define LOWPOWER_SRAM_LPMODE_ACTIVE (0x6UL) /*!< SRAM functional mode */
#define LOWPOWER_SRAM_LPMODE_SLEEP (0xFUL) /*!< SRAM Sleep mode (Data retention, fast wake up) */
#define LOWPOWER_SRAM_LPMODE_DEEPSLEEP (0x8UL) /*!< SRAM Deep Sleep mode (Data retention, slow wake up) */
#define LOWPOWER_SRAM_LPMODE_SHUTDOWN (0x9UL) /*!< SRAM Shut Down mode (no data retention) */
#define LOWPOWER_SRAM_LPMODE_POWERUP (0xAUL) /*!< SRAM is powering up */
/*@brief BOD VBAT level */
typedef enum _power_bod_vbat_level
{
kPOWER_BodVbatLevel1000mv = 0, /*!< Brown out detector VBAT level 1V */
kPOWER_BodVbatLevel1100mv = 1, /*!< Brown out detector VBAT level 1.1V */
kPOWER_BodVbatLevel1200mv = 2, /*!< Brown out detector VBAT level 1.2V */
kPOWER_BodVbatLevel1300mv = 3, /*!< Brown out detector VBAT level 1.3V */
kPOWER_BodVbatLevel1400mv = 4, /*!< Brown out detector VBAT level 1.4V */
kPOWER_BodVbatLevel1500mv = 5, /*!< Brown out detector VBAT level 1.5V */
kPOWER_BodVbatLevel1600mv = 6, /*!< Brown out detector VBAT level 1.6V */
kPOWER_BodVbatLevel1650mv = 7, /*!< Brown out detector VBAT level 1.65V */
kPOWER_BodVbatLevel1700mv = 8, /*!< Brown out detector VBAT level 1.7V */
kPOWER_BodVbatLevel1750mv = 9, /*!< Brown out detector VBAT level 1.75V */
kPOWER_BodVbatLevel1800mv = 10, /*!< Brown out detector VBAT level 1.8V */
kPOWER_BodVbatLevel1900mv = 11, /*!< Brown out detector VBAT level 1.9V */
kPOWER_BodVbatLevel2000mv = 12, /*!< Brown out detector VBAT level 2V */
kPOWER_BodVbatLevel2100mv = 13, /*!< Brown out detector VBAT level 2.1V */
kPOWER_BodVbatLevel2200mv = 14, /*!< Brown out detector VBAT level 2.2V */
kPOWER_BodVbatLevel2300mv = 15, /*!< Brown out detector VBAT level 2.3V */
kPOWER_BodVbatLevel2400mv = 16, /*!< Brown out detector VBAT level 2.4V */
kPOWER_BodVbatLevel2500mv = 17, /*!< Brown out detector VBAT level 2.5V */
kPOWER_BodVbatLevel2600mv = 18, /*!< Brown out detector VBAT level 2.6V */
kPOWER_BodVbatLevel2700mv = 19, /*!< Brown out detector VBAT level 2.7V */
kPOWER_BodVbatLevel2806mv = 20, /*!< Brown out detector VBAT level 2.806V */
kPOWER_BodVbatLevel2900mv = 21, /*!< Brown out detector VBAT level 2.9V */
kPOWER_BodVbatLevel3000mv = 22, /*!< Brown out detector VBAT level 3.0V */
kPOWER_BodVbatLevel3100mv = 23, /*!< Brown out detector VBAT level 3.1V */
kPOWER_BodVbatLevel3200mv = 24, /*!< Brown out detector VBAT level 3.2V */
kPOWER_BodVbatLevel3300mv = 25, /*!< Brown out detector VBAT level 3.3V */
} power_bod_vbat_level_t;
/*@brief BOD core level */
typedef enum _power_bod_core_level
{
kPOWER_BodCoreLevel600mv = 0, /*!< Brown out detector core level 600mV */
kPOWER_BodCoreLevel650mv = 1, /*!< Brown out detector core level 650mV */
kPOWER_BodCoreLevel700mv = 2, /*!< Brown out detector core level 700mV */
kPOWER_BodCoreLevel750mv = 3, /*!< Brown out detector core level 750mV */
kPOWER_BodCoreLevel800mv = 4, /*!< Brown out detector core level 800mV */
kPOWER_BodCoreLevel850mv = 5, /*!< Brown out detector core level 850mV */
kPOWER_BodCoreLevel900mv = 6, /*!< Brown out detector core level 900mV */
kPOWER_BodCoreLevel950mv = 7, /*!< Brown out detector core level 950mV */
} power_bod_core_level_t;
/*@brief BOD Hysteresis control */
typedef enum _power_bod_hyst
{
kPOWER_BodHystLevel25mv = 0U, /*!< BOD Hysteresis control level 25mv */
kPOWER_BodHystLevel50mv = 1U, /*!< BOD Hysteresis control level 50mv */
kPOWER_BodHystLevel75mv = 2U, /*!< BOD Hysteresis control level 75mv */
kPOWER_BodHystLevel100mv = 3U, /*!< BOD Hysteresis control level 100mv */
} power_bod_hyst_t;
/**
* @brief LDO Voltage control in Low Power Modes
*/
#define LOWPOWER_VOLTAGE_LDO_PMU_INDEX 0
#define LOWPOWER_VOLTAGE_LDO_PMU_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_INDEX)
#define LOWPOWER_VOLTAGE_LDO_MEM_INDEX 5
#define LOWPOWER_VOLTAGE_LDO_MEM_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_INDEX)
#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX 10
#define LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_MASK (0x7ULL << LOWPOWER_VOLTAGE_LDO_DEEP_SLEEP_INDEX)
#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX 19
#define LOWPOWER_VOLTAGE_LDO_PMU_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_PMU_BOOST_INDEX)
#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX 24
#define LOWPOWER_VOLTAGE_LDO_MEM_BOOST_MASK (0x1FULL << LOWPOWER_VOLTAGE_LDO_MEM_BOOST_INDEX)
#define LOWPOWER_VOLTAGE_DCDC_INDEX 29
#define LOWPOWER_VOLTAGE_DCDC_MASK (0xFULL << LOWPOWER_VOLTAGE_DCDC_INDEX)
/**
* @brief Always On and Memories LDO voltage settings
*/
typedef enum _v_ao
{
// V_AO_1P220 1.22 = 0, /*!< 1.22 V */
V_AO_0P700 = 1, /*!< 0.7 V */
V_AO_0P725 = 2, /*!< 0.725 V */
V_AO_0P750 = 3, /*!< 0.75 V */
V_AO_0P775 = 4, /*!< 0.775 V */
V_AO_0P800 = 5, /*!< 0.8 V */
V_AO_0P825 = 6, /*!< 0.825 V */
V_AO_0P850 = 7, /*!< 0.85 V */
V_AO_0P875 = 8, /*!< 0.875 V */
V_AO_0P900 = 9, /*!< 0.9 V */
V_AO_0P960 = 10, /*!< 0.96 V */
V_AO_0P970 = 11, /*!< 0.97 V */
V_AO_0P980 = 12, /*!< 0.98 V */
V_AO_0P990 = 13, /*!< 0.99 V */
V_AO_1P000 = 14, /*!< 1 V */
V_AO_1P010 = 15, /*!< 1.01 V */
V_AO_1P020 = 16, /*!< 1.02 V */
V_AO_1P030 = 17, /*!< 1.03 V */
V_AO_1P040 = 18, /*!< 1.04 V */
V_AO_1P050 = 19, /*!< 1.05 V */
V_AO_1P060 = 20, /*!< 1.06 V */
V_AO_1P070 = 21, /*!< 1.07 V */
V_AO_1P080 = 22, /*!< 1.08 V */
V_AO_1P090 = 23, /*!< 1.09 V */
V_AO_1P100 = 24, /*!< 1.1 V */
V_AO_1P110 = 25, /*!< 1.11 V */
V_AO_1P120 = 26, /*!< 1.12 V */
V_AO_1P130 = 27, /*!< 1.13 V */
V_AO_1P140 = 28, /*!< 1.14 V */
V_AO_1P150 = 29, /*!< 1.15 V */
V_AO_1P160 = 30, /*!< 1.16 V */
V_AO_1P220 = 31 /*!< 1.22 V */
} v_ao_t;
/**
* @brief Deep Sleep LDO voltage settings
*/
typedef enum _v_deepsleep
{
V_DEEPSLEEP_0P900 = 0, /*!< 0.9 V */
V_DEEPSLEEP_0P925 = 1, /*!< 0.925 V */
V_DEEPSLEEP_0P950 = 2, /*!< 0.95 V */
V_DEEPSLEEP_0P975 = 3, /*!< 0.975 V */
V_DEEPSLEEP_1P000 = 4, /*!< 1.000 V */
V_DEEPSLEEP_1P025 = 5, /*!< 1.025 V */
V_DEEPSLEEP_1P050 = 6, /*!< 1.050 V */
V_DEEPSLEEP_1P075 = 7 /*!< 1.075 V */
} v_deepsleep_t;
/**
* @brief DCDC voltage settings
*/
typedef enum _v_dcdc
{
V_DCDC_0P950 = 0, /*!< 0.95 V */
V_DCDC_0P975 = 1, /*!< 0.975 V */
V_DCDC_1P000 = 2, /*!< 1 V */
V_DCDC_1P025 = 3, /*!< 1.025 V */
V_DCDC_1P050 = 4, /*!< 1.050 V */
V_DCDC_1P075 = 5, /*!< 1.075 V */
V_DCDC_1P100 = 6, /*!< 1.1 V */
V_DCDC_1P125 = 7, /*!< 1.125 V */
V_DCDC_1P150 = 8, /*!< 1.150 V */
V_DCDC_1P175 = 9, /*!< 1.175 V */
V_DCDC_1P200 = 10 /*!< 1.2 V */
} v_dcdc_t;
/**
* @brief LDO_FLASH_NV & LDO_USB voltage settings
*/
typedef enum _v_flashnv
{
V_LDOFLASHNV_1P650 = 0, /*!< 0.95 V */
V_LDOFLASHNV_1P700 = 1, /*!< 0.975 V */
V_LDOFLASHNV_1P750 = 2, /*!< 1 V */
V_LDOFLASHNV_0P800 = 3, /*!< 1.025 V */
V_LDOFLASHNV_1P850 = 4, /*!< 1.050 V */
V_LDOFLASHNV_1P900 = 5, /*!< 1.075 V */
V_LDOFLASHNV_1P950 = 6, /*!< 1.1 V */
V_LDOFLASHNV_2P000 = 7 /*!< 1.125 V */
} v_flashnv_t;
/**
* @brief Low Power Modes Wake up sources
*/
#define WAKEUP_SYS (1ULL << 0) /*!< [SLEEP, DEEP SLEEP ] */ /* WWDT0_IRQ and BOD_IRQ*/
#define WAKEUP_SDMA0 (1ULL << 1) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_GLOBALINT0 (1ULL << 2) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
#define WAKEUP_GPIO_GLOBALINT1 (1ULL << 3) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
#define WAKEUP_GPIO_INT0_0 (1ULL << 4) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_1 (1ULL << 5) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_2 (1ULL << 6) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_3 (1ULL << 7) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_UTICK (1ULL << 8) /*!< [SLEEP, ] */
#define WAKEUP_MRT (1ULL << 9) /*!< [SLEEP, ] */
#define WAKEUP_CTIMER0 (1ULL << 10) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_CTIMER1 (1ULL << 11) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_SCT (1ULL << 12) /*!< [SLEEP, ] */
#define WAKEUP_CTIMER3 (1ULL << 13) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM0 (1ULL << 14) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM1 (1ULL << 15) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM2 (1ULL << 16) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM3 (1ULL << 17) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
#define WAKEUP_FLEXCOMM4 (1ULL << 18) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM5 (1ULL << 19) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM6 (1ULL << 20) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_FLEXCOMM7 (1ULL << 21) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_ADC (1ULL << 22) /*!< [SLEEP, ] */
// reserved (1ULL << 23) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_ACMP_CAPT (1ULL << 24) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
// reserved (1ULL << 25)
// reserved (1ULL << 26)
#define WAKEUP_USB0_NEEDCLK (1ULL << 27) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_USB0 (1ULL << 28) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_RTC_LITE_ALARM_WAKEUP (1ULL << 29) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
#define WAKEUP_EZH_ARCH_B (1ULL << 30) /*!< [SLEEP, ] */
#define WAKEUP_WAKEUP_MAILBOX (1ULL << 31) /*!< [SLEEP, DEEP SLEEP, POWER DOWN ] */
#define WAKEUP_GPIO_INT0_4 (1ULL << 32) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_5 (1ULL << 33) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_6 (1ULL << 34) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_GPIO_INT0_7 (1ULL << 35) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_CTIMER2 (1ULL << 36) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_CTIMER4 (1ULL << 37) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_OS_EVENT_TIMER (1ULL << 38) /*!< [SLEEP, DEEP SLEEP, POWER DOWN, DEEP POWER DOWN] */
// reserved (1ULL << 39)
// reserved (1ULL << 40)
// reserved (1ULL << 41)
#define WAKEUP_SDIO (1ULL << 42) /*!< [SLEEP, ] */
// reserved (1ULL << 43)
// reserved (1ULL << 44)
// reserved (1ULL << 45)
// reserved (1ULL << 46)
#define WAKEUP_USB1 (1ULL << 47) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_USB1_NEEDCLK (1ULL << 48) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_SEC_HYPERVISOR_CALL (1ULL << 49) /*!< [SLEEP, ] */
#define WAKEUP_SEC_GPIO_INT0_0 (1ULL << 50) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_SEC_GPIO_INT0_1 (1ULL << 51) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_PLU (1ULL << 52) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_SEC_VIO (1ULL << 53)
#define WAKEUP_SHA (1ULL << 54) /*!< [SLEEP, ] */
#define WAKEUP_CASPER (1ULL << 55) /*!< [SLEEP, ] */
#define WAKEUP_PUFF (1ULL << 56) /*!< [SLEEP, ] */
#define WAKEUP_PQ (1ULL << 57) /*!< [SLEEP, ] */
#define WAKEUP_SDMA1 (1ULL << 58) /*!< [SLEEP, DEEP SLEEP ] */
#define WAKEUP_LSPI_HS (1ULL << 59) /*!< [SLEEP, DEEP SLEEP ] */
// reserved WAKEUP_PVTVF0_AMBER (1ULL << 60)
// reserved WAKEUP_PVTVF0_RED (1ULL << 61)
// reserved WAKEUP_PVTVF1_AMBER (1ULL << 62)
#define WAKEUP_ALLWAKEUPIOS (1ULL << 63) /*!< [ , DEEP POWER DOWN] */
/**
* @brief Sleep Postpone
*/
#define LOWPOWER_HWWAKE_FORCED (1UL << 0) /*!< Force peripheral clocking to stay on during deep-sleep mode. */
#define LOWPOWER_HWWAKE_PERIPHERALS (1UL << 1) /*!< Wake for Flexcomms. Any Flexcomm FIFO reaching the level specified by its own TXLVL will cause peripheral clocking to wake up temporarily while the related status is asserted */
#define LOWPOWER_HWWAKE_SDMA0 (1UL << 3) /*!< Wake for DMA0. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
#define LOWPOWER_HWWAKE_SDMA1 (1UL << 5) /*!< Wake for DMA1. DMA0 being busy will cause peripheral clocking to remain running until DMA completes. Used in conjonction with LOWPOWER_HWWAKE_PERIPHERALS */
#define LOWPOWER_HWWAKE_ENABLE_FRO192M (1UL << 31) /*!< Need to be set if FRO192M is disable - via PDCTRL0 - in Deep Sleep mode and any of LOWPOWER_HWWAKE_PERIPHERALS, LOWPOWER_HWWAKE_SDMA0 or LOWPOWER_HWWAKE_SDMA1 is set */
/**
* @brief Wake up I/O sources
*/
#define LOWPOWER_WAKEUPIOSRC_PIO0_INDEX 0 /*!< Pin P1( 1) */
#define LOWPOWER_WAKEUPIOSRC_PIO1_INDEX 2 /*!< Pin P0(28) */
#define LOWPOWER_WAKEUPIOSRC_PIO2_INDEX 4 /*!< Pin P1(18) */
#define LOWPOWER_WAKEUPIOSRC_PIO3_INDEX 6 /*!< Pin P1(30) */
#define LOWPOWER_WAKEUPIOSRC_DISABLE 0 /*!< Wake up is disable */
#define LOWPOWER_WAKEUPIOSRC_RISING 1 /*!< Wake up on rising edge */
#define LOWPOWER_WAKEUPIOSRC_FALLING 2 /*!< Wake up on falling edge */
#define LOWPOWER_WAKEUPIOSRC_RISING_FALLING 3 /*!< Wake up on both rising or falling edges */
/**
* @brief Wake up timers configuration in Low Power Modes
*/
#define LOWPOWER_TIMERCFG_CTRL_INDEX 0
#define LOWPOWER_TIMERCFG_CTRL_MASK (0x1UL << LOWPOWER_TIMERCFG_CTRL_INDEX)
#define LOWPOWER_TIMERCFG_TIMER_INDEX 1
#define LOWPOWER_TIMERCFG_TIMER_MASK (0x7UL << LOWPOWER_TIMERCFG_TIMER_INDEX)
#define LOWPOWER_TIMERCFG_OSC32K_INDEX 4
#define LOWPOWER_TIMERCFG_OSC32K_MASK (0x1UL << LOWPOWER_TIMERCFG_OSC32K_INDEX)
#define LOWPOWER_TIMERCFG_CTRL_DISABLE 0 /*!< Wake Timer Disable */
#define LOWPOWER_TIMERCFG_CTRL_ENABLE 1 /*!< Wake Timer Enable */
/**
* @brief Primary Wake up timers configuration in Low Power Modes
*/
#define LOWPOWER_TIMERCFG_TIMER_RTC1KHZ 0 /*!< 1 KHz Real Time Counter (RTC) used as wake up source */
#define LOWPOWER_TIMERCFG_TIMER_RTC1HZ 1 /*!< 1 Hz Real Time Counter (RTC) used as wake up source */
#define LOWPOWER_TIMERCFG_TIMER_OSTIMER 2 /*!< OS Event Timer used as wake up source */
#define LOWPOWER_TIMERCFG_OSC32K_FRO32KHZ 0 /*!< Wake up Timers uses FRO 32 KHz as clock source */
#define LOWPOWER_TIMERCFG_OSC32K_XTAL32KHZ 1 /*!< Wake up Timers uses Chrystal 32 KHz as clock source */
//! @brief Interface for lowpower functions
typedef struct LowpowerDriverInterface
{
void (*power_cycle_cpu_and_flash)(void);
void (*set_lowpower_mode)(LPC_LOWPOWER_T *p_lowpower_cfg);
} lowpower_driver_interface_t;
/* Power mode configuration API parameter */
typedef enum _power_mode_config
{
kPmu_Sleep = 0U,
kPmu_Deep_Sleep = 1U,
kPmu_PowerDown = 2U,
kPmu_Deep_PowerDown = 3U,
} power_mode_cfg_t;
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*!
* @brief API to enable PDRUNCFG bit in the Syscon. Note that enabling the bit powers down the peripheral
*
* @param en peripheral for which to enable the PDRUNCFG bit
* @return none
*/
static inline void POWER_EnablePD(pd_bit_t en)
{
/* PDRUNCFGSET */
PMC->PDRUNCFGSET0 = en;
}
/*!
* @brief API to disable PDRUNCFG bit in the Syscon. Note that disabling the bit powers up the peripheral
*
* @param en peripheral for which to disable the PDRUNCFG bit
* @return none
*/
static inline void POWER_DisablePD(pd_bit_t en)
{
/* PDRUNCFGCLR */
PMC->PDRUNCFGCLR0 = en;
}
/*!
* @brief set BOD VBAT level.
*
* @param level BOD detect level
* @param hyst BoD Hysteresis control
* @param enBodVbatReset VBAT brown out detect reset
*/
static inline void POWER_SetBodVbatLevel(power_bod_vbat_level_t level, power_bod_hyst_t hyst, bool enBodVbatReset)
{
PMC->BODVBAT = (PMC->BODVBAT & (~(PMC_BODVBAT_TRIGLVL_MASK | PMC_BODVBAT_HYST_MASK))) | PMC_BODVBAT_TRIGLVL(level) |
PMC_BODVBAT_HYST(hyst);
PMC->RESETCTRL =
(PMC->RESETCTRL & (~PMC_RESETCTRL_BODVBATRESETENABLE_MASK)) | PMC_RESETCTRL_BODVBATRESETENABLE(enBodVbatReset);
}
/*!
* @brief set BOD core level.
*
* @param level BOD detect level
* @param hyst BoD Hysteresis control
* @param enBodCoreReset core brown out detect reset
*/
static inline void POWER_SetBodCoreLevel(power_bod_core_level_t level, power_bod_hyst_t hyst, bool enBodCoreReset)
{
PMC->BODCORE = (PMC->BODCORE & (~(PMC_BODCORE_TRIGLVL_MASK | PMC_BODCORE_HYST_MASK))) | PMC_BODCORE_TRIGLVL(level) |
PMC_BODCORE_HYST(hyst);
PMC->RESETCTRL =
(PMC->RESETCTRL & (~PMC_RESETCTRL_BODCORERESETENABLE_MASK)) | PMC_RESETCTRL_BODCORERESETENABLE(enBodCoreReset);
}
/*!
* @brief API to enable deep sleep bit in the ARM Core.
*
* @param none
* @return none
*/
static inline void POWER_EnableDeepSleep(void)
{
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
}
/*!
* @brief API to disable deep sleep bit in the ARM Core.
*
* @param none
* @return none
*/
static inline void POWER_DisableDeepSleep(void)
{
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
}
/*!
* @brief API to power down flash controller.
*
* @param none
* @return none
*/
static inline void POWER_PowerDownFlash(void)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
CLOCK_DisableClock(kCLOCK_Flash);
/* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
CLOCK_DisableClock(kCLOCK_Fmc);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief API to power up flash controller.
*
* @param none
* @return none
*/
static inline void POWER_PowerUpFlash(void)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* TURN OFF clock ip_2113 (only needed for FLASH programming, will be turned on by ROM API) */
CLOCK_EnableClock(kCLOCK_Fmc);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/**
* @brief Configures and enters in low power mode
* @param p_lowpower_cfg: pointer to a structure that contains all low power mode parameters
* @return Nothing
*
* !!! IMPORTANT NOTES :
* 1 - CPU Interrupt Enable registers are updated with p_lowpower_cfg->WAKEUPINT. They are NOT restored by the
* API.
* 2 - The Non Maskable Interrupt (NMI) should be disable before calling this API (otherwise, there is a risk
* of Dead Lock).
* 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip
* reset)
*/
void POWER_EnterLowPower(LPC_LOWPOWER_T *p_lowpower_cfg);
/**
* @brief Shut off the Flash and execute the _WFI(), then power up the Flash after wake-up event
* This MUST BE EXECUTED outside the Flash:
* either from ROM or from SRAM. The rest could stay in Flash. But, for consistency, it is
* preferable to have all functions defined in this file implemented in ROM.
* @param None
* @return Nothing
*/
void POWER_CycleCpuAndFlash(void);
/**
* @brief Configures and enters in DEEP-SLEEP low power mode
* @param exclude_from_pd:
* @param sram_retention_ctrl:
* @param wakeup_interrupts:
* @param hardware_wake_ctrl:
* @return Nothing
*
* !!! IMPORTANT NOTES :
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
* 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
* 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
* 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)
reset)
*/
void POWER_EnterDeepSleep(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts,uint32_t hardware_wake_ctrl);
/**
* @brief Configures and enters in POWERDOWN low power mode
* @param exclude_from_pd:
* @param sram_retention_ctrl:
* @param wakeup_interrupts:
* @param cpu_retention_ctrl: 0 = CPU retention is disable / 1 = CPU retention is enabled, all other values are
RESERVED.
* @return Nothing
*
* !!! IMPORTANT NOTES :
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
* 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back in case of CPU retention or if POWERDOWN is not taken (for instance because an interrupt is pending).
* 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if POWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
* 3 - In case of CPU retention, it is the responsability of the user to make sure that SRAM instance containing the stack used to call this function WILL BE preserved during low power (via parameter "sram_retention_ctrl")
* 4 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)
reset)
*/
void POWER_EnterPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t cpu_retention_ctrl);
/**
* @brief Configures and enters in DEEPPOWERDOWN low power mode
* @param exclude_from_pd:
* @param sram_retention_ctrl:
* @param wakeup_interrupts:
* @param wakeup_io_ctrl:
* @return Nothing
*
* !!! IMPORTANT NOTES :
0 - CPU0 & System CLock frequency is switched to FRO12MHz and is NOT restored back by the API.
* 1 - CPU0 Interrupt Enable registers (NVIC->ISER) are modified by this function. They are restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
* 2 - The Non Maskable Interrupt (NMI) is disabled and its configuration before calling this function will be restored back if DEEPPOWERDOWN is not taken (for instance because an RTC or OSTIMER interrupt is pending).
* 3 - The HARD FAULT handler should execute from SRAM. (The Hard fault handler should initiate a full chip reset)
*/
void POWER_EnterDeepPowerDown(uint32_t exclude_from_pd, uint32_t sram_retention_ctrl, uint64_t wakeup_interrupts, uint32_t wakeup_io_ctrl);
/**
* @brief Configures and enters in SLEEP low power mode
* @param :
* @return Nothing
*/
void POWER_EnterSleep(void);
/*!
* @brief Power Library API to choose normal regulation and set the voltage for the desired operating frequency.
*
* @param system_freq_hz - The desired frequency (in Hertz) at which the part would like to operate,
* note that the voltage and flash wait states should be set before changing frequency
* @return none
*/
void POWER_SetVoltageForFreq(uint32_t system_freq_hz);
/*!
* @brief Power Library API to return the library version.
*
* @param none
* @return version number of the power library
*/
uint32_t POWER_GetLibVersion(void);
/**
* @brief Sets board-specific trim values for 16MHz XTAL
* @param pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @param pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @param pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @return none
* @note Following default Values can be used:
* pi32_32MfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
* pi32_32MfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 20
* pi32_32MfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
*/
extern void POWER_Xtal16mhzCapabankTrim(int32_t pi32_16MfXtalIecLoadpF_x100, int32_t pi32_16MfXtalPPcbParCappF_x100, int32_t pi32_16MfXtalNPcbParCappF_x100);
/**
* @brief Sets board-specific trim values for 32kHz XTAL
* @param pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @param pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @param pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100. For example, 6pF becomes 600, 1.2pF becomes 120
* @return none
* @note Following default Values can be used:
* pi32_32kfXtalIecLoadpF_x100 Load capacitance, pF x 100 : 600
* pi32_32kfXtalPPcbParCappF_x100 PCB +ve parasitic capacitance, pF x 100 : 40
* pi32_32kfXtalNPcbParCappF_x100 PCB -ve parasitic capacitance, pF x 100 : 40
*/
extern void POWER_Xtal32khzCapabankTrim(int32_t pi32_32kfXtalIecLoadpF_x100, int32_t pi32_32kfXtalPPcbParCappF_x100, int32_t pi32_32kfXtalNPcbParCappF_x100);
/**
* @brief Enables and sets LDO for 16MHz XTAL
* @param none
* @return none
*/
extern void POWER_SetXtal16mhzLdo(void);
/**
* @brief Set up 16-MHz XTAL Trimmings
* @param amp Amplitude
* @param gm Transconductance
* @return none
*/
extern void POWER_SetXtal16mhzTrim(uint32_t amp, uint32_t gm);
#ifdef __cplusplus
}
#endif
/**
* @}
*/
#endif /* _FSL_POWER_H_ */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_common.h"
#include "fsl_reset.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.reset"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
/*!
* brief Assert reset to peripheral.
*
* Asserts reset signal to specified peripheral module.
*
* param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_SetPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
/* reset register is in SYSCON */
/* set bit */
SYSCON->PRESETCTRLSET[regIndex] = bitMask;
/* wait until it reads 0b1 */
while (0u == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
{
}
}
/*!
* brief Clear reset to peripheral.
*
* Clears reset signal to specified peripheral module, allows it to operate.
*
* param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral)
{
const uint32_t regIndex = ((uint32_t)peripheral & 0xFFFF0000u) >> 16;
const uint32_t bitPos = ((uint32_t)peripheral & 0x0000FFFFu);
const uint32_t bitMask = 1u << bitPos;
assert(bitPos < 32u);
/* reset register is in SYSCON */
/* clear bit */
SYSCON->PRESETCTRLCLR[regIndex] = bitMask;
/* wait until it reads 0b0 */
while (bitMask == (SYSCON->PRESETCTRLX[regIndex] & bitMask))
{
}
}
/*!
* brief Reset peripheral module.
*
* Reset peripheral module.
*
* param peripheral Peripheral to reset. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_PeripheralReset(reset_ip_name_t peripheral)
{
RESET_SetPeripheralReset(peripheral);
RESET_ClearPeripheralReset(peripheral);
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT || FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016, NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_RESET_H_
#define _FSL_RESET_H_
#include <assert.h>
#include <stdbool.h>
#include <stdint.h>
#include <string.h>
#include "fsl_device_registers.h"
/*!
* @addtogroup ksdk_common
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief reset driver version 2.0.0. */
#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*!
* @brief Enumeration for peripheral reset control bits
*
* Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
*/
typedef enum _SYSCON_RSTn
{
kROM_RST_SHIFT_RSTn = 0 | 1U, /**< ROM reset control */
kSRAM1_RST_SHIFT_RSTn = 0 | 3U, /**< SRAM1 reset control */
kSRAM2_RST_SHIFT_RSTn = 0 | 4U, /**< SRAM2 reset control */
kSRAM3_RST_SHIFT_RSTn = 0 | 5U, /**< SRAM3 reset control */
kSRAM4_RST_SHIFT_RSTn = 0 | 6U, /**< SRAM4 reset control */
kFLASH_RST_SHIFT_RSTn = 0 | 7U, /**< Flash controller reset control */
kFMC_RST_SHIFT_RSTn = 0 | 8U, /**< Flash accelerator reset control */
kSPIFI_RST_SHIFT_RSTn = 0 | 10U, /**< SPIFI reset control */
kMUX0_RST_SHIFT_RSTn = 0 | 11U, /**< Input mux0 reset control */
kIOCON_RST_SHIFT_RSTn = 0 | 13U, /**< IOCON reset control */
kGPIO0_RST_SHIFT_RSTn = 0 | 14U, /**< GPIO0 reset control */
kGPIO1_RST_SHIFT_RSTn = 0 | 15U, /**< GPIO1 reset control */
kGPIO2_RST_SHIFT_RSTn = 0 | 16U, /**< GPIO2 reset control */
kGPIO3_RST_SHIFT_RSTn = 0 | 17U, /**< GPIO3 reset control */
kPINT_RST_SHIFT_RSTn = 0 | 18U, /**< Pin interrupt (PINT) reset control */
kGINT_RST_SHIFT_RSTn = 0 | 19U, /**< Grouped interrupt (PINT) reset control. */
kDMA0_RST_SHIFT_RSTn = 0 | 20U, /**< DMA reset control */
kCRC_RST_SHIFT_RSTn = 0 | 21U, /**< CRC reset control */
kWWDT_RST_SHIFT_RSTn = 0 | 22U, /**< Watchdog timer reset control */
kRTC_RST_SHIFT_RSTn = 0 | 23U, /**< RTC reset control */
kMAILBOX_RST_SHIFT_RSTn = 0 | 26U, /**< Mailbox reset control */
kADC0_RST_SHIFT_RSTn = 0 | 27U, /**< ADC0 reset control */
kMRT_RST_SHIFT_RSTn = 65536 | 0U, /**< Multi-rate timer (MRT) reset control */
kOSTIMER0_RST_SHIFT_RSTn = 65536 | 1U, /**< OSTimer0 reset control */
kSCT0_RST_SHIFT_RSTn = 65536 | 2U, /**< SCTimer/PWM 0 (SCT0) reset control */
kSCTIPU_RST_SHIFT_RSTn = 65536 | 6U, /**< SCTIPU reset control */
kUTICK_RST_SHIFT_RSTn = 65536 | 10U, /**< Micro-tick timer reset control */
kFC0_RST_SHIFT_RSTn = 65536 | 11U, /**< Flexcomm Interface 0 reset control */
kFC1_RST_SHIFT_RSTn = 65536 | 12U, /**< Flexcomm Interface 1 reset control */
kFC2_RST_SHIFT_RSTn = 65536 | 13U, /**< Flexcomm Interface 2 reset control */
kFC3_RST_SHIFT_RSTn = 65536 | 14U, /**< Flexcomm Interface 3 reset control */
kFC4_RST_SHIFT_RSTn = 65536 | 15U, /**< Flexcomm Interface 4 reset control */
kFC5_RST_SHIFT_RSTn = 65536 | 16U, /**< Flexcomm Interface 5 reset control */
kFC6_RST_SHIFT_RSTn = 65536 | 17U, /**< Flexcomm Interface 6 reset control */
kFC7_RST_SHIFT_RSTn = 65536 | 18U, /**< Flexcomm Interface 7 reset control */
kCTIMER2_RST_SHIFT_RSTn = 65536 | 22U, /**< CTimer 2 reset control */
kUSB0D_RST_SHIFT_RSTn = 65536 | 25U, /**< USB0 Device reset control */
kCTIMER0_RST_SHIFT_RSTn = 65536 | 26U, /**< CTimer 0 reset control */
kCTIMER1_RST_SHIFT_RSTn = 65536 | 27U, /**< CTimer 1 reset control */
kPVT_RST_SHIFT_RSTn = 65536 | 28U, /**< PVT reset control */
kEZHA_RST_SHIFT_RSTn = 65536 | 30U, /**< EZHA reset control */
kEZHB_RST_SHIFT_RSTn = 65536 | 31U, /**< EZHB reset control */
kDMA1_RST_SHIFT_RSTn = 131072 | 1U, /**< DMA1 reset control */
kCMP_RST_SHIFT_RSTn = 131072 | 2U, /**< CMP reset control */
kSDIO_RST_SHIFT_RSTn = 131072 | 3U, /**< SDIO reset control */
kUSB1H_RST_SHIFT_RSTn = 131072 | 4U, /**< USBHS Host reset control */
kUSB1D_RST_SHIFT_RSTn = 131072 | 5U, /**< USBHS Device reset control */
kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U, /**< USB RAM reset control */
kUSB1_RST_SHIFT_RSTn = 131072 | 7U, /**< USBHS reset control */
kFREQME_RST_SHIFT_RSTn = 131072 | 8U, /**< FREQME reset control */
kGPIO4_RST_SHIFT_RSTn = 131072 | 9U, /**< GPIO4 reset control */
kGPIO5_RST_SHIFT_RSTn = 131072 | 10U, /**< GPIO5 reset control */
kAES_RST_SHIFT_RSTn = 131072 | 11U, /**< AES reset control */
kOTP_RST_SHIFT_RSTn = 131072 | 12U, /**< OTP reset control */
kRNG_RST_SHIFT_RSTn = 131072 | 13U, /**< RNG reset control */
kMUX1_RST_SHIFT_RSTn = 131072 | 14U, /**< Input mux1 reset control */
kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U, /**< USB0HMR reset control */
kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U, /**< USB0HSL reset control */
kHASHCRYPT_RST_SHIFT_RSTn = 131072 | 18U, /**< HASHCRYPT reset control */
kPOWERQUAD_RST_SHIFT_RSTn = 131072 | 19U, /**< PowerQuad reset control */
kPLULUT_RST_SHIFT_RSTn = 131072 | 20U, /**< PLU LUT reset control */
kCTIMER3_RST_SHIFT_RSTn = 131072 | 21U, /**< CTimer 3 reset control */
kCTIMER4_RST_SHIFT_RSTn = 131072 | 22U, /**< CTimer 4 reset control */
kPUF_RST_SHIFT_RSTn = 131072 | 23U, /**< PUF reset control */
kCASPER_RST_SHIFT_RSTn = 131072 | 24U, /**< CASPER reset control */
kCAP0_RST_SHIFT_RSTn = 131072 | 25U, /**< CASPER reset control */
kOSTIMER1_RST_SHIFT_RSTn = 131072 | 26U, /**< OSTIMER1 reset control */
kANALOGCTL_RST_SHIFT_RSTn = 131072 | 27U, /**< ANALOG_CTL reset control */
kHSLSPI_RST_SHIFT_RSTn = 131072 | 28U, /**< HS LSPI reset control */
kGPIOSEC_RST_SHIFT_RSTn = 131072 | 29U, /**< GPIO Secure reset control */
kGPIOSECINT_RST_SHIFT_RSTn = 131072 | 30U, /**< GPIO Secure int reset control */
} SYSCON_RSTn_t;
/** Array initializers with peripheral reset bits **/
#define ADC_RSTS \
{ \
kADC0_RST_SHIFT_RSTn \
} /* Reset bits for ADC peripheral */
#define AES_RSTS \
{ \
kAES_RST_SHIFT_RSTn \
} /* Reset bits for AES peripheral */
#define CRC_RSTS \
{ \
kCRC_RST_SHIFT_RSTn \
} /* Reset bits for CRC peripheral */
#define CTIMER_RSTS \
{ \
kCTIMER0_RST_SHIFT_RSTn, kCTIMER1_RST_SHIFT_RSTn, kCTIMER2_RST_SHIFT_RSTn, kCTIMER3_RST_SHIFT_RSTn, \
kCTIMER4_RST_SHIFT_RSTn \
} /* Reset bits for CTIMER peripheral */
#define DMA_RSTS_N \
{ \
kDMA0_RST_SHIFT_RSTn, kDMA1_RST_SHIFT_RSTn \
} /* Reset bits for DMA peripheral */
#define FLEXCOMM_RSTS \
{ \
kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kHSLSPI_RST_SHIFT_RSTn \
} /* Reset bits for FLEXCOMM peripheral */
#define GINT_RSTS \
{ \
kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
} /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
#define GPIO_RSTS_N \
{ \
kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn, \
kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn \
} /* Reset bits for GPIO peripheral */
#define INPUTMUX_RSTS \
{ \
kMUX0_RST_SHIFT_RSTn, kMUX1_RST_SHIFT_RSTn \
} /* Reset bits for INPUTMUX peripheral */
#define IOCON_RSTS \
{ \
kIOCON_RST_SHIFT_RSTn \
} /* Reset bits for IOCON peripheral */
#define FLASH_RSTS \
{ \
kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
} /* Reset bits for Flash peripheral */
#define MRT_RSTS \
{ \
kMRT_RST_SHIFT_RSTn \
} /* Reset bits for MRT peripheral */
#define OTP_RSTS \
{ \
kOTP_RST_SHIFT_RSTn \
} /* Reset bits for OTP peripheral */
#define PINT_RSTS \
{ \
kPINT_RST_SHIFT_RSTn \
} /* Reset bits for PINT peripheral */
#define RNG_RSTS \
{ \
kRNG_RST_SHIFT_RSTn \
} /* Reset bits for RNG peripheral */
#define SDIO_RST \
{ \
kSDIO_RST_SHIFT_RSTn \
} /* Reset bits for SDIO peripheral */
#define SCT_RSTS \
{ \
kSCT0_RST_SHIFT_RSTn \
} /* Reset bits for SCT peripheral */
#define SPIFI_RSTS \
{ \
kSPIFI_RST_SHIFT_RSTn \
} /* Reset bits for SPIFI peripheral */
#define USB0D_RST \
{ \
kUSB0D_RST_SHIFT_RSTn \
} /* Reset bits for USB0D peripheral */
#define USB0HMR_RST \
{ \
kUSB0HMR_RST_SHIFT_RSTn \
} /* Reset bits for USB0HMR peripheral */
#define USB0HSL_RST \
{ \
kUSB0HSL_RST_SHIFT_RSTn \
} /* Reset bits for USB0HSL peripheral */
#define USB1H_RST \
{ \
kUSB1H_RST_SHIFT_RSTn \
} /* Reset bits for USB1H peripheral */
#define USB1D_RST \
{ \
kUSB1D_RST_SHIFT_RSTn \
} /* Reset bits for USB1D peripheral */
#define USB1RAM_RST \
{ \
kUSB1RAM_RST_SHIFT_RSTn \
} /* Reset bits for USB1RAM peripheral */
#define UTICK_RSTS \
{ \
kUTICK_RST_SHIFT_RSTn \
} /* Reset bits for UTICK peripheral */
#define WWDT_RSTS \
{ \
kWWDT_RST_SHIFT_RSTn \
} /* Reset bits for WWDT peripheral */
#define CAPT_RSTS_N \
{ \
kCAP0_RST_SHIFT_RSTn \
} /* Reset bits for CAPT peripheral */
#define PLU_RSTS_N \
{ \
kPLULUT_RST_SHIFT_RSTn \
} /* Reset bits for PLU peripheral */
#define OSTIMER_RSTS \
{ \
kOSTIMER0_RST_SHIFT_RSTn \
} /* Reset bits for OSTIMER peripheral */
typedef SYSCON_RSTn_t reset_ip_name_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Assert reset to peripheral.
*
* Asserts reset signal to specified peripheral module.
*
* @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
/*!
* @brief Clear reset to peripheral.
*
* Clears reset signal to specified peripheral module, allows it to operate.
*
* @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
/*!
* @brief Reset peripheral module.
*
* Reset peripheral module.
*
* @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
* and reset bit position in the reset register.
*/
void RESET_PeripheralReset(reset_ip_name_t peripheral);
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_RESET_H_ */

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/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181219
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
/*!
* @file LPC55S69_cm33_core0
* @version 1.0
* @date 2018-08-22
* @brief Device specific configuration file for LPC55S69_cm33_core0
* (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "fsl_device_registers.h"
/* PLL0 SSCG control1 */
#define PLL_SSCG_MD_FRACT_P 0U
#define PLL_SSCG_MD_INT_P 25U
#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)
#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)
/* Get predivider (N) from PLL0 NDEC setting */
static uint32_t findPll0PreDiv(void)
{
uint32_t preDiv = 1;
/* Direct input is not used? */
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
{
preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
if (preDiv == 0)
{
preDiv = 1;
}
}
return preDiv;
}
/* Get postdivider (P) from PLL0 PDEC setting */
static uint32_t findPll0PostDiv(void)
{
uint32_t postDiv = 1;
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
{
if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
{
postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
}
else
{
postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
}
if (postDiv == 0)
{
postDiv = 2;
}
}
return postDiv;
}
/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
static float findPll0MMult(void)
{
float mMult = 1;
float mMult_fract;
uint32_t mMult_int;
if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
{
mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
}
else
{
mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));
mMult = (float)mMult_int + mMult_fract;
}
if (mMult == 0)
{
mMult = 1;
}
return mMult;
}
/* Get predivider (N) from PLL1 NDEC setting */
static uint32_t findPll1PreDiv(void)
{
uint32_t preDiv = 1;
/* Direct input is not used? */
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
{
preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
if (preDiv == 0)
{
preDiv = 1;
}
}
return preDiv;
}
/* Get postdivider (P) from PLL1 PDEC setting */
static uint32_t findPll1PostDiv(void)
{
uint32_t postDiv = 1;
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
{
if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
{
postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
}
else
{
postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
}
if (postDiv == 0)
{
postDiv = 2;
}
}
return postDiv;
}
/* Get multiplier (M) from PLL1 MDEC settings */
static uint32_t findPll1MMult(void)
{
uint32_t mMult = 1;
mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
if (mMult == 0)
{
mMult = 1;
}
return mMult;
}
/* Get FRO 12M Clk */
/*! brief Return Frequency of FRO 12MHz
* return Frequency of FRO 12MHz
*/
static uint32_t CLOCK_GetFro12MFreq(void)
{
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
0 :
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
}
/* Get FRO 1M Clk */
/*! brief Return Frequency of FRO 1MHz
* return Frequency of FRO 1MHz
*/
static uint32_t CLOCK_GetFro1MFreq(void)
{
return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
}
/* Get EXT OSC Clk */
/*! brief Return Frequency of External Clock
* return Frequency of External Clock. If no external clock is used returns 0.
*/
static uint32_t CLOCK_GetExtClkFreq(void)
{
return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
}
/* Get HF FRO Clk */
/*! brief Return Frequency of High-Freq output of FRO
* return Frequency of High-Freq output of FRO
*/
static uint32_t CLOCK_GetFroHfFreq(void)
{
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
0 :
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
}
/* Get RTC OSC Clk */
/*! brief Return Frequency of 32kHz osc
* return Frequency of 32kHz osc
*/
static uint32_t CLOCK_GetOsc32KFreq(void)
{
return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?
CLK_RTC_32K_CLK :
((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?
CLK_RTC_32K_CLK :
0U;
}
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInit (void) {
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */
SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
#if defined(__MCUXPRESSO)
extern void(*const g_pfnVectors[]) (void);
SCB->VTOR = (uint32_t) &g_pfnVectors;
#else
extern void *__Vectors;
SCB->VTOR = (uint32_t) &__Vectors;
#endif
SYSCON->TRACECLKDIV = 0;
/* Optionally enable RAM banks that may be off by default at reset */
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK
| SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
#endif
SystemInitHook();
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t clkRate = 0;
uint32_t prediv, postdiv;
float workRate;
uint64_t workRate1;
switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
{
case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
default: /* = 0x03 = FRO 96 MHz (fro_hf) */
clkRate = CLOCK_GetFroHfFreq();
break;
}
break;
case 0x01: /* PLL0 clock (pll0_clk)*/
switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
{
prediv = findPll0PreDiv();
postdiv = findPll0PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
workRate = (float)clkRate * (float)findPll0MMult();
clkRate = (uint32_t)(workRate / ((float)postdiv));
}
break;
case 0x02: /* PLL1 clock (pll1_clk)*/
switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
{
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
prediv = findPll1PreDiv();
postdiv = findPll1PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
clkRate = workRate1 / ((uint64_t)postdiv);
}
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

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/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core0
** LPC55S69JET98_cm33_core0
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181219
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
/*!
* @file LPC55S69_cm33_core0
* @version 1.0
* @date 2018-08-22
* @brief Device specific configuration file for LPC55S69_cm33_core0 (header
* file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_LPC55S69_cm33_core0_H_
#define _SYSTEM_LPC55S69_cm33_core0_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_LPC55S69_cm33_core0_H_ */

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/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core1
** LPC55S69JET98_cm33_core1
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181219
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
/*!
* @file LPC55S69_cm33_core1
* @version 1.0
* @date 2018-08-22
* @brief Device specific configuration file for LPC55S69_cm33_core1
* (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h>
#include "fsl_device_registers.h"
/* PLL0 SSCG control1 */
#define PLL_SSCG_MD_FRACT_P 0U
#define PLL_SSCG_MD_INT_P 25U
#define PLL_SSCG_MD_FRACT_M (0x1FFFFFFUL << PLL_SSCG_MD_FRACT_P)
#define PLL_SSCG_MD_INT_M ((uint64_t)0xFFUL << PLL_SSCG_MD_INT_P)
/* Get predivider (N) from PLL0 NDEC setting */
static uint32_t findPll0PreDiv(void)
{
uint32_t preDiv = 1;
/* Direct input is not used? */
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPREDIV_MASK) == 0)
{
preDiv = SYSCON->PLL0NDEC & SYSCON_PLL0NDEC_NDIV_MASK;
if (preDiv == 0)
{
preDiv = 1;
}
}
return preDiv;
}
/* Get postdivider (P) from PLL0 PDEC setting */
static uint32_t findPll0PostDiv(void)
{
uint32_t postDiv = 1;
if ((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV_MASK) == 0)
{
if (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPOSTDIV2_MASK)
{
postDiv = SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK;
}
else
{
postDiv = 2 * (SYSCON->PLL0PDEC & SYSCON_PLL0PDEC_PDIV_MASK);
}
if (postDiv == 0)
{
postDiv = 2;
}
}
return postDiv;
}
/* Get multiplier (M) from PLL0 SSCG and SEL_EXT settings */
static float findPll0MMult(void)
{
float mMult = 1;
float mMult_fract;
uint32_t mMult_int;
if (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_SEL_EXT_MASK)
{
mMult = (SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MDIV_EXT_MASK) >> SYSCON_PLL0SSCG1_MDIV_EXT_SHIFT;
}
else
{
mMult_int = ((SYSCON->PLL0SSCG1 & SYSCON_PLL0SSCG1_MD_MBS_MASK) << 7U) | ((SYSCON->PLL0SSCG0) >> PLL_SSCG_MD_INT_P);
mMult_fract = ((float)((SYSCON->PLL0SSCG0) & PLL_SSCG_MD_FRACT_M)/(1 << PLL_SSCG_MD_INT_P));
mMult = (float)mMult_int + mMult_fract;
}
if (mMult == 0)
{
mMult = 1;
}
return mMult;
}
/* Get predivider (N) from PLL1 NDEC setting */
static uint32_t findPll1PreDiv(void)
{
uint32_t preDiv = 1;
/* Direct input is not used? */
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPREDIV_MASK) == 0)
{
preDiv = SYSCON->PLL1NDEC & SYSCON_PLL1NDEC_NDIV_MASK;
if (preDiv == 0)
{
preDiv = 1;
}
}
return preDiv;
}
/* Get postdivider (P) from PLL1 PDEC setting */
static uint32_t findPll1PostDiv(void)
{
uint32_t postDiv = 1;
if ((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV_MASK) == 0)
{
if (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPOSTDIV2_MASK)
{
postDiv = SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK;
}
else
{
postDiv = 2 * (SYSCON->PLL1PDEC & SYSCON_PLL1PDEC_PDIV_MASK);
}
if (postDiv == 0)
{
postDiv = 2;
}
}
return postDiv;
}
/* Get multiplier (M) from PLL1 MDEC settings */
static uint32_t findPll1MMult(void)
{
uint32_t mMult = 1;
mMult = SYSCON->PLL1MDEC & SYSCON_PLL1MDEC_MDIV_MASK;
if (mMult == 0)
{
mMult = 1;
}
return mMult;
}
/* Get FRO 12M Clk */
/*! brief Return Frequency of FRO 12MHz
* return Frequency of FRO 12MHz
*/
static uint32_t CLOCK_GetFro12MFreq(void)
{
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
0 :
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK) ? 12000000U : 0U;
}
/* Get FRO 1M Clk */
/*! brief Return Frequency of FRO 1MHz
* return Frequency of FRO 1MHz
*/
static uint32_t CLOCK_GetFro1MFreq(void)
{
return (SYSCON->CLOCK_CTRL & SYSCON_CLOCK_CTRL_FRO1MHZ_CLK_ENA_MASK) ? 1000000U : 0U;
}
/* Get EXT OSC Clk */
/*! brief Return Frequency of External Clock
* return Frequency of External Clock. If no external clock is used returns 0.
*/
static uint32_t CLOCK_GetExtClkFreq(void)
{
return (ANACTRL->XO32M_CTRL & ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK) ? CLK_CLK_IN : 0U;
}
/* Get HF FRO Clk */
/*! brief Return Frequency of High-Freq output of FRO
* return Frequency of High-Freq output of FRO
*/
static uint32_t CLOCK_GetFroHfFreq(void)
{
return (PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO192M_MASK) ?
0 :
(ANACTRL->FRO192M_CTRL & ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK) ? 96000000U : 0U;
}
/* Get RTC OSC Clk */
/*! brief Return Frequency of 32kHz osc
* return Frequency of 32kHz osc
*/
static uint32_t CLOCK_GetOsc32KFreq(void)
{
return ((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_FRO32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(0))) ?
CLK_RTC_32K_CLK :
((~(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_XTAL32K_MASK)) && (PMC->RTCOSC32K & PMC_RTCOSC32K_SEL(1))) ?
CLK_RTC_32K_CLK :
0U;
}
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) {
SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2)); /* set CP0, CP1 Full Access (enable PowerQuad) */
SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
#if defined(__MCUXPRESSO)
extern void(*const g_pfnVectors[]) (void);
SCB->VTOR = (uint32_t) &g_pfnVectors;
#else
extern void *__Vectors;
SCB->VTOR = (uint32_t) &__Vectors;
#endif
SYSCON->TRACECLKDIV = 0;
/* Optionally enable RAM banks that may be off by default at reset */
#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL0_SRAM_CTRL1_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL2_MASK
| SYSCON_AHBCLKCTRL0_SRAM_CTRL3_MASK | SYSCON_AHBCLKCTRL0_SRAM_CTRL4_MASK;
#endif
SystemInitHook();
}
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) {
uint32_t clkRate = 0;
uint32_t prediv, postdiv;
float workRate;
uint64_t workRate1;
switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
{
case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
default: /* = 0x03 = FRO 96 MHz (fro_hf) */
clkRate = CLOCK_GetFroHfFreq();
break;
}
break;
case 0x01: /* PLL0 clock (pll0_clk)*/
switch (SYSCON->PLL0CLKSEL & SYSCON_PLL0CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
if (((SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL0CTRL & SYSCON_PLL0CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_MASK) == 0) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL0_SSCG_MASK) == 0))
{
prediv = findPll0PreDiv();
postdiv = findPll0PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
workRate = (float)clkRate * (float)findPll0MMult();
clkRate = (uint32_t)(workRate / ((float)postdiv));
}
break;
case 0x02: /* PLL1 clock (pll1_clk)*/
switch (SYSCON->PLL1CLKSEL & SYSCON_PLL1CLKSEL_SEL_MASK)
{
case 0x00: /* FRO 12 MHz (fro_12m) */
clkRate = CLOCK_GetFro12MFreq();
break;
case 0x01: /* CLKIN (clk_in) */
clkRate = CLOCK_GetExtClkFreq();
break;
case 0x02: /* Fro 1MHz (fro_1m) */
clkRate = CLOCK_GetFro1MFreq();
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
if (((SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_BYPASSPLL_MASK) == 0) && (SYSCON->PLL1CTRL & SYSCON_PLL1CTRL_CLKEN_MASK) && ((PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_PLL1_MASK) == 0))
{
/* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
prediv = findPll1PreDiv();
postdiv = findPll1PostDiv();
/* Adjust input clock */
clkRate = clkRate / prediv;
/* MDEC used for rate */
workRate1 = (uint64_t)clkRate * (uint64_t)findPll1MMult();
clkRate = workRate1 / ((uint64_t)postdiv);
}
break;
case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
clkRate = CLOCK_GetOsc32KFreq();
break;
default:
break;
}
SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
}
/* ----------------------------------------------------------------------------
-- SystemInitHook()
---------------------------------------------------------------------------- */
__attribute__ ((weak)) void SystemInitHook (void) {
/* Void implementation of the weak function. */
}

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/*
** ###################################################################
** Processors: LPC55S69JBD100_cm33_core1
** LPC55S69JET98_cm33_core1
**
** Compilers: GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: LPC55xx/LPC55Sxx User manual Rev.0.4 25 Sep 2018
** Version: rev. 1.0, 2018-08-22
** Build: b181219
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright 2016 Freescale Semiconductor, Inc.
** Copyright 2016-2018 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 1.0 (2018-08-22)
** Initial version based on v0.2UM
**
** ###################################################################
*/
/*!
* @file LPC55S69_cm33_core1
* @version 1.0
* @date 2018-08-22
* @brief Device specific configuration file for LPC55S69_cm33_core1 (header
* file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#ifndef _SYSTEM_LPC55S69_cm33_core1_H_
#define _SYSTEM_LPC55S69_cm33_core1_H_ /**< Symbol preventing repeated inclusion */
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
#define CLK_CLK_IN 16000000u /* Default CLK_IN pin clock */
/**
* @brief System clock frequency (core clock)
*
* The system clock frequency supplied to the SysTick timer and the processor
* core clock. This variable can be used by the user application to setup the
* SysTick timer or configure other parameters. It may also be used by debugger to
* query the frequency of the debug timer or configure the trace clock speed
* SystemCoreClock is initialized with a correct predefined value.
*/
extern uint32_t SystemCoreClock;
/**
* @brief Setup the microcontroller system.
*
* Typically this function configures the oscillator (PLL) that is part of the
* microcontroller device. For systems with variable clock speed it also updates
* the variable SystemCoreClock. SystemInit is called from startup_device file.
*/
void SystemInit (void);
/**
* @brief Updates the SystemCoreClock variable.
*
* It must be called whenever the core clock is changed during program
* execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
* the current core clock.
*/
void SystemCoreClockUpdate (void);
/**
* @brief SystemInit function hook.
*
* This weak function allows to call specific initialization code during the
* SystemInit() execution.This can be used when an application specific code needs
* to be called as close to the reset entry as possible (for example the Multicore
* Manager MCMGR_EarlyInit() function call).
* NOTE: No global r/w variables can be used in this hook function because the
* initialization of these variables happens after this function.
*/
void SystemInitHook (void);
#ifdef __cplusplus
}
#endif
#endif /* _SYSTEM_LPC55S69_cm33_core1_H_ */

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@ -6,5 +6,4 @@
zephyr_include_directories(.) zephyr_include_directories(.)
zephyr_sources(fsl_reset.c)
zephyr_sources_ifdef(CONFIG_USART_MCUX_LPC fsl_usart.c fsl_flexcomm.c) zephyr_sources_ifdef(CONFIG_USART_MCUX_LPC fsl_usart.c fsl_flexcomm.c)

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/*
* Copyright (c) 2018, NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_anactrl.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.anactrl"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for ANACTRL module.
*
* @param base ANACTRL peripheral base address
*/
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to ANACTRL bases for each instance. */
static ANACTRL_Type *const s_anactrlBases[] = ANACTRL_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to ANACTRL clocks for each instance. */
static const clock_ip_name_t s_anactrlClocks[] = ANALOGCTRL_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Get the ANACTRL instance from peripheral base address.
*
* param base ANACTRL peripheral base address.
* return ANACTRL instance.
*/
static uint32_t ANACTRL_GetInstance(ANACTRL_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_anactrlBases); instance++)
{
if (s_anactrlBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_anactrlBases));
return instance;
}
/*!
* @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Init(ANACTRL_Type *base)
{
assert(NULL != base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock for ANACTRL instance. */
CLOCK_EnableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief De-initialize ANACTRL module.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Deinit(ANACTRL_Type *base)
{
assert(NULL != base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock for ANACTRL instance. */
CLOCK_DisableClock(s_anactrlClocks[ANACTRL_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Set the on-chip high-speed Free Running Oscillator.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
*/
void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0;
/* Set FRO trim values. */
base->FRO192M_CTRL |= ANACTRL_FRO192M_CTRL_WRTRIM_MASK;
tmp32 |= ANACTRL_FRO192M_CTRL_BIAS_TRIM(config->biasTrim) | ANACTRL_FRO192M_CTRL_TEMP_TRIM(config->tempTrim) |
ANACTRL_FRO192M_CTRL_DAC_TRIM(config->dacTrim);
if (config->enable12MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_12MHZCLK_MASK;
}
if (config->enable48MhzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_48MHZCLK_MASK;
}
if (config->enable96MHzClk)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ENA_96MHZCLK_MASK;
}
if (config->enableAnalogTestBus)
{
tmp32 |= ANACTRL_FRO192M_CTRL_ATB_CTRL_MASK;
}
base->FRO192M_CTRL |= tmp32;
}
/*!
* @brief Get the default configuration of FRO192M.
* The default values are:
* code
* config->biasTrim = 0x1AU;
* config->tempTrim = 0x20U;
* config->enable12MHzClk = true;
* config->enable48MhzClk = true;
* config->dacTrim = 0x80U;
* config->enableAnalogTestBus = false;
* config->enable96MHzClk = false;
* encode
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
*/
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->biasTrim = 0x1AU;
config->tempTrim = 0x20U;
config->enable12MHzClk = true;
config->enable48MhzClk = true;
config->dacTrim = 0x80U;
config->enableAnalogTestBus = false;
config->enable96MHzClk = false;
}
/*!
* @brief Set the 32 MHz Crystal oscillator.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
*/
void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
/* Set XO32M CTRL. */
if (config->enableACBufferBypass)
{
tmp32 |= ANACTRL_XO32M_CTRL_ACBUF_PASS_ENABLE_MASK;
}
if (config->enablePllUsbOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_PLL_USB_OUT_MASK;
}
if (config->enableSysCLkOutput)
{
tmp32 |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK;
}
base->XO32M_CTRL = tmp32;
/* Set LDO XO32M. */
tmp32 = ANACTRL_LDO_XO32M_HIGHZ(config->LDOOutputMode) | ANACTRL_LDO_XO32M_VOUT(config->LDOOutputLevel) |
ANACTRL_LDO_XO32M_IBIAS(config->bias) | ANACTRL_LDO_XO32M_STABMODE(config->stability);
if (config->enableLDOBypass)
{
tmp32 |= ANACTRL_LDO_XO32M_BYPASS_MASK;
}
base->LDO_XO32M = tmp32;
}
/*!
* @brief Get the default configuration of XO32M.
* The default values are:
* code
* config->enableACBufferBypass = false;
* config->enablePllUsbOutput = false;
* config->enableSysCLkOutput = false;
* config->enableLDOBypass = false;
* config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
* config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
* config->bias = 2U;
* config->stability = 3U;
* encode
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
*/
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->enableACBufferBypass = false;
config->enablePllUsbOutput = false;
config->enableSysCLkOutput = false;
config->enableLDOBypass = false;
config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
config->bias = 2U;
config->stability = 3U;
}
/*!
* @brief Set the ring oscillators.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config)
{
assert(NULL != config);
uint32_t tmp32 = 0U;
/* Configure the first ring oscillator. */
tmp32 = ANACTRL_RINGO0_CTRL_SL(config->ringOscSel) | ANACTRL_RINGO0_CTRL_FS(config->ringOscFreqOutputDiv) |
ANACTRL_RINGO0_CTRL_SWN_SWP(config->pnRingOscMode) | ANACTRL_RINGO0_CTRL_E_ND0_MASK |
ANACTRL_RINGO0_CTRL_E_ND1_MASK | ANACTRL_RINGO0_CTRL_E_NR0_MASK | ANACTRL_RINGO0_CTRL_E_NR1_MASK |
ANACTRL_RINGO0_CTRL_E_IV0_MASK | ANACTRL_RINGO0_CTRL_E_IV1_MASK | ANACTRL_RINGO0_CTRL_E_PN0_MASK |
ANACTRL_RINGO0_CTRL_E_PN1_MASK | ANACTRL_RINGO0_CTRL_DIV_UPDATE_REQ_MASK |
ANACTRL_RINGO0_CTRL_DIVISOR(config->ringOscOutClkDiv);
base->RINGO0_CTRL = tmp32;
/* Configure the second and third ring oscillator. */
tmp32 = ANACTRL_RINGO1_CTRL_S(config->ringOscSel) | ANACTRL_RINGO1_CTRL_FS(config->ringOscFreqOutputDiv) |
ANACTRL_RINGO1_CTRL_E_R24_MASK | ANACTRL_RINGO1_CTRL_E_R35_MASK | ANACTRL_RINGO1_CTRL_E_M2_MASK |
ANACTRL_RINGO1_CTRL_E_M3_MASK | ANACTRL_RINGO1_CTRL_E_M4_MASK | ANACTRL_RINGO1_CTRL_E_M5_MASK |
ANACTRL_RINGO1_CTRL_DIV_UPDATE_REQ_MASK | ANACTRL_RINGO1_CTRL_DIVISOR(config->ringOscOutClkDiv);
base->RINGO1_CTRL = tmp32;
base->RINGO2_CTRL = tmp32;
/* Ensure the Riongo module is enabled. */
base->RINGO0_CTRL &= ~ANACTRL_RINGO0_CTRL_PD_MASK;
base->RINGO1_CTRL &= ~ANACTRL_RINGO1_CTRL_PD_MASK;
base->RINGO2_CTRL &= ~ANACTRL_RINGO2_CTRL_PD_MASK;
}
/*!
* @brief Get the default configuration of ring oscillators.
* The default values are:
* code
* config->ringOscSel = kANACTRL_ShortRingOsc;
* config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
* config->pnRingOscMode = kANACTRL_NormalMode;
* config->ringOscOutClkDiv = 0U;
* encode
* @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config)
{
assert(NULL != config);
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->ringOscSel = kANACTRL_ShortRingOsc;
config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
config->pnRingOscMode = kANACTRL_NormalMode;
config->ringOscOutClkDiv = 0U;
}
/*!
* @brief Measure Frequency
*
* This function measures target frequency according to a accurate reference frequency.The formula is:
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
*
* @param base ANACTRL peripheral base address.
* @scale Define the power of 2 count that ref counter counts to during measurement.
* @refClkFreq frequency of the reference clock.
* @return frequency of the target clock.
*
* @Note the minimum count (scale) is 2.
*/
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq)
{
assert(scale >= 2U);
uint32_t targetClkFreq = 0U;
uint32_t capval = 0U;
/* Init a measurement cycle. */
base->FREQ_ME_CTRL = ANACTRL_FREQ_ME_CTRL_PROG_MASK + ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE(scale);
while (ANACTRL_FREQ_ME_CTRL_PROG_MASK == (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_PROG_MASK))
{
}
/* Calculate the target clock frequency. */
capval = (base->FREQ_ME_CTRL & ANACTRL_FREQ_ME_CTRL_CAPVAL_SCALE_MASK);
targetClkFreq = (capval * refClkFreq) / ((1 << scale) - 1);
return targetClkFreq;
}

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/*
* Copyright (c) 2018, NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_ANACTRL_H__
#define __FSL_ANACTRL_H__
#include "fsl_common.h"
/*!
* @addtogroup anactrl
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @brief ANACTRL driver version. */
#define FSL_ANACTRL_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */`
/*!
* @brief ANACTRL interrupt flags
*/
enum _anactrl_interrupt_flags
{
kANACTRL_BodVbatFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_STATUS_MASK, /*!< BOD VBAT Interrupt status before Interrupt Enable. */
kANACTRL_BodVbatInterruptFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_INT_STATUS_MASK, /*!< BOD VBAT Interrupt status after Interrupt Enable. */
kANACTRL_BodVbatPowerFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODVBAT_VAL_MASK, /*!< Current value of BOD VBAT power status output. */
kANACTRL_BodCoreFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_STATUS_MASK, /*!< BOD CORE Interrupt status before Interrupt Enable. */
kANACTRL_BodCoreInterruptFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_INT_STATUS_MASK, /*!< BOD CORE Interrupt status after Interrupt Enable. */
kANACTRL_BodCorePowerFlag =
ANACTRL_BOD_DCDC_INT_STATUS_BODCORE_VAL_MASK, /*!< Current value of BOD CORE power status output. */
kANACTRL_DcdcFlag =
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_STATUS_MASK, /*!< DCDC Interrupt status before Interrupt Enable. */
kANACTRL_DcdcInterruptFlag =
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_INT_STATUS_MASK, /*!< DCDC Interrupt status after Interrupt Enable. */
kANACTRL_DcdcPowerFlag =
ANACTRL_BOD_DCDC_INT_STATUS_DCDC_VAL_MASK, /*!< Current value of DCDC power status output. */
};
/*!
* @brief ANACTRL interrupt control
*/
enum _anactrl_interrupt
{
kANACTRL_BodVbatInterruptEnable =
ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_ENABLE_MASK, /*!< BOD VBAT interrupt control. */
kANACTRL_BodCoreInterruptEnable =
ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_ENABLE_MASK, /*!< BOD CORE interrupt control. */
kANACTRL_DcdcInterruptEnable = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_ENABLE_MASK, /*!< DCDC interrupt control. */
kANACTRL_BodVbatInterruptClear =
ANACTRL_BOD_DCDC_INT_CTRL_BODVBAT_INT_CLEAR_MASK, /*!< BOD VBAT interrupt clear.1: Clear the interrupt.
Self-cleared bit. */
kANACTRL_BodCoreInterruptClear =
ANACTRL_BOD_DCDC_INT_CTRL_BODCORE_INT_CLEAR_MASK, /*!< BOD CORE interrupt clear.1: Clear the interrupt.
Self-cleared bit. */
kANACTRL_DcdcInterruptClear = ANACTRL_BOD_DCDC_INT_CTRL_DCDC_INT_CLEAR_MASK, /*!< DCDC interrupt clear.1: Clear the
interrupt. Self-cleared bit. */
};
/*!
* @brief ANACTRL status flags
*/
enum _anactrl_flags
{
kANACTRL_PMUId = ANACTRL_ANALOG_CTRL_STATUS_PMU_ID_MASK, /*!< Power Management Unit (PMU) analog macro-bloc
identification number. */
kANACTRL_OSCId =
ANACTRL_ANALOG_CTRL_STATUS_OSC_ID_MASK, /*!< Oscillators analog macro-bloc identification number. */
kANACTRL_FlashPowerDownFlag = ANACTRL_ANALOG_CTRL_STATUS_FLASH_PWRDWN_MASK, /*!< Flash power-down status. */
kANACTRL_FlashInitErrorFlag =
ANACTRL_ANALOG_CTRL_STATUS_FLASH_INIT_ERROR_MASK, /*!< Flash initialization error status. */
kANACTRL_FinalTestFlag =
ANACTRL_ANALOG_CTRL_STATUS_FINAL_TEST_DONE_VECT_MASK, /*!< Indicates current status of final test. */
};
/*!
* @brief ANACTRL FRO192M and XO32M status flags
*/
enum _anactrl_osc_flags
{
kANACTRL_OutputClkValidFlag = ANACTRL_FRO192M_STATUS_CLK_VALID_MASK, /*!< Output clock valid signal. */
kANACTRL_CCOThresholdVoltageFlag =
ANACTRL_FRO192M_STATUS_ATB_VCTRL_MASK, /*!< CCO threshold voltage detector output (signal vcco_ok). */
kANACTRL_XO32MOutputReadyFlag = ANACTRL_XO32M_STATUS_XO_READY_MASK
<< 16U, /*!< Indicates XO out frequency statibilty. */
};
/*!
* @brief LDO output mode
*/
typedef enum _anactrl_ldo_output_mode
{
kANACTRL_LDOOutputHighNormalMode = 0U, /*!< Output in High normal state. */
kANACTRL_LDOOutputHighImpedanceMode = 1U, /*!< Output in High Impedance state. */
} anactrl_ldo_output_mode_t;
/*!
* @brief LDO output level
*/
typedef enum _anactrl_ldo_output_level
{
kANACTRL_LDOOutputLevel0 = 0U, /*!< Output level 0.750 V. */
kANACTRL_LDOOutputLevel1, /*!< Output level 0.775 V. */
kANACTRL_LDOOutputLevel2, /*!< Output level 0.800 V. */
kANACTRL_LDOOutputLevel3, /*!< Output level 0.825 V. */
kANACTRL_LDOOutputLevel4, /*!< Output level 0.850 V. */
kANACTRL_LDOOutputLevel5, /*!< Output level 0.875 V. */
kANACTRL_LDOOutputLevel6, /*!< Output level 0.900 V. */
kANACTRL_LDOOutputLevel7, /*!< Output level 0.925 V. */
} anactrl_ldo_output_level_t;
/*!
* @brief Select short or long ring osc
*/
typedef enum _anactrl_ring_osc_selector
{
kANACTRL_ShortRingOsc = 0U, /*!< Select short ring osc (few elements). */
kANACTRL_LongRingOsc = 1U, /*!< Select long ring osc (many elements). */
} anactrl_ring_osc_selector_t;
/*!
* @brief Ring osc frequency output divider
*/
typedef enum _anactrl_ring_osc_freq_output_divider
{
kANACTRL_HighFreqOutput = 0U, /*!< High frequency output (frequency lower than 100 MHz). */
kANACTRL_LowFreqOutput = 1U, /*!< Low frequency output (frequency lower than 10 MHz). */
} anactrl_ring_osc_freq_output_divider_t;
/*!
* @brief PN-Ring osc (P-Transistor and N-Transistor processing) control.
*/
typedef enum _anactrl_pn_ring_osc_mode
{
kANACTRL_NormalMode = 0U, /*!< Normal mode. */
kANACTRL_PMonitorPTransistorMode = 1U, /*!< P-Monitor mode. Measure with weak P transistor. */
kANACTRL_PMonitorNTransistorMode = 2U, /*!< P-Monitor mode. Measure with weak N transistor. */
kANACTRL_NotUse = 3U, /*!< Do not use. */
} anactrl_pn_ring_osc_mode_t;
/*!
* @breif Configuration for FRO192M
*
* This structure holds the configuration settings for the on-chip high-speed Free Running Oscillator. To initialize
* this structure to reasonable defaults, call the ANACTRL_GetDefaultFro192MConfig() function and pass a
* pointer to your config structure instance.
*/
typedef struct _anactrl_fro192M_config
{
uint8_t biasTrim; /*!< Set bias trimming value (course frequency trimming). */
uint8_t tempTrim; /*!< Set temperature coefficient trimming value. */
uint8_t dacTrim; /*!< Set curdac trimming value (fine frequency trimming) This trim is used to
adjust the frequency, given that the bias and temperature trim are set. */
bool enable12MHzClk; /*!< Enable 12MHz clock. */
bool enable48MhzClk; /*!< Enable 48MHz clock. */
bool enable96MHzClk; /*!< Enable 96MHz clock. */
bool enableAnalogTestBus; /*!< Enable analog test bus. */
} anactrl_fro192M_config_t;
/*!
* @breif Configuration for XO32M
*
* This structure holds the configuration settings for the 32 MHz crystal oscillator. To initialize this
* structure to reasonable defaults, call the ANACTRL_GetDefaultXo32MConfig() function and pass a
* pointer to your config structure instance.
*/
typedef struct _anactrl_xo32M_config
{
bool enableACBufferBypass; /*!< Enable XO AC buffer bypass in pll and top level. */
bool enablePllUsbOutput; /*!< Enable XO 32 MHz output to USB HS PLL. */
bool enableSysCLkOutput; /*!< Enable XO 32 MHz output to CPU system, SCT, and CLKOUT */
bool enableLDOBypass; /*!< Activate LDO bypass. */
anactrl_ldo_output_mode_t LDOOutputMode; /*!< Set LDO output mode. */
anactrl_ldo_output_level_t LDOOutputLevel; /*!< Set LDO output level. */
uint8_t bias; /*!< Adjust the biasing current. */
uint8_t stability; /*!< Stability configuration. */
} anactrl_xo32M_config_t;
/*!
* @breif Configuration for ring oscillator
*
* This structure holds the configuration settings for the three ring oscillators. To initialize this
* structure to reasonable defaults, call the ANACTRL_GetDefaultRingOscConfig() function and pass a
* pointer to your config structure instance.
*/
typedef struct _anactrl_ring_osc_config
{
anactrl_ring_osc_selector_t ringOscSel;
anactrl_ring_osc_freq_output_divider_t ringOscFreqOutputDiv;
anactrl_pn_ring_osc_mode_t pnRingOscMode;
uint8_t ringOscOutClkDiv;
} anactrl_ring_osc_config_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Enable the access to ANACTRL registers and initialize ANACTRL module.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Init(ANACTRL_Type *base);
/*!
* @brief De-initialize ANACTRL module.
*
* @param base ANACTRL peripheral base address.
*/
void ANACTRL_Deinit(ANACTRL_Type *base);
/* @} */
/*!
* @name Set oscillators
* @{
*/
/*!
* @brief Set the on-chip high-speed Free Running Oscillator.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
*/
void ANACTRL_SetFro192M(ANACTRL_Type *base, anactrl_fro192M_config_t *config);
/*!
* @brief Get the default configuration of FRO192M.
* The default values are:
* code
* config->biasTrim = 0x1AU;
* config->tempTrim = 0x20U;
* config->enable12MHzClk = true;
* config->enable48MhzClk = true;
* config->dacTrim = 0x80U;
* config->enableAnalogTestBus = false;
* config->enable96MHzClk = false;
* encode
* @param config Pointer to FRO192M configuration structure. Refer to "anactrl_fro192M_config_t" structure.
*/
void ANACTRL_GetDefaultFro192MConfig(anactrl_fro192M_config_t *config);
/*!
* @brief Set the 32 MHz Crystal oscillator.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
*/
void ANACTRL_SetXo32M(ANACTRL_Type *base, anactrl_xo32M_config_t *config);
/*!
* @brief Get the default configuration of XO32M.
* The default values are:
* code
* config->enableACBufferBypass = false;
* config->enablePllUsbOutput = false;
* config->enableSysCLkOutput = false;
* config->enableLDOBypass = false;
* config->LDOOutputMode = kANACTRL_LDOOutputHighNormalMode;
* config->LDOOutputLevel = kANACTRL_LDOOutputLevel4;
* config->bias = 2U;
* config->stability = 3U;
* encode
* @param config Pointer to XO32M configuration structure. Refer to "anactrl_xo32M_config_t" structure.
*/
void ANACTRL_GetDefaultXo32MConfig(anactrl_xo32M_config_t *config);
/*!
* @brief Set the ring oscillators.
*
* @param base ANACTRL peripheral base address.
* @param config Pointer to ring osc configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_SetRingOsc(ANACTRL_Type *base, anactrl_ring_osc_config_t *config);
/*!
* @brief Get the default configuration of ring oscillators.
* The default values are:
* code
* config->ringOscSel = kANACTRL_ShortRingOsc;
* config->ringOscFreqOutputDiv = kANACTRL_HighFreqOutput;
* config->pnRingOscMode = kANACTRL_NormalMode;
* config->ringOscOutClkDiv = 0U;
* encode
* @param config Pointer to ring oscillator configuration structure. Refer to "anactrl_ring_osc_config_t" structure.
*/
void ANACTRL_GetDefaultRingOscConfig(anactrl_ring_osc_config_t *config);
/* @} */
/*!
* @name ADC control
* @{
*/
/*!
* @brief Enable VBAT divider branch.
*
* @param base ANACTRL peripheral base address.
* @param enable switcher to the function.
*/
static inline void ANACTRL_EnableAdcVBATDivider(ANACTRL_Type *base, bool enable)
{
if (enable)
{
base->ADC_CTRL |= ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
}
else
{
base->ADC_CTRL &= ~ANACTRL_ADC_CTRL_VBATDIVENABLE_MASK;
}
}
/* @} */
/*!
* @name Measure Frequency
* @{
*/
/*!
* @brief Measure Frequency
*
* This function measures target frequency according to a accurate reference frequency.The formula is:
* Ftarget = (CAPVAL * Freference) / ((1<<SCALE)-1)
*
* @param base ANACTRL peripheral base address.
* @scale Define the power of 2 count that ref counter counts to during measurement.
* @refClkFreq frequency of the reference clock.
* @return frequency of the target clock.
*
* @Note the minimum count (scale) is 2.
*/
uint32_t ANACTRL_MeasureFrequency(ANACTRL_Type *base, uint8_t scale, uint32_t refClkFreq);
/* @} */
/*!
* @name Interrupt Interface
* @{
*/
/*!
* @brief Enable the ANACTRL interrupts.
*
* @param bas ANACTRL peripheral base address.
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
*/
static inline void ANACTRL_EnableInterrupt(ANACTRL_Type *base, uint32_t mask)
{
base->BOD_DCDC_INT_CTRL |= (0x15U & mask);
}
/*!
* @brief Disable the ANACTRL interrupts.
*
* @param bas ANACTRL peripheral base address.
* @param mask The interrupt mask. Refer to "_anactrl_interrupt" enumeration.
*/
static inline void ANACTRL_DisableInterrupt(ANACTRL_Type *base, uint32_t mask)
{
base->BOD_DCDC_INT_CTRL = (base->BOD_DCDC_INT_CTRL & ~0x2AU) | (mask & 0x2AU);
}
/* @} */
/*!
* @name Status Interface
* @{
*/
/*!
* @brief Get ANACTRL status flags.
*
* This function gets Analog control status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_flags.
* For example, to check whether the flash is in power down mode:
* @code
* if (kANACTRL_FlashPowerDownFlag & ANACTRL_ANACTRL_GetStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL status flags which are given in the enumerators in the @ref _anactrl_flags.
*/
static inline uint32_t ANACTRL_GetStatusFlags(ANACTRL_Type *base)
{
return base->ANALOG_CTRL_STATUS;
}
/*!
* @brief Get ANACTRL oscillators status flags.
*
* This function gets Anactrl oscillators status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_osc_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_osc_flags.
* For example, to check whether the FRO192M clock output is valid:
* @code
* if (kANACTRL_OutputClkValidFlag & ANACTRL_ANACTRL_GetOscStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
*/
static inline uint32_t ANACTRL_GetOscStatusFlags(ANACTRL_Type *base)
{
return (base->FRO192M_STATUS & 0xFFU) | ((base->XO32M_STATUS & 0xFFU) << 16U);
}
/*!
* @brief Get ANACTRL interrupt status flags.
*
* This function gets Anactrl interrupt status flags. The flags are returned as the logical
* OR value of the enumerators @ref _anactrl_interrupt_flags. To check for a specific status,
* compare the return value with enumerators in the @ref _anactrl_interrupt_flags.
* For example, to check whether the VBAT voltage level is above the threshold:
* @code
* if (kANACTRL_BodVbatPowerFlag & ANACTRL_ANACTRL_GetInterruptStatusFlags(ANACTRL))
* {
* ...
* }
* @endcode
*
* @param base ANACTRL peripheral base address.
* @return ANACTRL oscillators status flags which are given in the enumerators in the @ref _anactrl_osc_flags.
*/
static inline uint32_t ANACTRL_GetInterruptStatusFlags(ANACTRL_Type *base)
{
return base->BOD_DCDC_INT_STATUS & 0x1FFU;
}
/* @} */
#if defined(__cplusplus)
}
#endif
/* @}*/
#endif /* __FSL_ANACTRL_H__ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_CASPER_H_
#define _FSL_CASPER_H_
#include "fsl_common.h"
/*! @file */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @addtogroup casper_driver
* @{
*/
/*! @name Driver version */
/*@{*/
/*! @brief CASPER driver version. Version 2.0.2.
*
* Current version: 2.0.2
*
* Change log:
* - Version 2.0.0
* - Initial version
* - Version 2.0.1
* - Bug fix KPSDK-24531 double_scalar_multiplication() result may be all zeroes for some specific input
* - Version 2.0.2
* - Bug fix KPSDK-25015 CASPER_MEMCPY hard-fault on LPC55xx when both source and destination buffers are outside of CASPER_RAM
*/
#define FSL_CASPER_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/
/*! @brief CASPER operation
*
*/
typedef enum _casper_operation
{
kCASPER_OpMul6464NoSum = 0x01, /*! Walking 1 or more of J loop, doing r=a*b using 64x64=128*/
kCASPER_OpMul6464Sum =
0x02, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but assume inner j loop*/
kCASPER_OpMul6464FullSum =
0x03, /*! Walking 1 or more of J loop, doing c,r=r+a*b using 64x64=128, but sum all of w. */
kCASPER_OpMul6464Reduce =
0x04, /*! Walking 1 or more of J loop, doing c,r[-1]=r+a*b using 64x64=128, but skip 1st write*/
kCASPER_OpAdd64 = 0x08, /*! Walking add with off_AB, and in/out off_RES doing c,r=r+a+c using 64+64=65*/
kCASPER_OpSub64 = 0x09, /*! Walking subtract with off_AB, and in/out off_RES doing r=r-a uding 64-64=64, with last
borrow implicit if any*/
kCASPER_OpDouble64 = 0x0A, /*! Walking add to self with off_RES doing c,r=r+r+c using 64+64=65*/
kCASPER_OpXor64 = 0x0B, /*! Walking XOR with off_AB, and in/out off_RES doing r=r^a using 64^64=64*/
kCASPER_OpShiftLeft32 =
0x10, /*! Walking shift left doing r1,r=(b*D)|r1, where D is 2^amt and is loaded by app (off_CD not used)*/
kCASPER_OpShiftRight32 = 0x11, /*! Walking shift right doing r,r1=(b*D)|r1, where D is 2^(32-amt) and is loaded by
app (off_CD not used) and off_RES starts at MSW*/
kCASPER_OpCopy = 0x14, /*! Copy from ABoff to resoff, 64b at a time*/
kCASPER_OpRemask = 0x15, /*! Copy and mask from ABoff to resoff, 64b at a time*/
kCASPER_OpCompare = 0x16, /*! Compare two arrays, running all the way to the end*/
kCASPER_OpCompareFast = 0x17, /*! Compare two arrays, stopping on 1st !=*/
} casper_operation_t;
#define CASPER_CP 1
#define CASPER_CP_CTRL0 (0x0 >> 2)
#define CASPER_CP_CTRL1 (0x4 >> 2)
#define CASPER_CP_LOADER (0x8 >> 2)
#define CASPER_CP_STATUS (0xC >> 2)
#define CASPER_CP_INTENSET (0x10 >> 2)
#define CASPER_CP_INTENCLR (0x14 >> 2)
#define CASPER_CP_INTSTAT (0x18 >> 2)
#define CASPER_CP_AREG (0x20 >> 2)
#define CASPER_CP_BREG (0x24 >> 2)
#define CASPER_CP_CREG (0x28 >> 2)
#define CASPER_CP_DREG (0x2C >> 2)
#define CASPER_CP_RES0 (0x30 >> 2)
#define CASPER_CP_RES1 (0x34 >> 2)
#define CASPER_CP_RES2 (0x38 >> 2)
#define CASPER_CP_RES3 (0x3C >> 2)
#define CASPER_CP_MASK (0x60 >> 2)
#define CASPER_CP_REMASK (0x64 >> 2)
#define CASPER_CP_LOCK (0x80 >> 2)
#define CASPER_CP_ID (0xFFC >> 2)
/* mcr (cp, opc1, value, CRn, CRm, opc2) */
#define CASPER_Wr32b(value, off) __arm_mcr(CASPER_CP, 0, value, ((off >> 4)), (off), 0)
/* mcrr(coproc, opc1, value, CRm) */
#define CASPER_Wr64b(value, off) __arm_mcrr(CASPER_CP, 0, value, off)
/* mrc(coproc, opc1, CRn, CRm, opc2) */
#define CASPER_Rd32b(off) __arm_mrc(CASPER_CP, 0, ((off >> 4)), (off), 0)
/* The model for this algo is that it can be implemented for a fixed size RSA key */
/* for max speed. If this is made into a variable (to allow varying size), then */
/* it will be slower by a bit. */
/* The file is compiled with N_bitlen passed in as number of bits of the RSA key */
/* #define N_bitlen 2048 */
#define N_wordlen_max (4096 / 32)
#define CASPER_ECC_P256 1
#define CASPER_ECC_P384 0
#if CASPER_ECC_P256
#define N_bitlen 256
#endif /* CASPER_ECC_P256 */
#if CASPER_ECC_P384
#define N_bitlen 384
#endif /* CASPER_ECC_P256 */
#define NUM_LIMBS (N_bitlen / 32)
enum
{
kCASPER_RamOffset_Result = 0x0u,
kCASPER_RamOffset_Base = (N_wordlen_max + 8u),
kCASPER_RamOffset_TempBase = (2u * N_wordlen_max + 16u),
kCASPER_RamOffset_Modulus = (kCASPER_RamOffset_TempBase + N_wordlen_max + 4u),
kCASPER_RamOffset_M64 = 1022,
};
/*! @} */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @addtogroup casper_driver
* @{
*/
/*!
* @brief Enables clock and disables reset for CASPER peripheral.
*
* Enable clock and disable reset for CASPER.
*
* @param base CASPER base address
*/
void CASPER_Init(CASPER_Type *base);
/*!
* @brief Disables clock for CASPER peripheral.
*
* Disable clock and enable reset.
*
* @param base CASPER base address
*/
void CASPER_Deinit(CASPER_Type *base);
/*!
*@}
*/ /* end of casper_driver */
/*******************************************************************************
* PKHA API
******************************************************************************/
/*!
* @addtogroup casper_driver_pkha
* @{
*/
/*!
* @brief Performs modular exponentiation - (A^E) mod N.
*
* This function performs modular exponentiation.
*
* @param base CASPER base address
* @param signature first addend (in little endian format)
* @param pubN modulus (in little endian format)
* @param wordLen Size of pubN in bytes
* @param pubE exponent
* @param[out] plaintext Output array to store result of operation (in little endian format)
*/
void CASPER_ModExp(CASPER_Type *base,
const uint8_t *signature,
const uint8_t *pubN,
size_t wordLen,
uint32_t pubE,
uint8_t *plaintext);
void CASPER_ecc_init(void);
/*!
* @brief Performs ECC secp256r1 point single scalar multiplication
*
* This function performs ECC secp256r1 point single scalar multiplication
* [resX; resY] = scalar * [X; Y]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate in normal form, little endian.
* @param[out] resY Output Y affine coordinate in normal form, little endian.
* @param X Input X affine coordinate in normal form, little endian.
* @param Y Input Y affine coordinate in normal form, little endian.
* @param scalar Input scalar integer, in normal form, little endian.
*/
void CASPER_ECC_SECP256R1_Mul(
CASPER_Type *base, uint32_t resX[8], uint32_t resY[8], uint32_t X[8], uint32_t Y[8], uint32_t scalar[8]);
/*!
* @brief Performs ECC secp256r1 point double scalar multiplication
*
* This function performs ECC secp256r1 point double scalar multiplication
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate.
* @param[out] resY Output Y affine coordinate.
* @param X1 Input X1 affine coordinate.
* @param Y1 Input Y1 affine coordinate.
* @param scalar1 Input scalar1 integer.
* @param X2 Input X2 affine coordinate.
* @param Y2 Input Y2 affine coordinate.
* @param scalar2 Input scalar2 integer.
*/
void CASPER_ECC_SECP256R1_MulAdd(CASPER_Type *base,
uint32_t resX[8],
uint32_t resY[8],
uint32_t X1[8],
uint32_t Y1[8],
uint32_t scalar1[8],
uint32_t X2[8],
uint32_t Y2[8],
uint32_t scalar2[8]);
/*!
* @brief Performs ECC secp384r1 point single scalar multiplication
*
* This function performs ECC secp384r1 point single scalar multiplication
* [resX; resY] = scalar * [X; Y]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate in normal form, little endian.
* @param[out] resY Output Y affine coordinate in normal form, little endian.
* @param X Input X affine coordinate in normal form, little endian.
* @param Y Input Y affine coordinate in normal form, little endian.
* @param scalar Input scalar integer, in normal form, little endian.
*/
void CASPER_ECC_SECP384R1_Mul(
CASPER_Type *base, uint32_t resX[12], uint32_t resY[12], uint32_t X[12], uint32_t Y[12], uint32_t scalar[12]);
/*!
* @brief Performs ECC secp384r1 point double scalar multiplication
*
* This function performs ECC secp384r1 point double scalar multiplication
* [resX; resY] = scalar1 * [X1; Y1] + scalar2 * [X2; Y2]
* Coordinates are affine in normal form, little endian.
* Scalars are little endian.
* All arrays are little endian byte arrays, uint32_t type is used
* only to enforce the 32-bit alignment (0-mod-4 address).
*
* @param base CASPER base address
* @param[out] resX Output X affine coordinate.
* @param[out] resY Output Y affine coordinate.
* @param X1 Input X1 affine coordinate.
* @param Y1 Input Y1 affine coordinate.
* @param scalar1 Input scalar1 integer.
* @param X2 Input X2 affine coordinate.
* @param Y2 Input Y2 affine coordinate.
* @param scalar2 Input scalar2 integer.
*/
void CASPER_ECC_SECP384R1_MulAdd(CASPER_Type *base,
uint32_t resX[12],
uint32_t resY[12],
uint32_t X1[12],
uint32_t Y1[12],
uint32_t scalar1[12],
uint32_t X2[12],
uint32_t Y2[12],
uint32_t scalar2[12]);
void CASPER_ECC_equal(int *res, uint32_t *op1, uint32_t *op2);
void CASPER_ECC_equal_to_zero(int *res, uint32_t *op1);
/*!
*@}
*/ /* end of casper_driver_pkha */
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_CASPER_H_ */

55
ext/hal/nxp/mcux/drivers/lpc/fsl_cmp.c Normal file
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@ -0,0 +1,55 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_cmp.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.cmp_1"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Prototypes
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
void CMP_Init(cmp_config_t *config)
{
assert(NULL != config);
/*enable the clock to the register interface*/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Comp);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*Clear reset to peripheral cmp*/
#if !(defined(FSL_FEATURE_CMP_HAS_NO_RESET) && FSL_TEATURE_CMP_HAS_NO_RESET)
RESET_ClearPeripheralReset(kCMP_RST_SHIFT_RSTn);
#endif
/*clear COMP bits*/
PMC->COMP &= ~(PMC_COMP_LOWPOWER_MASK | PMC_COMP_HYST_MASK | PMC_COMP_PMUX_MASK | PMC_COMP_NMUX_MASK);
PMC->COMP |= (config->enLowPower << PMC_COMP_LOWPOWER_SHIFT) /*Select if enter low power mode*/
| (config->enHysteris << PMC_COMP_HYST_SHIFT) /*select if enable hysteresis*/
| config->pmuxInput /*pmux input source select*/
| config->nmuxInput; /*nmux input source select */
}
void CMP_Deinit(void)
{
/*disable the clock to the register interface*/
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_Comp);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}

293
ext/hal/nxp/mcux/drivers/lpc/fsl_cmp.h Normal file
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@ -0,0 +1,293 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __FSL_CMP_H_
#define __FSL_CMP_H_
#include "fsl_common.h"
/*!
* @addtogroup cmp_1
* @{
*/
/******************************************************************************
* Definitions.
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.0.0. */
#define FSL_CMP_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 0U))
/*@}*/
/*! @brief VREF select */
enum _cmp_vref_select
{
KCMP_VREFSelectVDDA = 1U, /*!< Select VDDA as VREF*/
KCMP_VREFSelectInternalVREF = 0U, /*!< select internal VREF as VREF*/
};
/*! @brief cmp interrupt type */
typedef enum _cmp_interrupt_type
{
kCMP_EdgeDisable = 0U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable edge sensitive */
kCMP_EdgeRising = 2U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, falling edge */
kCMP_EdgeFalling = 4U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising edge */
kCMP_EdgeRisingFalling = 6U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Edge sensitive, rising and falling edge */
kCMP_LevelDisable = 1U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */
kCMP_LevelHigh = 3U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, high level */
kCMP_LevelLow = 5U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< Level sensitive, low level */
kCMP_LevelDisable1 = 7U << SYSCON_COMP_INT_CTRL_INT_CTRL_SHIFT, /*!< disable level sensitive */
} cmp_interrupt_type_t;
/*! @brief cmp Pmux input source */
typedef enum _cmp_pmux_input
{
kCMP_PInputVREF = 0U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from VREF */
kCMP_PInputP0_0 = 1U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_0 */
kCMP_PInputP0_9 = 2U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_9 */
kCMP_PInputP0_18 = 3U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P0_18 */
kCMP_PInputP1_14 = 4U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P1_14 */
kCMP_PInputP2_23 = 5U << PMC_COMP_PMUX_SHIFT, /*!< Cmp Pmux input from P2_23 */
} cmp_pmux_input_t;
/*! @brief cmp Nmux input source */
typedef enum _cmp_nmux_input
{
kCMP_NInputVREF = 0U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from VREF */
kCMP_NInputP0_0 = 1U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_0 */
kCMP_NInputP0_9 = 2U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_9 */
kCMP_NInputP0_18 = 3U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P0_18 */
kCMP_NInputP1_14 = 4U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P1_14 */
kCMP_NInputP2_23 = 5U << PMC_COMP_NMUX_SHIFT, /*!< Cmp Nmux input from P2_23 */
} cmp_nmux_input_t;
/*! @brief cmp configurataions */
typedef struct _cmp_config
{
bool enHysteris; /*!< low hysteresis */
bool enLowPower; /*!<low power mode*/
cmp_nmux_input_t nmuxInput; /*!<Nmux input select*/
cmp_pmux_input_t pmuxInput; /*!<Pmux input select*/
} cmp_config_t;
/*************************************************************************************************
* API
************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Cmp Initialization and deinitialization
* @{
*/
/*!
* @brief CMP intialization.
* Note: The cmp initial function not responsible for cmp power, application shall handle it.
*
* @param config init configurations.
*/
void CMP_Init(cmp_config_t *config);
/*!
* @brief CMP deintialization.
* Note: The cmp deinit function not responsible for cmp power, application shall handle it.
*
*/
void CMP_Deinit(void);
/* @} */
/*!
* @name cmp functionality
* @{
*/
/*!
* @brief select input source for pmux.
*
* @param pmux_select_source reference cmp_pmux_input_t above.
*/
static inline void CMP_PmuxSelect(cmp_pmux_input_t pmux_select_source)
{
PMC->COMP &= ~PMC_COMP_PMUX_MASK;
PMC->COMP |= pmux_select_source;
}
/*!
* @brief select input source for nmux.
*
* @param nmux_select_source reference cmp_nmux_input_t above.
*/
static inline void CMP_NmuxSelect(cmp_nmux_input_t nmux_select_source)
{
PMC->COMP &= ~PMC_COMP_NMUX_MASK;
PMC->COMP |= nmux_select_source;
}
/*!
* @brief switch cmp work mode.
*
* @param enable true is enter low power mode, false is enter fast mode
*/
static inline void CMP_EnableLowePowerMode(bool enable)
{
if (enable)
{
PMC->COMP |= PMC_COMP_LOWPOWER_MASK;
}
else
{
PMC->COMP &= ~PMC_COMP_LOWPOWER_MASK;
}
}
/*!
* @brief Control reference voltage step, per steps of (VREFINPUT/31).
*
* @param step reference voltage step, per steps of (VREFINPUT/31).
*/
static inline void CMP_SetRefStep(uint32_t step)
{
PMC->COMP |= step << PMC_COMP_VREF_SHIFT;
}
/*!
* @brief cmp enable hysteresis.
*
*/
static inline void CMP_EnableHysteresis(bool enable)
{
if (enable)
{
PMC->COMP |= PMC_COMP_HYST_MASK;
}
else
{
PMC->COMP &= ~PMC_COMP_HYST_MASK;
}
}
/*!
* @brief VREF select between internal VREF and VDDA (for the resistive ladder).
*
* @param select 1 is Select VDDA, 0 is Select internal VREF.
*/
static inline void CMP_VREFSelect(uint32_t select)
{
if (select)
{
PMC->COMP |= PMC_COMP_VREFINPUT_MASK;
}
else
{
PMC->COMP &= ~PMC_COMP_VREFINPUT_MASK;
}
}
/*!
* @brief comparator analog output.
*
* @return 1 indicates p is greater than n, 0 indicates n is greater than p.
*/
static inline uint32_t CMP_GetOutput(void)
{
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_VAL_MASK) ? 1 : 0;
}
/* @} */
/*!
* @name cmp interrupt
* @{
*/
/*!
* @brief cmp enable interrupt.
*
*/
static inline void CMP_EnableInterrupt(void)
{
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
}
/*!
* @brief cmp disable interrupt.
*
*/
static inline void CMP_DisableInterrupt(void)
{
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_ENABLE_MASK;
}
/*!
* @brief Select which Analog comparator output (filtered or un-filtered) is used for interrupt detection.
*
* @param enable true is Select Analog Comparator raw output (unfiltered) as input for interrupt detection.
* false is Select Analog Comparator filtered output as input for interrupt detection.
*/
static inline void CMP_InterruptSourceSelect(bool enable)
{
if (enable)
{
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
}
else
{
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_SOURCE_MASK;
}
}
/*!
* @brief cmp get status.
*
* @return true is interrupt pending, false is no interrupt pending.
*/
static inline bool CMP_GetStatus(void)
{
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_STATUS_MASK) ? true : false;
}
/*!
* @brief cmp clear interrupt status.
*
*/
static inline void CMP_ClearStatus(void)
{
SYSCON->COMP_INT_CTRL |= SYSCON_COMP_INT_CTRL_INT_CLEAR_MASK;
}
/*!
* @brief Comparator interrupt type select.
*
* @param type reference cmp_interrupt_type_t.
*/
static inline void CMP_InterruptTypeSelect(cmp_interrupt_type_t cmp_interrupt_type)
{
SYSCON->COMP_INT_CTRL &= ~SYSCON_COMP_INT_CTRL_INT_CTRL_MASK;
SYSCON->COMP_INT_CTRL |= cmp_interrupt_type;
}
/*!
* @brief cmp get interrupt status.
*
* @return true is interrupt pending, false is no interrupt pending.
*/
static inline bool CMP_GetInterruptStatus(void)
{
return (SYSCON->COMP_INT_STATUS & SYSCON_COMP_INT_STATUS_INT_STATUS_MASK) ? true : false;
}
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* __FSL_CMP_H_ */

325
ext/hal/nxp/mcux/drivers/lpc/fsl_dma.c
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@ -47,22 +47,23 @@ static DMA_Type *const s_dmaBases[] = DMA_BASE_PTRS;
static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS; static const clock_ip_name_t s_dmaClockName[] = DMA_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*! @brief Array to map DMA instance number to IRQ number. */ #if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET)
/*! @brief Pointers to DMA resets for each instance. */
static const reset_ip_name_t s_dmaResets[] = DMA_RSTS_N;
#endif /*! @brief Array to map DMA instance number to IRQ number. */
static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS; static const IRQn_Type s_dmaIRQNumber[] = DMA_IRQS;
/*! @brief Pointers to transfer handle for each DMA channel. */ /*! @brief Pointers to transfer handle for each DMA channel. */
static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS]; static dma_handle_t *s_DMAHandle[FSL_FEATURE_DMA_ALL_CHANNELS];
/*! @brief Static table of descriptors */ SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table0[FSL_FEATURE_DMA_MAX_CHANNELS],
#if defined(__ICCARM__) FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
#pragma data_alignment = FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE #if defined(DMA1)
static dma_descriptor_t s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; SDK_ALIGN(dma_descriptor_t s_dma_descriptor_table1[FSL_FEATURE_DMA_MAX_CHANNELS],
#elif defined(__CC_ARM) || defined(__ARMCC_VERSION) FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE);
__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0, s_dma_descriptor_table1};
s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0}; #else
#elif defined(__GNUC__) static dma_descriptor_t *s_dma_descriptor_table[] = {s_dma_descriptor_table0};
__attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descriptor_t
s_dma_descriptor_table[FSL_FEATURE_SOC_DMA_COUNT][FSL_FEATURE_DMA_MAX_CHANNELS] = {0};
#endif #endif
/******************************************************************************* /*******************************************************************************
@ -71,7 +72,7 @@ __attribute__((aligned(FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE))) static dma_descr
static uint32_t DMA_GetInstance(DMA_Type *base) static uint32_t DMA_GetInstance(DMA_Type *base)
{ {
int32_t instance; uint32_t instance;
/* Find the instance index from base address mappings. */ /* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++) for (instance = 0; instance < ARRAY_SIZE(s_dmaBases); instance++)
{ {
@ -111,13 +112,18 @@ static uint32_t DMA_GetVirtualStartChannel(DMA_Type *base)
*/ */
void DMA_Init(DMA_Type *base) void DMA_Init(DMA_Type *base)
{ {
uint32_t instance = DMA_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* enable dma clock gate */ /* enable dma clock gate */
CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]); CLOCK_EnableClock(s_dmaClockName[DMA_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_DMA_HAS_NO_RESET) && FSL_FEATURE_DMA_HAS_NO_RESET)
/* Reset the DMA module */
RESET_PeripheralReset(s_dmaResets[DMA_GetInstance(base)]);
#endif
/* set descriptor table */ /* set descriptor table */
base->SRAMBASE = (uint32_t)s_dma_descriptor_table; base->SRAMBASE = (uint32_t)s_dma_descriptor_table[instance];
/* enable dma peripheral */ /* enable dma peripheral */
base->CTRL |= DMA_CTRL_ENABLE_MASK; base->CTRL |= DMA_CTRL_ENABLE_MASK;
} }
@ -140,6 +146,7 @@ void DMA_Deinit(DMA_Type *base)
/*! /*!
* brief Set trigger settings of DMA channel. * brief Set trigger settings of DMA channel.
* deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig.
* *
* param base DMA peripheral base address. * param base DMA peripheral base address.
* param channel DMA channel number. * param channel DMA channel number.
@ -157,13 +164,6 @@ void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_t
base->CHANNEL[channel].CFG = tmp; base->CHANNEL[channel].CFG = tmp;
} }
/*!
* @brief Gets the remaining bytes of the current DMA descriptor transfer.
*
* @param base DMA peripheral base address.
* @param channel DMA channel number.
* @return The number of bytes which have not been transferred yet.
*/
/*! /*!
* brief Gets the remaining bytes of the current DMA descriptor transfer. * brief Gets the remaining bytes of the current DMA descriptor transfer.
* *
@ -195,50 +195,39 @@ uint32_t DMA_GetRemainingBytes(DMA_Type *base, uint32_t channel)
1; 1;
} }
static void DMA_SetupDescriptor(
dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc)
{
desc->xfercfg = xfercfg;
desc->srcEndAddr = srcEndAddr;
desc->dstEndAddr = dstEndAddr;
desc->linkToNextDesc = nextDesc;
}
/* Verify and convert dma_xfercfg_t to XFERCFG register */ /* Verify and convert dma_xfercfg_t to XFERCFG register */
static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr) static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
{ {
assert(xfercfg != NULL); assert(xfercfg != NULL);
/* check source increment */ /* check source increment */
assert((xfercfg->srcInc == 0) || (xfercfg->srcInc == 1) || (xfercfg->srcInc == 2) || (xfercfg->srcInc == 4)); assert((xfercfg->srcInc <= kDMA_AddressInterleave4xWidth) && (xfercfg->dstInc <= kDMA_AddressInterleave4xWidth));
/* check destination increment */
assert((xfercfg->dstInc == 0) || (xfercfg->dstInc == 1) || (xfercfg->dstInc == 2) || (xfercfg->dstInc == 4));
/* check data width */ /* check data width */
assert((xfercfg->byteWidth == 1) || (xfercfg->byteWidth == 2) || (xfercfg->byteWidth == 4)); assert(xfercfg->byteWidth <= kDMA_Transfer32BitWidth);
/* check transfer count */ /* check transfer count */
assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT); assert(xfercfg->transferCount <= DMA_MAX_TRANSFER_COUNT);
uint32_t xfer = 0, tmp; uint32_t xfer = 0;
/* set valid flag - descriptor is ready now */ /* set valid flag - descriptor is ready now */
xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_CFGVALID(xfercfg->valid);
/* set reload - allow link to next descriptor */ /* set reload - allow link to next descriptor */
xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload);
/* set swtrig flag - start transfer */ /* set swtrig flag - start transfer */
xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig);
/* set transfer count */ /* set transfer count */
xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig);
/* set INTA */ /* set INTA */
xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA);
/* set INTB */ /* set INTB */
xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB ? 1 : 0); xfer |= DMA_CHANNEL_XFERCFG_SETINTB(xfercfg->intB);
/* set data width */ /* set data width */
tmp = xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1; xfer |= DMA_CHANNEL_XFERCFG_WIDTH(xfercfg->byteWidth == 4 ? 2 : xfercfg->byteWidth - 1);
xfer |= DMA_CHANNEL_XFERCFG_WIDTH(tmp);
/* set source increment value */ /* set source increment value */
tmp = xfercfg->srcInc == 4 ? 3 : xfercfg->srcInc; xfer |= DMA_CHANNEL_XFERCFG_SRCINC((xfercfg->srcInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->srcInc - 1) :
xfer |= DMA_CHANNEL_XFERCFG_SRCINC(tmp); xfercfg->srcInc);
/* set destination increment value */ /* set destination increment value */
tmp = xfercfg->dstInc == 4 ? 3 : xfercfg->dstInc; xfer |= DMA_CHANNEL_XFERCFG_DSTINC((xfercfg->dstInc == kDMA_AddressInterleave4xWidth) ? (xfercfg->dstInc - 1) :
xfer |= DMA_CHANNEL_XFERCFG_DSTINC(tmp); xfercfg->dstInc);
/* set transfer count */ /* set transfer count */
xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1); xfer |= DMA_CHANNEL_XFERCFG_XFERCOUNT(xfercfg->transferCount - 1);
@ -246,10 +235,58 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
*xfercfg_addr = xfer; *xfercfg_addr = xfer;
} }
/*!
* brief setup dma descriptor
*
* param desc DMA descriptor address.
* param xfercfg Transfer configuration for DMA descriptor.
* param srcStartAddr Start address of source address.
* param dstStartAddr Start address of destination address.
* param nextDesc Address of next descriptor in chain.
*/
void DMA_SetupDescriptor(
dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc)
{
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
uint32_t width = 0, srcInc = 0, dstInc = 0, transferCount = 0;
width = (xfercfg & DMA_CHANNEL_XFERCFG_WIDTH_MASK) >> DMA_CHANNEL_XFERCFG_WIDTH_SHIFT;
srcInc = (xfercfg & DMA_CHANNEL_XFERCFG_SRCINC_MASK) >> DMA_CHANNEL_XFERCFG_SRCINC_SHIFT;
dstInc = (xfercfg & DMA_CHANNEL_XFERCFG_DSTINC_MASK) >> DMA_CHANNEL_XFERCFG_DSTINC_SHIFT;
transferCount = ((xfercfg & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT) + 1U;
/* covert register value to actual value */
if (width == 2U)
{
width = kDMA_Transfer32BitWidth;
}
else
{
width += 1U;
}
if (srcInc == 3U)
{
srcInc = kDMA_AddressInterleave4xWidth;
}
if (dstInc == 3U)
{
dstInc = kDMA_AddressInterleave4xWidth;
}
desc->xfercfg = xfercfg;
desc->srcEndAddr = DMA_DESCRIPTOR_END_ADDRESS(srcStartAddr, srcInc, transferCount * width, width);
desc->dstEndAddr = DMA_DESCRIPTOR_END_ADDRESS(dstStartAddr, dstInc, transferCount * width, width);
;
desc->linkToNextDesc = nextDesc;
}
/*! /*!
* brief Create application specific DMA descriptor * brief Create application specific DMA descriptor
* to be used in a chain in transfer * to be used in a chain in transfer
* * deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor
* param desc DMA descriptor address. * param desc DMA descriptor address.
* param xfercfg Transfer configuration for DMA descriptor. * param xfercfg Transfer configuration for DMA descriptor.
* param srcAddr Address of last item to transmit * param srcAddr Address of last item to transmit
@ -258,20 +295,16 @@ static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
*/ */
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc) void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
{ {
uint32_t xfercfg_reg = 0; assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
assert((NULL != desc) && (0 == (uint32_t)desc % 16) && (NULL != xfercfg));
assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth)); assert((NULL != srcAddr) && (0 == (uint32_t)srcAddr % xfercfg->byteWidth));
assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth)); assert((NULL != dstAddr) && (0 == (uint32_t)dstAddr % xfercfg->byteWidth));
assert((NULL == nextDesc) || (0 == (uint32_t)nextDesc % 16));
/* Setup channel configuration */ uint32_t xfercfg_reg = 0;
DMA_SetupXferCFG(xfercfg, &xfercfg_reg); DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
/* Set descriptor structure */ /* Set descriptor structure */
DMA_SetupDescriptor( DMA_SetupDescriptor(desc, xfercfg_reg, srcAddr, dstAddr, nextDesc);
desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
(uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc);
} }
/*! /*!
@ -320,6 +353,8 @@ void DMA_CreateHandle(dma_handle_t *handle, DMA_Type *base, uint32_t channel)
s_DMAHandle[startChannel + channel] = handle; s_DMAHandle[startChannel + channel] = handle;
/* Enable NVIC interrupt */ /* Enable NVIC interrupt */
EnableIRQ(s_dmaIRQNumber[dmaInstance]); EnableIRQ(s_dmaIRQNumber[dmaInstance]);
/* Enable channel interrupt */
DMA_EnableChannelInterrupts(handle->base, channel);
} }
/*! /*!
@ -342,7 +377,8 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData
/*! /*!
* brief Prepares the DMA transfer structure. * brief Prepares the DMA transfer structure.
* * deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer and
* DMA_PrepareChannelXfer.
* This function prepares the transfer configuration structure according to the user input. * This function prepares the transfer configuration structure according to the user input.
* *
* param config The user configuration structure of type dma_transfer_t. * param config The user configuration structure of type dma_transfer_t.
@ -367,6 +403,7 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
uint32_t xfer_count; uint32_t xfer_count;
assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr)); assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4)); assert((byteWidth == 1) || (byteWidth == 2) || (byteWidth == 4));
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
/* check max */ /* check max */
xfer_count = transferBytes / byteWidth; xfer_count = transferBytes / byteWidth;
@ -411,8 +448,151 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
config->xfercfg.valid = true; config->xfercfg.valid = true;
} }
/*!
* brief set channel config.
*
* This function provide a interface to configure channel configuration reisters.
*
* param base DMA base address.
* param channel DMA channel number.
* param config channel configurations structure.
*/
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph)
{
assert(channel <= FSL_FEATURE_DMA_MAX_CHANNELS);
uint32_t tmp = DMA_CHANNEL_CFG_PERIPHREQEN_MASK;
if (trigger != NULL)
{
tmp |= DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK;
}
tmp = base->CHANNEL[channel].CFG & (~tmp);
if (trigger != NULL)
{
tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
}
tmp |= DMA_CHANNEL_CFG_PERIPHREQEN(isPeriph);
base->CHANNEL[channel].CFG = tmp;
}
/*!
* brief Prepare channel transfer configurations.
*
* This function used to prepare channel transfer configurations.
*
* param config Pointer to DMA channel transfer configuration structure.
* param srcStartAddr source start address.
* param dstStartAddr destination start address.
* param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
* param type transfer type.
* param trigger DMA channel trigger configurations.
* param nextDesc address of next descriptor.
*/
void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
void *srcStartAddr,
void *dstStartAddr,
uint32_t xferCfg,
dma_transfer_type_t type,
dma_channel_trigger_t *trigger,
void *nextDesc)
{
assert((NULL != config) && (NULL != srcStartAddr) && (NULL != dstStartAddr));
assert(((uint32_t)nextDesc & (DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN - 1)) == 0U);
/* check max */
memset(config, 0, sizeof(*config));
switch (type)
{
case kDMA_MemoryToMemory:
config->isPeriph = false;
break;
case kDMA_PeripheralToMemory:
config->isPeriph = true;
break;
case kDMA_MemoryToPeripheral:
config->isPeriph = true;
break;
case kDMA_StaticToStatic:
config->isPeriph = true;
break;
default:
return;
}
config->dstStartAddr = (uint8_t *)dstStartAddr;
config->srcStartAddr = (uint8_t *)srcStartAddr;
config->nextDesc = (uint8_t *)nextDesc;
config->trigger = trigger;
config->xferCfg = xferCfg;
}
/*!
* brief Install DMA descriptor memory.
*
* This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong
* transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has
* a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.
* User should be take care about the address of DMA descriptor pool which required align with 512BYTE.
*
* param handle Pointer to DMA channel transfer handle.
* param addr DMA descriptor address
* param num DMA descriptor number.
*/
void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr)
{
assert(addr != NULL);
assert(((uint32_t)addr & (FSL_FEATURE_DMA_DESCRIPTOR_ALIGN_SIZE - 1U)) == 0U);
/* reconfigure the DMA descriptor base address */
base->SRAMBASE = (uint32_t)addr;
}
/*!
* brief Submits the DMA channel transfer request.
*
* This function submits the DMA transfer request according to the transfer configuration structure.
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
* a TCD and enables scatter/gather feature to process it in the next time.
*
* param handle DMA handle pointer.
* param config Pointer to DMA transfer configuration structure.
* retval kStatus_DMA_Success It means submit transfer request succeed.
* retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
* retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
*/
status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config)
{
assert((NULL != handle) && (NULL != config));
assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
uint32_t instance = DMA_GetInstance(handle->base);
dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
/* Previous transfer has not finished */
if (DMA_ChannelIsActive(handle->base, handle->channel))
{
return kStatus_DMA_Busy;
}
DMA_SetupDescriptor(descriptor, config->xferCfg, config->srcStartAddr, config->dstStartAddr, config->nextDesc);
DMA_SetChannelConfig(handle->base, handle->channel, config->trigger, config->isPeriph);
/* Set channel XFERCFG register according first channel descriptor. */
handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg;
return kStatus_Success;
}
/*! /*!
* brief Submits the DMA transfer request. * brief Submits the DMA transfer request.
* deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer.
* *
* This function submits the DMA transfer request according to the transfer configuration structure. * This function submits the DMA transfer request according to the transfer configuration structure.
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
@ -427,7 +607,10 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config) status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
{ {
assert((NULL != handle) && (NULL != config)); assert((NULL != handle) && (NULL != config));
assert(handle->channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
uint32_t instance = DMA_GetInstance(handle->base); uint32_t instance = DMA_GetInstance(handle->base);
dma_descriptor_t *descriptor = (dma_descriptor_t *)(&s_dma_descriptor_table[instance][handle->channel]);
/* Previous transfer has not finished */ /* Previous transfer has not finished */
if (DMA_ChannelIsActive(handle->base, handle->channel)) if (DMA_ChannelIsActive(handle->base, handle->channel))
@ -445,8 +628,9 @@ status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config)
DMA_DisableChannelPeriphRq(handle->base, handle->channel); DMA_DisableChannelPeriphRq(handle->base, handle->channel);
} }
DMA_CreateDescriptor(&(s_dma_descriptor_table[instance][handle->channel]), &config->xfercfg, config->srcAddr, DMA_CreateDescriptor(descriptor, &config->xfercfg, config->srcAddr, config->dstAddr, config->nextDesc);
config->dstAddr, config->nextDesc); /* Set channel XFERCFG register according first channel descriptor. */
handle->base->CHANNEL[handle->channel].XFERCFG = descriptor->xfercfg;
return kStatus_Success; return kStatus_Success;
} }
@ -463,27 +647,18 @@ void DMA_StartTransfer(dma_handle_t *handle)
{ {
assert(NULL != handle); assert(NULL != handle);
uint32_t instance = DMA_GetInstance(handle->base); uint32_t channel = handle->channel;
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELSn(handle->base));
/* Enable channel interrupt */ /* enable channel */
DMA_EnableChannelInterrupts(handle->base, handle->channel); DMA_EnableChannel(handle->base, channel);
/* If HW trigger is enabled - disable SW trigger */ /* user software trigger if Peripheral request not enabled */
if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK) if (((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGBURST_MASK) != 0U) ||
((handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_TRIGTYPE_MASK) != DMA_CHANNEL_CFG_TRIGTYPE(1U)))
{ {
s_dma_descriptor_table[instance][handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK); handle->base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
} }
/* Otherwise enable SW trigger */
else
{
s_dma_descriptor_table[instance][handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
}
/* Set channel XFERCFG register according first channel descriptor. */
handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[instance][handle->channel].xfercfg;
/* At this moment, the channel ACTIVE bit is set and application cannot modify
* or start another transfer using this channel. Channel ACTIVE bit is cleared by
* 'AbortTransfer' function or when the transfer finishes */
} }
void DMA_IRQHandle(DMA_Type *base) void DMA_IRQHandle(DMA_Type *base)

182
ext/hal/nxp/mcux/drivers/lpc/fsl_dma.h
View file

@ -24,7 +24,7 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief DMA driver version */ /*! @brief DMA driver version */
#define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */ #define FSL_DMA_DRIVER_VERSION (MAKE_VERSION(2, 2, 1)) /*!< Version 2.2.1. */
/*@}*/ /*@}*/
#define DMA_MAX_TRANSFER_COUNT 0x400 #define DMA_MAX_TRANSFER_COUNT 0x400
@ -40,7 +40,8 @@
#define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U) #define DMA_CHANNEL_GROUP(channel) (((uint8_t)(channel)) >> 5U)
/* Channel index in channel group. channel_index = (channel % 32) */ /* Channel index in channel group. channel_index = (channel % 32) */
#define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F) #define DMA_CHANNEL_INDEX(channel) (((uint8_t)(channel)) & 0x1F)
/*! @brief DMA linked descriptor address algin size */
#define DMA_LINK_DESCRIPTOR_ADDRESS_ALIGN (16)
#define DMA_COMMON_REG_GET(base, channel, reg) \ #define DMA_COMMON_REG_GET(base, channel, reg) \
(((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)]) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)])
#define DMA_COMMON_CONST_REG_GET(base, channel, reg) \ #define DMA_COMMON_CONST_REG_GET(base, channel, reg) \
@ -48,6 +49,56 @@
#define DMA_COMMON_REG_SET(base, channel, reg, value) \ #define DMA_COMMON_REG_SET(base, channel, reg, value) \
(((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value)) (((volatile uint32_t *)(&((base)->COMMON[0].reg)))[DMA_CHANNEL_GROUP(channel)] = (value))
/*! @brief DMA descriptor end address calculate
* @param start, start address
* @param inc, address interleave size
* @param bytes, transfer bytes
* @param width, transfer width
*/
#define DMA_DESCRIPTOR_END_ADDRESS(start, inc, bytes, width) ((void *)((uint32_t)(start) + inc * bytes - inc * width))
/*! @brief DMA channel transfer configurations macro
* @param reload, true is reload link descriptor after current exhaust, false is not
* @param clrTrig, true is clear trigger status, wait software trigger, false is not
* @param intA, enable interruptA
* @param intB, enable interruptB
* @param width,transfer width
* @param srcInc, source address interleave size
* @param dstInc, destination address interleave size
* @param bytes, transfer bytes
*/
#define DMA_CHANNEL_XFER(reload, clrTrig, intA, intB, width, srcInc, dstInc, bytes) \
DMA_CHANNEL_XFERCFG_CFGVALID_MASK | DMA_CHANNEL_XFERCFG_RELOAD(reload) | DMA_CHANNEL_XFERCFG_CLRTRIG(clrTrig) | \
DMA_CHANNEL_XFERCFG_SETINTA(intA) | DMA_CHANNEL_XFERCFG_SETINTB(intB) | \
DMA_CHANNEL_XFERCFG_WIDTH(width == 4 ? 2 : (width - 1)) | \
DMA_CHANNEL_XFERCFG_SRCINC(srcInc == 4 ? (srcInc - 1) : srcInc) | \
DMA_CHANNEL_XFERCFG_DSTINC(dstInc == 4 ? (srcInc - 1) : dstInc) | \
DMA_CHANNEL_XFERCFG_XFERCOUNT(bytes / width - 1)
/*! @brief DMA transfer status */
enum _dma_transfer_status
{
kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
transfer request. */
};
/*! @brief dma address interleave size */
enum _dma_addr_interleave_size
{
kDMA_AddressInterleave0xWidth = 0U, /*!< dma source/destination address no interleave */
kDMA_AddressInterleave1xWidth = 1U, /*!< dma source/destination address interleave 1xwidth */
kDMA_AddressInterleave2xWidth = 2U, /*!< dma source/destination address interleave 2xwidth */
kDMA_AddressInterleave4xWidth = 4U, /*!< dma source/destination address interleave 3xwidth */
};
/*! @brief dma transfer width */
enum _dma_transfer_width
{
kDMA_Transfer8BitWidth = 1U, /*!< dma channel transfer bit width is 8 bit */
kDMA_Transfer16BitWidth = 2U, /*!< dma channel transfer bit width is 16 bit */
kDMA_Transfer32BitWidth = 4U, /*!< dma channel transfer bit width is 32 bit */
};
/*! @brief DMA descriptor structure */ /*! @brief DMA descriptor structure */
typedef struct _dma_descriptor typedef struct _dma_descriptor
{ {
@ -162,12 +213,16 @@ typedef struct _dma_channel_trigger
dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */ dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
} dma_channel_trigger_t; } dma_channel_trigger_t;
/*! @brief DMA transfer status */ /*! @brief DMA channel trigger */
enum _dma_transfer_status typedef struct _dma_channel_config
{ {
kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the void *srcStartAddr; /*!< Source data address */
transfer request. */ void *dstStartAddr; /*!< Destination data address */
}; void *nextDesc; /*!< Chain custom descriptor */
uint32_t xferCfg; /*!< channel transfer configurations */
dma_channel_trigger_t *trigger; /*!< DMA trigger type */
bool isPeriph; /*!< select the request type */
} dma_channel_config_t;
/*! @brief DMA transfer configuration */ /*! @brief DMA transfer configuration */
typedef struct _dma_transfer_config typedef struct _dma_transfer_config
@ -226,6 +281,18 @@ void DMA_Init(DMA_Type *base);
*/ */
void DMA_Deinit(DMA_Type *base); void DMA_Deinit(DMA_Type *base);
/*!
* @brief Install DMA descriptor memory.
*
* This function used to register DMA descriptor memory for linked transfer, a typical case is ping pong
* transfer which will request more than one DMA descriptor memory space, althrough current DMA driver has
* a default DMA descriptor buffer, but it support one DMA descriptor for one channel only.
*
* @param base DMA base address.
* @param addr DMA descriptor address
*/
void DMA_InstallDescriptorMemory(DMA_Type *base, void *addr);
/* @} */ /* @} */
/*! /*!
* @name DMA Channel Operation * @name DMA Channel Operation
@ -320,6 +387,7 @@ static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
/*! /*!
* @brief Set trigger settings of DMA channel. * @brief Set trigger settings of DMA channel.
* @deprecated Do not use this function. It has been superceded by @ref DMA_SetChannelConfig.
* *
* @param base DMA peripheral base address. * @param base DMA peripheral base address.
* @param channel DMA channel number. * @param channel DMA channel number.
@ -327,6 +395,18 @@ static inline void DMA_DisableChannelPeriphRq(DMA_Type *base, uint32_t channel)
*/ */
void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger); void DMA_ConfigureChannelTrigger(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger);
/*!
* @brief set channel config.
*
* This function provide a interface to configure channel configuration reisters.
*
* @param base DMA base address.
* @param channel DMA channel number.
* @param trigger channel configurations structure.
* @param isPeriph true is periph request, false is not.
*/
void DMA_SetChannelConfig(DMA_Type *base, uint32_t channel, dma_channel_trigger_t *trigger, bool isPeriph);
/*! /*!
* @brief Gets the remaining bytes of the current DMA descriptor transfer. * @brief Gets the remaining bytes of the current DMA descriptor transfer.
* *
@ -364,10 +444,44 @@ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t cha
DMA_CHANNEL_CFG_CHPRIORITY_SHIFT); DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
} }
/*!
* @brief Set channel configuration valid..
*
* @param base DMA peripheral base address.
* @param channel DMA channel number.
*/
static inline void DMA_SetChannelConfigValid(DMA_Type *base, uint32_t channel)
{
base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_CFGVALID_MASK;
}
/*!
* @brief Do software trigger for the channel.
*
* @param base DMA peripheral base address.
* @param channel DMA channel number.
*/
static inline void DMA_DoChannelSoftwareTrigger(DMA_Type *base, uint32_t channel)
{
base->CHANNEL[channel].XFERCFG |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
}
/*!
* @brief Load channel transfer configurations.
*
* @param base DMA peripheral base address.
* @param channel DMA channel number.
* @param xfer transfer configurations.
*/
static inline void DMA_LoadChannelTransferConfig(DMA_Type *base, uint32_t channel, uint32_t xfer)
{
base->CHANNEL[channel].XFERCFG = xfer;
}
/*! /*!
* @brief Create application specific DMA descriptor * @brief Create application specific DMA descriptor
* to be used in a chain in transfer * to be used in a chain in transfer
* * @deprecated Do not use this function. It has been superceded by @ref DMA_SetupDescriptor.
* @param desc DMA descriptor address. * @param desc DMA descriptor address.
* @param xfercfg Transfer configuration for DMA descriptor. * @param xfercfg Transfer configuration for DMA descriptor.
* @param srcAddr Address of last item to transmit * @param srcAddr Address of last item to transmit
@ -376,6 +490,18 @@ static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t cha
*/ */
void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc); void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
/*!
* @brief setup dma descriptor
*
* @param desc DMA descriptor address.
* @param xfercfg Transfer configuration for DMA descriptor.
* @param srcStartAddr Start address of source address.
* @param dstStartAddr Start address of destination address.
* @param nextDesc Address of next descriptor in chain.
*/
void DMA_SetupDescriptor(
dma_descriptor_t *desc, uint32_t xfercfg, void *srcStartAddr, void *dstStartAddr, void *nextDesc);
/* @} */ /* @} */
/*! /*!
@ -419,7 +545,7 @@ void DMA_SetCallback(dma_handle_t *handle, dma_callback callback, void *userData
/*! /*!
* @brief Prepares the DMA transfer structure. * @brief Prepares the DMA transfer structure.
* * @deprecated Do not use this function. It has been superceded by @ref DMA_PrepareChannelTransfer.
* This function prepares the transfer configuration structure according to the user input. * This function prepares the transfer configuration structure according to the user input.
* *
* @param config The user configuration structure of type dma_transfer_t. * @param config The user configuration structure of type dma_transfer_t.
@ -441,8 +567,30 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
dma_transfer_type_t type, dma_transfer_type_t type,
void *nextDesc); void *nextDesc);
/*!
* @brief Prepare channel transfer configurations.
*
* This function used to prepare channel transfer configurations.
*
* @param config Pointer to DMA channel transfer configuration structure.
* @param srcStartAddr source start address.
* @param dstStartAddr destination start address.
* @param xferCfg xfer configuration, user can reference DMA_CHANNEL_XFER about to how to get xferCfg value.
* @param type transfer type.
* @param trigger DMA channel trigger configurations.
* @param nextDesc address of next descriptor.
*/
void DMA_PrepareChannelTransfer(dma_channel_config_t *config,
void *srcStartAddr,
void *dstStartAddr,
uint32_t xferCfg,
dma_transfer_type_t type,
dma_channel_trigger_t *trigger,
void *nextDesc);
/*! /*!
* @brief Submits the DMA transfer request. * @brief Submits the DMA transfer request.
* @deprecated Do not use this function. It has been superceded by @ref DMA_SubmitChannelTransfer.
* *
* This function submits the DMA transfer request according to the transfer configuration structure. * This function submits the DMA transfer request according to the transfer configuration structure.
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as * If the user submits the transfer request repeatedly, this function packs an unprocessed request as
@ -456,6 +604,22 @@ void DMA_PrepareTransfer(dma_transfer_config_t *config,
*/ */
status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config); status_t DMA_SubmitTransfer(dma_handle_t *handle, dma_transfer_config_t *config);
/*!
* @brief Submits the DMA channel transfer request.
*
* This function submits the DMA transfer request according to the transfer configuration structure.
* If the user submits the transfer request repeatedly, this function packs an unprocessed request as
* a TCD and enables scatter/gather feature to process it in the next time.
* This function should use together with DMA_PrepareChannelTransfer.
*
* @param handle DMA handle pointer.
* @param config Pointer to DMA channel transfer configuration structure.
* @retval kStatus_DMA_Success It means submit transfer request succeed.
* @retval kStatus_DMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
* @retval kStatus_DMA_Busy It means the given channel is busy, need to submit request later.
*/
status_t DMA_SubmitChannelTransfer(dma_handle_t *handle, dma_channel_config_t *config);
/*! /*!
* @brief DMA start transfer. * @brief DMA start transfer.
* *

12
ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.c
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@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -85,7 +85,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
{ {
if (config->pinDirection == kGPIO_DigitalInput) if (config->pinDirection == kGPIO_DigitalInput)
{ {
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
base->DIRCLR[port] = 1U << pin;
#else
base->DIR[port] &= ~(1U << pin); base->DIR[port] &= ~(1U << pin);
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
} }
else else
{ {
@ -98,7 +102,11 @@ void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_c
{ {
base->SET[port] = (1U << pin); base->SET[port] = (1U << pin);
} }
/* Set pin direction */ /* Set pin direction */
#if defined(FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR) && (FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR)
base->DIRSET[port] = 1U << pin;
#else
base->DIR[port] |= 1U << pin; base->DIR[port] |= 1U << pin;
#endif /*FSL_FEATURE_GPIO_DIRSET_AND_DIRCLR*/
} }
} }

8
ext/hal/nxp/mcux/drivers/lpc/fsl_gpio.h
View file

@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -24,8 +24,8 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief LPC GPIO driver version 2.1.2. */ /*! @brief LPC GPIO driver version 2.1.3. */
#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 2)) #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
/*@}*/ /*@}*/
/*! @brief LPC GPIO direction definition */ /*! @brief LPC GPIO direction definition */
@ -41,7 +41,7 @@ typedef enum _gpio_pin_direction
* Every pin can only be configured as either output pin or input pin at a time. * Every pin can only be configured as either output pin or input pin at a time.
* If configured as a input pin, then leave the outputConfig unused. * If configured as a input pin, then leave the outputConfig unused.
*/ */
typedef struct z_gpio_pin_config typedef struct _gpio_pin_config
{ {
gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */ gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
/* Output configurations, please ignore if configured as a input one */ /* Output configurations, please ignore if configured as a input one */

1307
ext/hal/nxp/mcux/drivers/lpc/fsl_hashcrypt.c Normal file
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420
ext/hal/nxp/mcux/drivers/lpc/fsl_hashcrypt.h Normal file
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@ -0,0 +1,420 @@
/*
* Copyright 2017-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_HASHCRYPT_H_
#define _FSL_HASHCRYPT_H_
#include "fsl_common.h"
/*! @brief HASHCRYPT status return codes. */
enum _hashcrypt_status
{
kStatus_HASHCRYPT_Again =
MAKE_STATUS(kStatusGroup_HASHCRYPT, 0), /*!< Non-blocking function shall be called again. */
};
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @addtogroup hashcrypt_driver
* @{
*/
/*! @name Driver version */
/*@{*/
/*! @brief HASHCRYPT driver version. Version 2.0.0.
*
* Current version: 2.0.0
*
* Change log:
* - Version 2.0.0
* - Initial version
*/
#define FSL_HASHCRYPT_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*! @brief Algorithm used for Hashcrypt operation */
typedef enum _hashcrypt_algo_t
{
kHASHCRYPT_Sha1 = 1, /*!< SHA_1 */
kHASHCRYPT_Sha256 = 2, /*!< SHA_256 */
kHASHCRYPT_Sha512 = 3, /*!< SHA_512 */
kHASHCRYPT_Aes = 4, /*!< AES */
kHASHCRYPT_AesIcb = 5, /*!< AES_ICB */
} hashcrypt_algo_t;
/*! @} */
/*******************************************************************************
* AES Definitions
*******************************************************************************/
/*!
* @addtogroup hashcrypt_driver_aes
* @{
*/
/*! AES block size in bytes */
#define HASHCRYPT_AES_BLOCK_SIZE 16
#define AES_ENCRYPT 0
#define AES_DECRYPT 1
/*! @brief AES mode */
typedef enum _hashcrypt_aes_mode_t
{
kHASHCRYPT_AesEcb = 0U, /*!< AES ECB mode */
kHASHCRYPT_AesCbc = 1U, /*!< AES CBC mode */
kHASHCRYPT_AesCtr = 2U, /*!< AES CTR mode */
} hashcrypt_aes_mode_t;
/*! @brief Size of AES key */
typedef enum _hashcrypt_aes_keysize_t
{
kHASHCRYPT_Aes128 = 0U, /*!< AES 128 bit key */
kHASHCRYPT_Aes192 = 1U, /*!< AES 192 bit key */
kHASHCRYPT_Aes256 = 2U, /*!< AES 256 bit key */
kHASHCRYPT_InvalidKey = 3U, /*!< AES invalid key */
} hashcrypt_aes_keysize_t;
/*! @brief HASHCRYPT key source selection.
*
*/
typedef enum _hashcrypt_key
{
kHASHCRYPT_UserKey = 0xc3c3U, /*!< HASHCRYPT user key */
kHASHCRYPT_SecretKey = 0x3c3cU, /*!< HASHCRYPT secret key (dedicated hw bus from PUF) */
} hashcrypt_key_t;
/*! @brief Specify HASHCRYPT's key resource. */
typedef struct _hashcrypt_handle
{
uint32_t keyWord[8]; /*!< Copy of user key (set by HASHCRYPT_AES_SetKey(). */
hashcrypt_aes_keysize_t keySize;
hashcrypt_key_t keyType; /*!< For operations with key (such as AES encryption/decryption), specify key type. */
} hashcrypt_handle_t;
/*!
*@}
*/ /* end of hashcrypt_driver_aes */
/*******************************************************************************
* HASH Definitions
******************************************************************************/
/*!
* @addtogroup hashcrypt_driver_hash
* @{
*/
/*! @brief HASHCRYPT HASH Context size. */
#define HASHCRYPT_HASH_CTX_SIZE 22
/*! @brief Storage type used to save hash context. */
typedef struct _hashcrypt_hash_ctx_t
{
uint32_t x[HASHCRYPT_HASH_CTX_SIZE]; /*!< storage */
} hashcrypt_hash_ctx_t;
/*! @brief HASHCRYPT background hash callback function. */
typedef void (*hashcrypt_callback_t)(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, status_t status, void *userData);
/*!
*@}
*/ /* end of hashcrypt_driver_hash */
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @addtogroup hashcrypt_driver
* @{
*/
/*!
* @brief Enables clock and disables reset for HASHCRYPT peripheral.
*
* Enable clock and disable reset for HASHCRYPT.
*
* @param base HASHCRYPT base address
*/
void HASHCRYPT_Init(HASHCRYPT_Type *base);
/*!
* @brief Disables clock for HASHCRYPT peripheral.
*
* Disable clock and enable reset.
*
* @param base HASHCRYPT base address
*/
void HASHCRYPT_Deinit(HASHCRYPT_Type *base);
/*!
*@}
*/ /* end of hashcrypt_driver */
/*******************************************************************************
* AES API
******************************************************************************/
/*!
* @addtogroup hashcrypt_driver_aes
* @{
*/
/*!
* @brief Set AES key to hashcrypt_handle_t struct and optionally to HASHCRYPT.
*
* Sets the AES key for encryption/decryption with the hashcrypt_handle_t structure.
* The hashcrypt_handle_t input argument specifies key source.
*
* @param base HASHCRYPT peripheral base address.
* @param handle Handle used for the request.
* @param key 0-mod-4 aligned pointer to AES key.
* @param keySize AES key size in bytes. Shall equal 16, 24 or 32.
* @return status from set key operation
*/
status_t HASHCRYPT_AES_SetKey(HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *key, size_t keySize);
/*!
* @brief Encrypts AES on one or multiple 128-bit block(s).
*
* Encrypts AES.
* The source plaintext and destination ciphertext can overlap in system memory.
*
* @param base HASHCRYPT peripheral base address
* @param handle Handle used for this request.
* @param plaintext Input plain text to encrypt
* @param[out] ciphertext Output cipher text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @return Status from encrypt operation
*/
status_t HASHCRYPT_AES_EncryptEcb(
HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *plaintext, uint8_t *ciphertext, size_t size);
/*!
* @brief Decrypts AES on one or multiple 128-bit block(s).
*
* Decrypts AES.
* The source ciphertext and destination plaintext can overlap in system memory.
*
* @param base HASHCRYPT peripheral base address
* @param handle Handle used for this request.
* @param ciphertext Input plain text to encrypt
* @param[out] plaintext Output cipher text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @return Status from decrypt operation
*/
status_t HASHCRYPT_AES_DecryptEcb(
HASHCRYPT_Type *base, hashcrypt_handle_t *handle, const uint8_t *ciphertext, uint8_t *plaintext, size_t size);
/*!
* @brief Encrypts AES using CBC block mode.
*
* @param base HASHCRYPT peripheral base address
* @param handle Handle used for this request.
* @param plaintext Input plain text to encrypt
* @param[out] ciphertext Output cipher text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @param iv Input initial vector to combine with the first input block.
* @return Status from encrypt operation
*/
status_t HASHCRYPT_AES_EncryptCbc(HASHCRYPT_Type *base,
hashcrypt_handle_t *handle,
const uint8_t *plaintext,
uint8_t *ciphertext,
size_t size,
const uint8_t iv[16]);
/*!
* @brief Decrypts AES using CBC block mode.
*
* @param base HASHCRYPT peripheral base address
* @param handle Handle used for this request.
* @param ciphertext Input cipher text to decrypt
* @param[out] plaintext Output plain text
* @param size Size of input and output data in bytes. Must be multiple of 16 bytes.
* @param iv Input initial vector to combine with the first input block.
* @return Status from decrypt operation
*/
status_t HASHCRYPT_AES_DecryptCbc(HASHCRYPT_Type *base,
hashcrypt_handle_t *handle,
const uint8_t *ciphertext,
uint8_t *plaintext,
size_t size,
const uint8_t iv[16]);
/*!
* @brief Encrypts or decrypts AES using CTR block mode.
*
* Encrypts or decrypts AES using CTR block mode.
* AES CTR mode uses only forward AES cipher and same algorithm for encryption and decryption.
* The only difference between encryption and decryption is that, for encryption, the input argument
* is plain text and the output argument is cipher text. For decryption, the input argument is cipher text
* and the output argument is plain text.
*
* @param base HASHCRYPT peripheral base address
* @param handle Handle used for this request.
* @param input Input data for CTR block mode
* @param[out] output Output data for CTR block mode
* @param size Size of input and output data in bytes
* @param[in,out] counter Input counter (updates on return)
* @param[out] counterlast Output cipher of last counter, for chained CTR calls (statefull encryption). NULL can be
* passed if chained calls are
* not used.
* @param[out] szLeft Output number of bytes in left unused in counterlast block. NULL can be passed if chained calls
* are not used.
* @return Status from encrypt operation
*/
status_t HASHCRYPT_AES_CryptCtr(HASHCRYPT_Type *base,
hashcrypt_handle_t *handle,
const uint8_t *input,
uint8_t *output,
size_t size,
uint8_t counter[HASHCRYPT_AES_BLOCK_SIZE],
uint8_t counterlast[HASHCRYPT_AES_BLOCK_SIZE],
size_t *szLeft);
/*!
*@}
*/ /* end of hashcrypt_driver_aes */
/*******************************************************************************
* HASH API
******************************************************************************/
/*!
* @addtogroup hashcrypt_driver_hash
* @{
*/
/*!
* @brief Create HASH on given data
*
* Perform the full SHA in one function call. The function is blocking.
*
* @param base HASHCRYPT peripheral base address
* @param algo Underlaying algorithm to use for hash computation.
* @param input Input data
* @param inputSize Size of input data in bytes
* @param[out] output Output hash data
* @param[out] outputSize Output parameter storing the size of the output hash in bytes
* @return Status of the one call hash operation.
*/
status_t HASHCRYPT_SHA(HASHCRYPT_Type *base,
hashcrypt_algo_t algo,
const uint8_t *input,
size_t inputSize,
uint8_t *output,
size_t *outputSize);
/*!
* @brief Initialize HASH context
*
* This function initializes the HASH.
*
* @param base HASHCRYPT peripheral base address
* @param[out] ctx Output hash context
* @param algo Underlaying algorithm to use for hash computation.
* @return Status of initialization
*/
status_t HASHCRYPT_SHA_Init(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, hashcrypt_algo_t algo);
/*!
* @brief Add data to current HASH
*
* Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
* hashed. The functions blocks. If it returns kStatus_Success, the running hash
* has been updated (HASHCRYPT has processed the input data), so the memory at \p input pointer
* can be released back to system. The HASHCRYPT context buffer is updated with the running hash
* and with all necessary information to support possible context switch.
*
* @param base HASHCRYPT peripheral base address
* @param[in,out] ctx HASH context
* @param input Input data
* @param inputSize Size of input data in bytes
* @return Status of the hash update operation
*/
status_t HASHCRYPT_SHA_Update(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, const uint8_t *input, size_t inputSize);
/*!
* @brief Finalize hashing
*
* Outputs the final hash (computed by HASHCRYPT_HASH_Update()) and erases the context.
*
* @param base HASHCRYPT peripheral base address
* @param[in,out] ctx Input hash context
* @param[out] output Output hash data
* @param[in,out] outputSize Optional parameter (can be passed as NULL). On function entry, it specifies the size of
* output[] buffer. On function return, it stores the number of updated output bytes.
* @return Status of the hash finish operation
*/
status_t HASHCRYPT_SHA_Finish(HASHCRYPT_Type *base, hashcrypt_hash_ctx_t *ctx, uint8_t *output, size_t *outputSize);
/*!
*@}
*/ /* end of hashcrypt_driver_hash */
/*!
* @addtogroup hashcrypt_background_driver_hash
* @{
*/
/*!
* @brief Initializes the HASHCRYPT handle for background hashing.
*
* This function initializes the hash context for background hashing
* (Non-blocking) APIs. This is less typical interface to hash function, but can be used
* for parallel processing, when main CPU has something else to do.
* Example is digital signature RSASSA-PKCS1-V1_5-VERIFY((n,e),M,S) algorithm, where
* background hashing of M can be started, then CPU can compute S^e mod n
* (in parallel with background hashing) and once the digest becomes available,
* CPU can proceed to comparison of EM with EM'.
*
* @param base HASHCRYPT peripheral base address.
* @param[out] ctx Hash context.
* @param callback Callback function.
* @param userData User data (to be passed as an argument to callback function, once callback is invoked from isr).
*/
void HASHCRYPT_SHA_SetCallback(HASHCRYPT_Type *base,
hashcrypt_hash_ctx_t *ctx,
hashcrypt_callback_t callback,
void *userData);
/*!
* @brief Create running hash on given data.
*
* Configures the HASHCRYPT to compute new running hash as AHB master
* and returns immediately. HASHCRYPT AHB Master mode supports only aligned \p input
* address and can be called only once per continuous block of data. Every call to this function
* must be preceded with HASHCRYPT_SHA_Init() and finished with HASHCRYPT_SHA_Finish().
* Once callback function is invoked by HASHCRYPT isr, it should set a flag
* for the main application to finalize the hashing (padding) and to read out the final digest
* by calling HASHCRYPT_SHA_Finish().
*
* @param base HASHCRYPT peripheral base address
* @param ctx Specifies callback. Last incomplete 512-bit block of the input is copied into clear buffer for padding.
* @param input 32-bit word aligned pointer to Input data.
* @param inputSize Size of input data in bytes (must be word aligned)
* @return Status of the hash update operation.
*/
status_t HASHCRYPT_SHA_UpdateNonBlocking(HASHCRYPT_Type *base,
hashcrypt_hash_ctx_t *ctx,
const uint8_t *input,
size_t inputSize);
/*!
*@}
*/ /* end of hashcrypt_background_driver_hash */
#if defined(__cplusplus)
}
#endif
#endif /* _FSL_HASHCRYPT_H_ */

603
ext/hal/nxp/mcux/drivers/lpc/fsl_iap.c
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@ -3,456 +3,287 @@
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*
*/ */
#include "fsl_iap.h" #include "fsl_iap.h"
#include "fsl_iap_ffr.h"
#include "fsl_device_registers.h"
/* Component ID definition, used by tools. */ /* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID #ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.iap" #define FSL_COMPONENT_ID "platform.drivers.iap1"
#endif #endif
#define HZ_TO_KHZ_DIV 1000 /*!
* @addtogroup flash_driver_api
* @{
*/
/******************************************************************************* #define ROM_API_TREE ((uint32_t *)0x130010f0)
* Definitions #define BOOTLOADER_API_TREE_POINTER ((bootloader_tree_t *)ROM_API_TREE)
******************************************************************************/
/******************************************************************************* static uint32_t S_Version_minor = 0;
* Prototypes
******************************************************************************/
static status_t translate_iap_status(uint32_t status) typedef status_t (*EraseCommend_t)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
typedef status_t (*ProgramCommend_t)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
typedef status_t (*VerifyProgramCommend_t)(flash_config_t *config,
uint32_t start,
uint32_t lengthInBytes,
const uint8_t *expectedData,
uint32_t *failedAddress,
uint32_t *failedData);
typedef status_t (*FFR_CustomerPagesInit_t)(flash_config_t *config);
typedef status_t (*FFR_InfieldPageWrite_t)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
typedef status_t (*FFR_GetManufactureData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
typedef status_t (*FFR_GetRompatchData_t)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
/*
*!@brief Structure of version property.
*
*!@ingroup bl_core
*/
typedef union BootloaderVersion
{ {
/* Translate IAP return code to sdk status code */ struct
if (status == kStatus_Success)
{ {
return status; uint32_t bugfix : 8; /*!< bugfix version [7:0] */
} uint32_t minor : 8; /*!< minor version [15:8] */
else uint32_t major : 8; /*!< major version [23:16] */
{ uint32_t name : 8; /*!< name [31:24] */
return MAKE_STATUS(kStatusGroup_IAP, status); } B;
} uint32_t version; /*!< combined version numbers. */
} } standard_version_t;
/*! @brief Interface for the flash driver.*/
typedef struct FlashDriverInterface
{
standard_version_t version; /*!< flash driver API version number.*/
/*!< Flash driver.*/
status_t (*flash_init)(flash_config_t *config);
status_t (*flash_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
status_t (*flash_program)(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
status_t (*flash_verify_erase)(flash_config_t *config, uint32_t start, uint32_t lengthInBytes);
status_t (*flash_verify_program)(flash_config_t *config,
uint32_t start,
uint32_t lengthInBytes,
const uint8_t *expectedData,
uint32_t *failedAddress,
uint32_t *failedData);
status_t (*flash_get_property)(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
/*!< Flash FFR driver*/
status_t (*ffr_init)(flash_config_t *config);
status_t (*ffr_deinit)(flash_config_t *config);
status_t (*ffr_cust_factory_page_write)(flash_config_t *config, uint8_t *page_data, bool seal_part);
status_t (*ffr_get_uuid)(flash_config_t *config, uint8_t *uuid);
status_t (*ffr_get_customer_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
status_t (*ffr_keystore_write)(flash_config_t *config, ffr_key_store_t *pKeyStore);
status_t (*ffr_keystore_get_ac)(flash_config_t *config, uint8_t *pActivationCode);
status_t (*ffr_keystore_get_kc)(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
status_t (*ffr_infield_page_write)(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
status_t (*ffr_get_customer_infield_data)(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
} flash_driver_interface_t;
/*!
* @brief Root of the bootloader API tree.
*
* An instance of this struct resides in read-only memory in the bootloader. It
* provides a user application access to APIs exported by the bootloader.
*
* @note The order of existing fields must not be changed.
*/
typedef struct BootloaderTree
{
void (*runBootloader)(void *arg); /*!< Function to start the bootloader executing. */
standard_version_t bootloader_version; /*!< Bootloader version number. */
const char *copyright; /*!< Copyright string. */
const uint32_t *reserved; /*!< Do NOT use. */
const flash_driver_interface_t *flashDriver; /*!< Flash driver API. */
} bootloader_tree_t;
/******************************************************************************* /*******************************************************************************
* Variables * Variables
******************************************************************************/ ******************************************************************************/
/*! @brief Global pointer to the flash driver API table in ROM. */
flash_driver_interface_t *FLASH_API_TREE;
/*! Get pointer to flash driver API table in ROM. */
#define FLASH_API_TREE BOOTLOADER_API_TREE_POINTER->flashDriver
/******************************************************************************* /*******************************************************************************
* Code * Code
******************************************************************************/ ******************************************************************************/
/*! /*! See fsl_flash.h for documentation of this function. */
* brief Read part identification number. status_t FLASH_Init(flash_config_t *config)
* This function is used to read the part identification number.
*
* param partID Address to store the part identification number.
*
* retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ReadPartID(uint32_t *partID)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
config->modeConfig.sysFreqInMHz = kSysToFlashFreq_defaultInMHz;
command[0] = kIapCmd_IAP_ReadPartId; S_Version_minor = FLASH_API_TREE->version.B.minor;
iap_entry(command, result); return FLASH_API_TREE->flash_init(config);
*partID = result[1];
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash.h for documentation of this function. */
* brief Read boot code version number. status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key)
* This function is used to read the boot code version number.
*
* param bootCodeVersion Address to store the boot code version.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* note Boot code version is two 32-bit words. Word 0 is the major version, word 1 is the minor version.
*/
status_t IAP_ReadBootCodeVersion(uint32_t *bootCodeVersion)
{ {
uint32_t command[5], result[5]; if (S_Version_minor == 0)
{
command[0] = kIapCmd_IAP_Read_BootromVersion; EraseCommend_t EraseCommand =
iap_entry(command, result); (EraseCommend_t)(0x1300413b); /*!< get the flash erase api location adress int rom */
bootCodeVersion[0] = result[1]; return EraseCommand(config, start, lengthInBytes, key);
bootCodeVersion[1] = result[2]; }
else
return translate_iap_status(result[0]); {
assert(FLASH_API_TREE);
return FLASH_API_TREE->flash_erase(config, start, lengthInBytes, key);
}
} }
/*! /*! See fsl_flash.h for documentation of this function. */
* brief Reinvoke ISP status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes)
* This function is used to invoke the boot loader in ISP mode. It maps boot vectors and configures the
* peripherals for ISP.
*
* param ispTyoe ISP type selection.
* param status store the possible status
*
* retval #kStatus_IAP_ReinvokeISPConfig reinvoke configuration error.
* note The error response is returned if IAP is disabled, or if there is an invalid ISP type selection. When
* there is no error the call does not return, so there can be no status code.
*/
void IAP_ReinvokeISP(uint8_t ispType, uint32_t *status)
{ {
uint32_t command[5], result[5]; if (S_Version_minor == 0)
uint8_t ispParameterArray[8]; {
ProgramCommend_t ProgramCommend =
command[0] = kIapCmd_IAP_ReinvokeISP; (ProgramCommend_t)(0x1300419d); /*!< get the flash program api location adress in rom*/
memset(ispParameterArray, 0, sizeof(uint8_t) * 8); return ProgramCommend(config, start, src, lengthInBytes);
ispParameterArray[1] = ispType; }
ispParameterArray[7] = ispParameterArray[0] ^ ispParameterArray[1] ^ ispParameterArray[2] ^ ispParameterArray[3] ^ else
ispParameterArray[4] ^ ispParameterArray[5] ^ ispParameterArray[6]; {
command[1] = (uint32_t)ispParameterArray; assert(FLASH_API_TREE);
iap_entry(command, result); return FLASH_API_TREE->flash_program(config, start, src, lengthInBytes);
*status = translate_iap_status(result[0]); }
} }
/*! /*! See fsl_flash.h for documentation of this function. */
* brief Read unique identification. status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes)
* This function is used to read the unique id.
*
* param uniqueID store the uniqueID.
*
* retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ReadUniqueID(uint32_t *uniqueID)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->flash_verify_erase(config, start, lengthInBytes);
command[0] = kIapCmd_IAP_ReadUid;
iap_entry(command, result);
uniqueID[0] = result[1];
uniqueID[1] = result[2];
uniqueID[2] = result[3];
uniqueID[3] = result[4];
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash.h for documentation of this function. */
* brief Read factory settings. status_t FLASH_VerifyProgram(flash_config_t *config,
uint32_t start,
* This function reads the factory settings for calibration registers. uint32_t lengthInBytes,
* const uint8_t *expectedData,
* param dstRegAddr Address of the targeted calibration register. uint32_t *failedAddress,
* param factoryValue Store the factory value uint32_t *failedData)
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_ParamError Param0 is not one of the supported calibration registers
*/
status_t IAP_ReadFactorySettings(uint32_t dstRegAddr, uint32_t *factoryValue)
{ {
uint32_t command[5], result[5]; if (S_Version_minor == 0)
{
command[0] = kIapCmd_IAP_ReadFactorySettings; VerifyProgramCommend_t VerifyProgramCommend =
command[1] = dstRegAddr; (VerifyProgramCommend_t)(0x1300427d); /*!< get the flash verify program api location adress in rom*/
iap_entry(command, result); return VerifyProgramCommend(config, start, lengthInBytes, expectedData, failedAddress, failedData);
*factoryValue = result[1]; }
else
return translate_iap_status(result[0]); {
assert(FLASH_API_TREE);
return FLASH_API_TREE->flash_verify_program(config, start, lengthInBytes, expectedData, failedAddress,
failedData);
}
} }
/*! /*! See fsl_flash.h for documentation of this function.*/
* brief Prepare sector for write operation status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value)
* This function prepares sector(s) for write/erase operation. This function must be
* called before calling the IAP_CopyRamToFlash() or IAP_EraseSector() or
* IAP_ErasePage() function. The end sector must be greater than or equal to
* start sector number.
*
* param startSector Start sector number.
* param endSector End sector number.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number
* is greater than start sector number.
* retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/
status_t IAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->flash_get_property(config, whichProperty, value);
}
/********************************************************************************
* fsl_flash_ffr CODE
*******************************************************************************/
command[0] = kIapCmd_IAP_PrepareSectorforWrite; /*! See fsl_flash_ffr.h for documentation of this function. */
command[1] = startSector; status_t FFR_Init(flash_config_t *config)
command[2] = endSector; {
iap_entry(command, result); assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_init(config);
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* brief Copy RAM to flash. status_t FFR_Deinit(flash_config_t *config)
* This function programs the flash memory. Corresponding sectors must be prepared
* via IAP_PrepareSectorForWrite before calling calling this function. The addresses
* should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
*
* param dstAddr Destination flash address where data bytes are to be written.
* param srcAddr Source ram address from where data bytes are to be read.
* param numOfBytes Number of bytes to be written.
* param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
* rom IAP function.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_SrcAddrError Source address is not on word boundary.
* retval #kStatus_IAP_DstAddrError Destination address is not on a correct boundary.
* retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map.
* retval #kStatus_IAP_DstAddrNotMapped Destination address is not mapped in the memory map.
* retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value.
* retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed.
* retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/
status_t IAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_deinit(config);
command[0] = kIapCmd_IAP_CopyRamToFlash;
command[1] = dstAddr;
command[2] = (uint32_t)srcAddr;
command[3] = numOfBytes;
command[4] = systemCoreClock / HZ_TO_KHZ_DIV;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! status_t FFR_CustomerPagesInit(flash_config_t *config)
* brief Erase sector
* This function erases sector(s). The end sector must be greater than or equal to
* start sector number. IAP_PrepareSectorForWrite must be called before
* calling this function.
*
* param startSector Start sector number.
* param endSector End sector number.
* param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
* rom IAP function.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number
* is greater than start sector number.
* retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed.
* retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/
status_t IAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
FFR_CustomerPagesInit_t FFR_CustomerPagesInit_cmd = (FFR_CustomerPagesInit_t)(0x13004951);
command[0] = kIapCmd_IAP_EraseSector; return FFR_CustomerPagesInit_cmd(config);
command[1] = startSector;
command[2] = endSector;
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len)
* This function erases page(s). The end page must be greater than or equal to
* start page number. Corresponding sectors must be prepared via IAP_PrepareSectorForWrite
* before calling calling this function.
*
* param startPage Start page number
* param endPage End page number
* param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
* rom IAP function.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_InvalidSector Page number is invalid or end page number
* is greater than start page number
* retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed.
* retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/
status_t IAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock)
{ {
uint32_t command[5], result[5]; FFR_InfieldPageWrite_t FFR_InfieldPageWrite_cmd = (FFR_InfieldPageWrite_t)(0x13004a0b);
return FFR_InfieldPageWrite_cmd(config, page_data, valid_len);
command[0] = kIapCmd_IAP_ErasePage;
command[1] = startPage;
command[2] = endPage;
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* brief Blank check sector(s) status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part)
*
* Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to
* start sector number. It can be used to verify the sector eraseure after IAP_EraseSector call.
*
* param startSector : Start sector number. Must be greater than or equal to start sector number
* param endSector : End sector number
* retval #kStatus_IAP_Success One or more sectors are in erased state.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_SectorNotblank One or more sectors are not blank.
*/
status_t IAP_BlankCheckSector(uint32_t startSector, uint32_t endSector)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_cust_factory_page_write(config, page_data, seal_part);
command[0] = kIapCmd_IAP_BlankCheckSector;
command[1] = startSector;
command[2] = endSector;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* brief Compare memory contents of flash with ram. status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
* This function compares the contents of flash and ram. It can be used to verify the flash
* memory contents after IAP_CopyRamToFlash call.
*
* param dstAddr Destination flash address.
* param srcAddr Source ram address.
* param numOfBytes Number of bytes to be compared.
*
* retval #kStatus_IAP_Success Contents of flash and ram match.
* retval #kStatus_IAP_NoPower Flash memory block is powered down.
* retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* retval #kStatus_IAP_AddrError Address is not on word boundary.
* retval #kStatus_IAP_AddrNotMapped Address is not mapped in the memory map.
* retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value.
* retval #kStatus_IAP_CompareError Destination and source memory contents do not match.
*/
status_t IAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_get_customer_data(config, pData, offset, len);
command[0] = kIapCmd_IAP_Compare;
command[1] = dstAddr;
command[2] = (uint32_t)srcAddr;
command[3] = numOfBytes;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* brief Extended Read signature. status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore)
* This function calculates the signature value for one or more pages of on-chip flash memory.
*
* param startPage Start page number.
* param endPage End page number.
* param numOfStates Number of wait status.
* param signature Address to store the signature value.
*
* retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ExtendedFlashSignatureRead(uint32_t startPage, uint32_t endPage, uint32_t numOfState, uint32_t *signature)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_keystore_write(config, pKeyStore);
command[0] = kIapCmd_IAP_ExtendedReadSignature;
command[1] = startPage;
command[2] = endPage;
command[3] = numOfState;
command[4] = 0;
iap_entry(command, result);
signature[0] = result[4];
signature[1] = result[3];
signature[2] = result[2];
signature[3] = result[1];
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* @brief Read flash signature status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode)
*
* This funtion is used to obtain a 32-bit signature value of the entire flash memory.
*
* @param signature Address to store the 32-bit generated signature value.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ReadFlashSignature(uint32_t *signature)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_keystore_get_ac(config, pActivationCode);
command[0] = kIapCmd_IAP_ReadSignature;
iap_entry(command, result);
*signature = result[1];
return translate_iap_status(result[0]);
} }
/*! /*! See fsl_flash_ffr.h for documentation of this function. */
* brief Read EEPROM page. status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex)
* This function is used to read given page of EEPROM into the memory provided.
*
* param pageNumber EEPROM page number.
* param dstAddr Memory address to store the value read from EEPROM.
* param systemCoreClock Current core clock frequency in kHz.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_InvalidSector Sector number is invalid.
* retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map.
*
* note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for
* EEPROM]
*/
status_t IAP_ReadEEPROMPage(uint32_t pageNumber, uint32_t *dstAddr, uint32_t systemCoreClock)
{ {
uint32_t command[5], result[5]; assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_keystore_get_kc(config, pKeyCode, keyIndex);
command[0] = kIapCmd_IAP_ReadEEPROMPage;
command[1] = pageNumber;
command[2] = (uint32_t)dstAddr;
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/*! status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
* brief Write EEPROM page.
* This function is used to write given data in the provided memory to a page of EEPROM.
*
* param pageNumber EEPROM page number.
* param srcAddr Memory address holding data to be stored on to EEPROM page.
* param systemCoreClock Current core clock frequency in kHz.
*
* retval #kStatus_IAP_Success Api was executed successfully.
* retval #kStatus_IAP_InvalidSector Sector number is invalid.
* retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map.
*
* note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for
* EEPROM]
*/
status_t IAP_WriteEEPROMPage(uint32_t pageNumber, uint32_t *srcAddr, uint32_t systemCoreClock)
{ {
uint32_t command[5], result[5]; FFR_GetRompatchData_t FFR_GetRompatchData_cmd = (FFR_GetRompatchData_t)(0x13004db3);
return FFR_GetRompatchData_cmd(config, pData, offset, len);
command[0] = kIapCmd_IAP_WriteEEPROMPage;
command[1] = pageNumber;
command[2] = (uint32_t)srcAddr;
command[3] = systemCoreClock / HZ_TO_KHZ_DIV;
iap_entry(command, result);
return translate_iap_status(result[0]);
} }
/* APIs to access NMPA pages */
status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
{
FFR_GetManufactureData_t FFR_GetManufactureData_cmd = (FFR_GetManufactureData_t)(0x13004e15);
return FFR_GetManufactureData_cmd(config, pData, offset, len);
}
/*! See fsl_flash_ffr.h for documentation of this function. */
status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid)
{
assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_get_uuid(config, uuid);
}
/*! See fsl_flash_ffr.h for documentation of this function. */
status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len)
{
assert(FLASH_API_TREE);
return FLASH_API_TREE->ffr_get_customer_infield_data(config, pData, offset, len);
}
/*! @}*/
/********************************************************************************
* EOF
*******************************************************************************/

720
ext/hal/nxp/mcux/drivers/lpc/fsl_iap.h
View file

@ -3,15 +3,15 @@
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*
*/ */
#ifndef _FSL_IAP_H_ #ifndef __FSL_IAP_H_
#define _FSL_IAP_H_ #define __FSL_IAP_H_
#include "fsl_common.h" #include "fsl_common.h"
/*! /*!
* @addtogroup IAP_driver * @addtogroup iap_driver
* @{ * @{
*/ */
@ -20,77 +20,294 @@
/******************************************************************************* /*******************************************************************************
* Definitions * Definitions
******************************************************************************/ ******************************************************************************/
/*!
* @name Flash version
* @{
*/
/*! @brief Constructs the version number for drivers. */
#if !defined(MAKE_VERSION)
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
#endif
/*! @name Driver version */ /*! @brief Flash driver version for SDK*/
/*@{*/ #define FSL_FLASH_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
#define FSL_IAP_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
/*@}*/ /*! @brief Flash driver version for ROM*/
enum _flash_driver_version_constants
{
kFLASH_DriverVersionName = 'F', /*!< Flash driver version name.*/
kFLASH_DriverVersionMajor = 2, /*!< Major flash driver version.*/
kFLASH_DriverVersionMinor = 0, /*!< Minor flash driver version.*/
kFLASH_DriverVersionBugfix = 0 /*!< Bugfix for flash driver version.*/
};
/*@}*/
/*! /*!
* @brief iap status codes. * @name Flash configuration
* @{
*/ */
enum _iap_status /*! @brief Flash IP Type. */
#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC)
#define FSL_FEATURE_FLASH_IP_IS_C040HD_ATFC (1)
#endif
#if !defined(FSL_FEATURE_FLASH_IP_IS_C040HD_FC)
#define FSL_FEATURE_FLASH_IP_IS_C040HD_FC (0)
#endif
/*@}*/
/*!
* @name Flash status
* @{
*/
/*! @brief Flash driver status group. */
#if defined(kStatusGroup_FlashDriver)
#define kStatusGroupGeneric kStatusGroup_Generic
#define kStatusGroupFlashDriver kStatusGroup_FlashDriver
#elif defined(kStatusGroup_FLASHIAP)
#define kStatusGroupGeneric kStatusGroup_Generic
#define kStatusGroupFlashDriver kStatusGroup_FLASH
#else
#define kStatusGroupGeneric 0
#define kStatusGroupFlashDriver 1
#endif
/*! @brief Constructs a status code value from a group and a code number. */
#if !defined(MAKE_STATUS)
#define MAKE_STATUS(group, code) ((((group)*100) + (code)))
#endif
/*!
* @brief Flash driver status codes.
*/
enum _flash_status
{ {
kStatus_IAP_Success = kStatus_Success, /*!< Api is executed successfully */ kStatus_FLASH_Success = MAKE_STATUS(kStatusGroupGeneric, 0), /*!< API is executed successfully*/
kStatus_IAP_InvalidCommand = MAKE_STATUS(kStatusGroup_IAP, 1U), /*!< Invalid command */ kStatus_FLASH_InvalidArgument = MAKE_STATUS(kStatusGroupGeneric, 4), /*!< Invalid argument*/
kStatus_IAP_SrcAddrError = MAKE_STATUS(kStatusGroup_IAP, 2U), /*!< Source address is not on word boundary */ kStatus_FLASH_SizeError = MAKE_STATUS(kStatusGroupFlashDriver, 0), /*!< Error size*/
kStatus_IAP_DstAddrError = kStatus_FLASH_AlignmentError =
MAKE_STATUS(kStatusGroup_IAP, 3U), /*!< Destination address is not on a correct boundary */ MAKE_STATUS(kStatusGroupFlashDriver, 1), /*!< Parameter is not aligned with the specified baseline*/
kStatus_IAP_SrcAddrNotMapped = kStatus_FLASH_AddressError = MAKE_STATUS(kStatusGroupFlashDriver, 2), /*!< Address is out of range */
MAKE_STATUS(kStatusGroup_IAP, 4U), /*!< Source address is not mapped in the memory map */ kStatus_FLASH_AccessError =
kStatus_IAP_DstAddrNotMapped = MAKE_STATUS(kStatusGroupFlashDriver, 3), /*!< Invalid instruction codes and out-of bound addresses */
MAKE_STATUS(kStatusGroup_IAP, 5U), /*!< Destination address is not mapped in the memory map */ kStatus_FLASH_ProtectionViolation = MAKE_STATUS(
kStatus_IAP_CountError = kStatusGroupFlashDriver, 4), /*!< The program/erase operation is requested to execute on protected areas */
MAKE_STATUS(kStatusGroup_IAP, 6U), /*!< Byte count is not multiple of 4 or is not a permitted value */ kStatus_FLASH_CommandFailure =
kStatus_IAP_InvalidSector = MAKE_STATUS( MAKE_STATUS(kStatusGroupFlashDriver, 5), /*!< Run-time error during command execution. */
kStatusGroup_IAP, 7), /*!< Sector number is invalid or end sector number is greater than start sector number */ kStatus_FLASH_UnknownProperty = MAKE_STATUS(kStatusGroupFlashDriver, 6), /*!< Unknown property.*/
kStatus_IAP_SectorNotblank = MAKE_STATUS(kStatusGroup_IAP, 8U), /*!< One or more sectors are not blank */ kStatus_FLASH_EraseKeyError = MAKE_STATUS(kStatusGroupFlashDriver, 7), /*!< API erase key is invalid.*/
kStatus_IAP_NotPrepared = kStatus_FLASH_RegionExecuteOnly =
MAKE_STATUS(kStatusGroup_IAP, 9U), /*!< Command to prepare sector for write operation was not executed */ MAKE_STATUS(kStatusGroupFlashDriver, 8), /*!< The current region is execute-only.*/
kStatus_IAP_CompareError = kStatus_FLASH_ExecuteInRamFunctionNotReady =
MAKE_STATUS(kStatusGroup_IAP, 10U), /*!< Destination and source memory contents do not match */ MAKE_STATUS(kStatusGroupFlashDriver, 9), /*!< Execute-in-RAM function is not available.*/
kStatus_IAP_Busy = MAKE_STATUS(kStatusGroup_IAP, 11U), /*!< Flash programming hardware interface is busy */
kStatus_IAP_ParamError = kStatus_FLASH_CommandNotSupported = MAKE_STATUS(kStatusGroupFlashDriver, 11), /*!< Flash API is not supported.*/
MAKE_STATUS(kStatusGroup_IAP, 12U), /*!< Insufficient number of parameters or invalid parameter */ kStatus_FLASH_ReadOnlyProperty = MAKE_STATUS(kStatusGroupFlashDriver, 12), /*!< The flash property is read-only.*/
kStatus_IAP_AddrError = MAKE_STATUS(kStatusGroup_IAP, 13U), /*!< Address is not on word boundary */ kStatus_FLASH_InvalidPropertyValue =
kStatus_IAP_AddrNotMapped = MAKE_STATUS(kStatusGroup_IAP, 14U), /*!< Address is not mapped in the memory map */ MAKE_STATUS(kStatusGroupFlashDriver, 13), /*!< The flash property value is out of range.*/
kStatus_IAP_NoPower = MAKE_STATUS(kStatusGroup_IAP, 24U), /*!< Flash memory block is powered down */ kStatus_FLASH_InvalidSpeculationOption =
kStatus_IAP_NoClock = MAKE_STATUS(kStatusGroup_IAP, 27U), /*!< Flash memory block or controller is not clocked */ MAKE_STATUS(kStatusGroupFlashDriver, 14), /*!< The option of flash prefetch speculation is invalid.*/
kStatus_IAP_ReinvokeISPConfig = MAKE_STATUS(kStatusGroup_IAP, 0x1CU), /*!< Reinvoke configuration error */ kStatus_FLASH_EccError = MAKE_STATUS(kStatusGroupFlashDriver,
0x10), /*!< A correctable or uncorrectable error during command execution. */
kStatus_FLASH_CompareError =
MAKE_STATUS(kStatusGroupFlashDriver, 0x11), /*!< Destination and source memory contents do not match. */
kStatus_FLASH_RegulationLoss = MAKE_STATUS(kStatusGroupFlashDriver, 0x12), /*!< A loss of regulation during read. */
kStatus_FLASH_InvalidWaitStateCycles =
MAKE_STATUS(kStatusGroupFlashDriver, 0x13), /*!< The wait state cycle set to r/w mode is invalid. */
kStatus_FLASH_OutOfDateCfpaPage =
MAKE_STATUS(kStatusGroupFlashDriver, 0x20), /*!< CFPA page version is out of date. */
kStatus_FLASH_BlankIfrPageData = MAKE_STATUS(kStatusGroupFlashDriver, 0x21), /*!< Blank page cannnot be read. */
kStatus_FLASH_EncryptedRegionsEraseNotDoneAtOnce =
MAKE_STATUS(kStatusGroupFlashDriver, 0x22), /*!< Encrypted flash subregions are not erased at once. */
kStatus_FLASH_ProgramVerificationNotAllowed = MAKE_STATUS(
kStatusGroupFlashDriver, 0x23), /*!< Program verification is not allowed when the encryption is enabled. */
kStatus_FLASH_HashCheckError =
MAKE_STATUS(kStatusGroupFlashDriver, 0x24), /*!< Hash check of page data is failed. */
kStatus_FLASH_SealedFfrRegion = MAKE_STATUS(kStatusGroupFlashDriver, 0x25), /*!< The FFR region is sealed. */
kStatus_FLASH_FfrRegionWriteBroken = MAKE_STATUS(
kStatusGroupFlashDriver, 0x26), /*!< The FFR Spec region is not allowed to be written discontinuously. */
kStatus_FLASH_NmpaAccessNotAllowed =
MAKE_STATUS(kStatusGroupFlashDriver, 0x27), /*!< The NMPA region is not allowed to be read/written/erased. */
kStatus_FLASH_CmpaCfgDirectEraseNotAllowed =
MAKE_STATUS(kStatusGroupFlashDriver, 0x28), /*!< The CMPA Cfg region is not allowed to be erased directly. */
kStatus_FLASH_FfrBankIsLocked = MAKE_STATUS(kStatusGroupFlashDriver, 0x29), /*!< The FFR bank region is locked. */
};
/*@}*/
/*!
* @name Flash API key
* @{
*/
/*! @brief Constructs the four character code for the Flash driver API key. */
#if !defined(FOUR_CHAR_CODE)
#define FOUR_CHAR_CODE(a, b, c, d) (((d) << 24) | ((c) << 16) | ((b) << 8) | ((a)))
#endif
/*!
* @brief Enumeration for Flash driver API keys.
*
* @note The resulting value is built with a byte order such that the string
* being readable in expected order when viewed in a hex editor, if the value
* is treated as a 32-bit little endian value.
*/
enum _flash_driver_api_keys
{
kFLASH_ApiEraseKey = FOUR_CHAR_CODE('l', 'f', 'e', 'k') /*!< Key value used to validate all flash erase APIs.*/
};
/*@}*/
/*!
* @brief Enumeration for various flash properties.
*/
typedef enum _flash_property_tag
{
kFLASH_PropertyPflashSectorSize = 0x00U, /*!< Pflash sector size property.*/
kFLASH_PropertyPflashTotalSize = 0x01U, /*!< Pflash total size property.*/
kFLASH_PropertyPflashBlockSize = 0x02U, /*!< Pflash block size property.*/
kFLASH_PropertyPflashBlockCount = 0x03U, /*!< Pflash block count property.*/
kFLASH_PropertyPflashBlockBaseAddr = 0x04U, /*!< Pflash block base address property.*/
kFLASH_PropertyPflashPageSize = 0x30U, /*!< Pflash page size property.*/
kFLASH_PropertyPflashSystemFreq = 0x31U, /*!< System Frequency System Frequency.*/
kFLASH_PropertyFfrSectorSize = 0x40U, /*!< FFR sector size property.*/
kFLASH_PropertyFfrTotalSize = 0x41U, /*!< FFR total size property.*/
kFLASH_PropertyFfrBlockBaseAddr = 0x42U, /*!< FFR block base address property.*/
kFLASH_PropertyFfrPageSize = 0x43U, /*!< FFR page size property.*/
} flash_property_tag_t;
/*!
* @brief Enumeration for flash max pages to erase.
*/
enum _flash_max_erase_page_value
{
kFLASH_MaxPagesToErase = 100U /*!< The max value in pages to erase. */
};
enum _flash_freq_tag
{
kSysToFlashFreq_lowInMHz = 12u,
kSysToFlashFreq_defaultInMHz = 96u,
kSysToFlashFreq_100MHz = 100u
}; };
/*! /*!
* @brief iap command codes. * @brief Enumeration for flash alignment property.
*/ */
enum _iap_commands enum _flash_alignment_property
{ {
kIapCmd_IAP_ReadFactorySettings = 40U, /*!< Read the factory settings */ kFLASH_AlignementUnitVerifyErase = 4, /*!< The alignment unit in bytes used for verify erase operation.*/
kIapCmd_IAP_PrepareSectorforWrite = 50U, /*!< Prepare Sector for write */ kFLASH_AlignementUnitProgram = 512, /*!< The alignment unit in bytes used for program operation.*/
kIapCmd_IAP_CopyRamToFlash = 51U, /*!< Copy RAM to flash */ /*kFLASH_AlignementUnitVerifyProgram = 4,*/ /*!< The alignment unit in bytes used for verify program operation.*/
kIapCmd_IAP_EraseSector = 52U, /*!< Erase Sector */ kFLASH_AlignementUnitSingleWordRead = 16 /*!< The alignment unit in bytes used for SingleWordRead command.*/
kIapCmd_IAP_BlankCheckSector = 53U, /*!< Blank check sector */
kIapCmd_IAP_ReadPartId = 54U, /*!< Read part id */
kIapCmd_IAP_Read_BootromVersion = 55U, /*!< Read bootrom version */
kIapCmd_IAP_Compare = 56U, /*!< Compare */
kIapCmd_IAP_ReinvokeISP = 57U, /*!< Reinvoke ISP */
kIapCmd_IAP_ReadUid = 58U, /*!< Read Uid */
kIapCmd_IAP_ErasePage = 59U, /*!< Erase Page */
kIapCmd_IAP_ReadSignature = 70U, /*!< Read Signature */
kIapCmd_IAP_ExtendedReadSignature = 73U, /*!< Extended Read Signature */
kIapCmd_IAP_ReadEEPROMPage = 80U, /*!< Read EEPROM page */
kIapCmd_IAP_WriteEEPROMPage = 81U /*!< Write EEPROM page */
}; };
/******************************************************************************* /*!
* Prototypes * @brief Enumeration for flash read ecc option
******************************************************************************/ */
enum _flash_read_ecc_option
{
kFLASH_ReadWithEccOn = 0, /*! ECC is on */
kFLASH_ReadWithEccOff = 1, /*! ECC is off */
};
/*! @brief IAP_ENTRY API function type */ /*!
typedef void (*IAP_ENTRY_T)(uint32_t cmd[], uint32_t stat[]); * @brief Enumeration for flash read margin option
*/
enum _flash_read_margin_option
{
kFLASH_ReadMarginNormal = 0, /*!< Normal read */
kFLASH_ReadMarginVsProgram = 1, /*!< Margin vs. program */
kFLASH_ReadMarginVsErase = 2, /*!< Margin vs. erase */
kFLASH_ReadMarginIllegalBitCombination = 3 /*!< Illegal bit combination */
};
/******************************************************************************* /*!
* Variables * @brief Enumeration for flash read dmacc option
******************************************************************************/ */
enum _flash_read_dmacc_option
{
kFLASH_ReadDmaccDisabled = 0, /*!< Memory word */
kFLASH_ReadDmaccEnabled = 1, /*!< DMACC word */
};
/*!
* @brief Enumeration for flash ramp control option
*/
enum _flash_ramp_control_option
{
kFLASH_RampControlDivisionFactorReserved = 0, /*!< Reserved */
kFLASH_RampControlDivisionFactor256 = 1, /*!< clk48mhz / 256 = 187.5KHz */
kFLASH_RampControlDivisionFactor128 = 2, /*!< clk48mhz / 128 = 375KHz */
kFLASH_RampControlDivisionFactor64 = 3 /*!< clk48mhz / 64 = 750KHz */
};
/*! @brief Flash ECC log info. */
typedef struct _flash_ecc_log
{
uint32_t firstEccEventAddress;
uint32_t eccErrorCount;
uint32_t eccCorrectionCount;
uint32_t reserved;
} flash_ecc_log_t;
/*! @brief Flash controller paramter config. */
typedef struct _flash_mode_config
{
uint32_t sysFreqInMHz;
/* ReadSingleWord parameter. */
struct
{
uint8_t readWithEccOff : 1;
uint8_t readMarginLevel : 2;
uint8_t readDmaccWord : 1;
uint8_t reserved0 : 4;
uint8_t reserved1[3];
} readSingleWord;
/* SetWriteMode parameter. */
struct
{
uint8_t programRampControl;
uint8_t eraseRampControl;
uint8_t reserved[2];
} setWriteMode;
/* SetReadMode parameter. */
struct
{
uint16_t readInterfaceTimingTrim;
uint16_t readControllerTimingTrim;
uint8_t readWaitStates;
uint8_t reserved[3];
} setReadMode;
} flash_mode_config_t;
/*! @brief Flash controller paramter config. */
typedef struct _flash_ffr_config
{
uint32_t ffrBlockBase;
uint32_t ffrTotalSize;
uint32_t ffrPageSize;
uint32_t cfpaPageVersion;
uint32_t cfpaPageOffset;
} flash_ffr_config_t;
/*! @brief Flash driver state information.
*
* An instance of this structure is allocated by the user of the flash driver and
* passed into each of the driver APIs.
*/
typedef struct _flash_config
{
uint32_t PFlashBlockBase; /*!< A base address of the first PFlash block */
uint32_t PFlashTotalSize; /*!< The size of the combined PFlash block. */
uint32_t PFlashBlockCount; /*!< A number of PFlash blocks. */
uint32_t PFlashPageSize; /*!< The size in bytes of a page of PFlash. */
uint32_t PFlashSectorSize; /*!< The size in bytes of a sector of PFlash. */
flash_ffr_config_t ffrConfig;
flash_mode_config_t modeConfig;
} flash_config_t;
/******************************************************************************* /*******************************************************************************
* API * API
@ -101,286 +318,199 @@ extern "C" {
#endif #endif
/*! /*!
* @brief IAP_ENTRY API function type * @name Initialization
* * @{
* Wrapper for rom iap call
*
* @param cmd_param IAP command and relevant parameter array.
* @param status_result IAP status result array.
*
* @retval None. Status/Result is returned via status_result array.
*/ */
static inline void iap_entry(uint32_t *cmd_param, uint32_t *status_result)
{
__disable_irq();
((IAP_ENTRY_T)FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION)(cmd_param, status_result);
__enable_irq();
}
/*! /*!
* @brief Read part identification number. * @brief Initializes the global flash properties structure members.
* This function is used to read the part identification number.
* *
* @param partID Address to store the part identification number. * This function checks and initializes the Flash module for the other Flash APIs.
* *
* @retval #kStatus_IAP_Success Api was executed successfully. * @param config Pointer to the storage for the driver runtime state.
*
* @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
*/ */
status_t IAP_ReadPartID(uint32_t *partID); status_t FLASH_Init(flash_config_t *config);
/*@}*/
/*! /*!
* @brief Read boot code version number. * @name Erasing
* @{
* This function is used to read the boot code version number.
*
* @param bootCodeVersion Address to store the boot code version.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
* @note Boot code version is two 32-bit words. Word 0 is the major version, word 1 is the minor version.
*/ */
status_t IAP_ReadBootCodeVersion(uint32_t *bootCodeVersion);
/*! /*!
* @brief Reinvoke ISP * @brief Erases the flash sectors encompassed by parameters passed into function.
* This function is used to invoke the boot loader in ISP mode. It maps boot vectors and configures the
* peripherals for ISP.
* *
* @param ispTyoe ISP type selection. * This function erases the appropriate number of flash sectors based on the
* @param status store the possible status * desired start address and length.
* *
* @retval #kStatus_IAP_ReinvokeISPConfig reinvoke configuration error. * @param config The pointer to the storage for the driver runtime state.
* @param start The start address of the desired flash memory to be erased.
* @note The error response is returned if IAP is disabled, or if there is an invalid ISP type selection. When * The start address does not need to be sector-aligned.
* there is no error the call does not return, so there can be no status code. * @param lengthInBytes The length, given in bytes (not words or long-words)
* to be erased. Must be word-aligned.
* @param key The value used to validate all flash erase APIs.
*
* @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_AlignmentError The parameter is not aligned with the specified baseline.
* @retval #kStatus_FLASH_AddressError The address is out of range.
* @retval #kStatus_FLASH_EraseKeyError The API erase key is invalid.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
*/ */
void IAP_ReinvokeISP(uint8_t ispType, uint32_t *status); status_t FLASH_Erase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes, uint32_t key);
/*@}*/
/*! /*!
* @brief Read unique identification. * @name Programming
* @{
* This function is used to read the unique id.
*
* @param uniqueID store the uniqueID.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
*/ */
status_t IAP_ReadUniqueID(uint32_t *uniqueID);
#if (defined(FSL_FEATURE_IAP_HAS_READ_FACTORY_SETTINGS_FUNCTION) && \
(FSL_FEATURE_IAP_HAS_READ_FACTORY_SETTINGS_FUNCTION == 1))
/*!
* @brief Read factory settings.
* This function reads the factory settings for calibration registers.
*
* @param dstRegAddr Address of the targeted calibration register.
* @param factoryValue Store the factory value
*
* @retval #kStatus_IAP_Success Api was executed successfully.
* @retval #kStatus_IAP_ParamError Param0 is not one of the supported calibration registers
*/
status_t IAP_ReadFactorySettings(uint32_t dstRegAddr, uint32_t *factoryValue);
#endif
#if (defined(FSL_FEATURE_IAP_HAS_FLASH_FUNCTION) && (FSL_FEATURE_IAP_HAS_FLASH_FUNCTION == 1))
/*!
* @brief Prepare sector for write operation
* This function prepares sector(s) for write/erase operation. This function must be
* called before calling the IAP_CopyRamToFlash() or IAP_EraseSector() or
* IAP_ErasePage() function. The end sector must be greater than or equal to
* start sector number.
*
* @param startSector Start sector number.
* @param endSector End sector number.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
* @retval #kStatus_IAP_NoPower Flash memory block is powered down.
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* @retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number
* is greater than start sector number.
* @retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/
status_t IAP_PrepareSectorForWrite(uint32_t startSector, uint32_t endSector);
/*! /*!
* @brief Copy RAM to flash. * @brief Programs flash with data at locations passed in through parameters.
* This function programs the flash memory. Corresponding sectors must be prepared
* via IAP_PrepareSectorForWrite before calling calling this function. The addresses
* should be a 256 byte boundary and the number of bytes should be 256 | 512 | 1024 | 4096.
* *
* @param dstAddr Destination flash address where data bytes are to be written. * This function programs the flash memory with the desired data for a given
* @param srcAddr Source ram address from where data bytes are to be read. * flash area as determined by the start address and the length.
* @param numOfBytes Number of bytes to be written.
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
* rom IAP function.
* *
* @retval #kStatus_IAP_Success Api was executed successfully. * @param config A pointer to the storage for the driver runtime state.
* @retval #kStatus_IAP_NoPower Flash memory block is powered down. * @param start The start address of the desired flash memory to be programmed. Must be
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. * word-aligned.
* @retval #kStatus_IAP_SrcAddrError Source address is not on word boundary. * @param src A pointer to the source buffer of data that is to be programmed
* @retval #kStatus_IAP_DstAddrError Destination address is not on a correct boundary. * into the flash.
* @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. * @param lengthInBytes The length, given in bytes (not words or long-words),
* @retval #kStatus_IAP_DstAddrNotMapped Destination address is not mapped in the memory map. * to be programmed. Must be word-aligned.
* @retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value. *
* @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. * @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with the specified baseline.
* @retval #kStatus_FLASH_AddressError Address is out of range.
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
*/ */
status_t IAP_CopyRamToFlash(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes, uint32_t systemCoreClock); status_t FLASH_Program(flash_config_t *config, uint32_t start, uint8_t *src, uint32_t lengthInBytes);
/*@}*/
/*! /*!
* @brief Erase sector * @name Verification
* @{
* This function erases sector(s). The end sector must be greater than or equal to
* start sector number. IAP_PrepareSectorForWrite must be called before
* calling this function.
*
* @param startSector Start sector number.
* @param endSector End sector number.
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the
* rom IAP function.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
* @retval #kStatus_IAP_NoPower Flash memory block is powered down.
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* @retval #kStatus_IAP_InvalidSector Sector number is invalid or end sector number
* is greater than start sector number.
* @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed.
* @retval #kStatus_IAP_Busy Flash programming hardware interface is busy.
*/ */
status_t IAP_EraseSector(uint32_t startSector, uint32_t endSector, uint32_t systemCoreClock);
/*! /*!
* @brief Verifies an erasure of the desired flash area at a specified margin level.
* This function erases page(s). The end page must be greater than or equal to
* start page number. Corresponding sectors must be prepared via IAP_PrepareSectorForWrite
* before calling calling this function.
* *
* @param startPage Start page number * This function checks the appropriate number of flash sectors based on
* @param endPage End page number * the desired start address and length to check whether the flash is erased
* @param systemCoreClock SystemCoreClock in Hz. It is converted to KHz before calling the * to the specified read margin level.
* rom IAP function.
* *
* @retval #kStatus_IAP_Success Api was executed successfully. * @param config A pointer to the storage for the driver runtime state.
* @retval #kStatus_IAP_NoPower Flash memory block is powered down. * @param start The start address of the desired flash memory to be verified.
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. * The start address does not need to be sector-aligned but must be word-aligned.
* @retval #kStatus_IAP_InvalidSector Page number is invalid or end page number * @param lengthInBytes The length, given in bytes (not words or long-words),
* is greater than start page number * to be verified. Must be word-aligned.
* @retval #kStatus_IAP_NotPrepared Command to prepare sector for write operation was not executed. * @param margin Read margin choice.
* @retval #kStatus_IAP_Busy Flash programming hardware interface is busy. *
* @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
* @retval #kStatus_FLASH_AddressError Address is out of range.
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
*/ */
status_t IAP_ErasePage(uint32_t startPage, uint32_t endPage, uint32_t systemCoreClock); status_t FLASH_VerifyErase(flash_config_t *config, uint32_t start, uint32_t lengthInBytes);
/*! /*!
* @brief Blank check sector(s) * @brief Verifies programming of the desired flash area at a specified margin level.
* *
* Blank check single or multiples sectors of flash memory. The end sector must be greater than or equal to * This function verifies the data programed in the flash memory using the
* start sector number. It can be used to verify the sector eraseure after IAP_EraseSector call. * Flash Program Check Command and compares it to the expected data for a given
* flash area as determined by the start address and length.
* *
* @param startSector : Start sector number. Must be greater than or equal to start sector number * @param config A pointer to the storage for the driver runtime state.
* @param endSector : End sector number * @param start The start address of the desired flash memory to be verified. Must be word-aligned.
* @retval #kStatus_IAP_Success One or more sectors are in erased state. * @param lengthInBytes The length, given in bytes (not words or long-words),
* @retval #kStatus_IAP_NoPower Flash memory block is powered down. * to be verified. Must be word-aligned.
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked. * @param expectedData A pointer to the expected data that is to be
* @retval #kStatus_IAP_SectorNotblank One or more sectors are not blank. * verified against.
* @param margin Read margin choice.
* @param failedAddress A pointer to the returned failing address.
* @param failedData A pointer to the returned failing data. Some derivatives do
* not include failed data as part of the FCCOBx registers. In this
* case, zeros are returned upon failure.
*
* @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_AlignmentError Parameter is not aligned with specified baseline.
* @retval #kStatus_FLASH_AddressError Address is out of range.
* @retval #kStatus_FLASH_AccessError Invalid instruction codes and out-of bounds addresses.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandFailure Run-time error during the command execution.
* @retval #kStatus_FLASH_CommandNotSupported Flash API is not supported.
* @retval #kStatus_FLASH_EccError A correctable or uncorrectable error during command execution.
*/ */
status_t IAP_BlankCheckSector(uint32_t startSector, uint32_t endSector); status_t FLASH_VerifyProgram(flash_config_t *config,
uint32_t start,
uint32_t lengthInBytes,
const uint8_t *expectedData,
uint32_t *failedAddress,
uint32_t *failedData);
/*@}*/
/*! /*!
* @brief Compare memory contents of flash with ram. * @name Properties
* @{
* This function compares the contents of flash and ram. It can be used to verify the flash
* memory contents after IAP_CopyRamToFlash call.
*
* @param dstAddr Destination flash address.
* @param srcAddr Source ram address.
* @param numOfBytes Number of bytes to be compared.
*
* @retval #kStatus_IAP_Success Contents of flash and ram match.
* @retval #kStatus_IAP_NoPower Flash memory block is powered down.
* @retval #kStatus_IAP_NoClock Flash memory block or controller is not clocked.
* @retval #kStatus_IAP_AddrError Address is not on word boundary.
* @retval #kStatus_IAP_AddrNotMapped Address is not mapped in the memory map.
* @retval #kStatus_IAP_CountError Byte count is not multiple of 4 or is not a permitted value.
* @retval #kStatus_IAP_CompareError Destination and source memory contents do not match.
*/ */
status_t IAP_Compare(uint32_t dstAddr, uint32_t *srcAddr, uint32_t numOfBytes);
#if defined(FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ) && FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ
/*!
* @brief Extended Read signature.
* This function calculates the signature value for one or more pages of on-chip flash memory.
*
* @param startPage Start page number.
* @param endPage End page number.
* @param numOfStates Number of wait status.
* @param signature Address to store the signature value.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ExtendedFlashSignatureRead(uint32_t startPage, uint32_t endPage, uint32_t numOfState, uint32_t *signature);
#endif /* FSL_FEATURE_IAP_HAS_FLASH_EXTENDED_SIGNATURE_READ */
#if defined(FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ) && FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ
/*!
* @brief Read flash signature
*
* This funtion is used to obtain a 32-bit signature value of the entire flash memory.
*
* @param signature Address to store the 32-bit generated signature value.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
*/
status_t IAP_ReadFlashSignature(uint32_t *signature);
#endif /* FSL_FEATURE_IAP_HAS_FLASH_SIGNATURE_READ */
#endif /* FSL_FEATURE_IAP_HAS_FLASH_FUNCTION */
#if (defined(FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION) && (FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION == 1))
/*!
* @brief Read EEPROM page.
* This function is used to read given page of EEPROM into the memory provided.
*
* @param pageNumber EEPROM page number.
* @param dstAddr Memory address to store the value read from EEPROM.
* @param systemCoreClock Current core clock frequency in kHz.
*
* @retval #kStatus_IAP_Success Api was executed successfully.
* @retval #kStatus_IAP_InvalidSector Sector number is invalid.
* @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map.
*
* @note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for
* EEPROM]
*/
status_t IAP_ReadEEPROMPage(uint32_t pageNumber, uint32_t *dstAddr, uint32_t systemCoreClock);
/*! /*!
* @brief Write EEPROM page. * @brief Returns the desired flash property.
* This function is used to write given data in the provided memory to a page of EEPROM.
* *
* @param pageNumber EEPROM page number. * @param config A pointer to the storage for the driver runtime state.
* @param srcAddr Memory address holding data to be stored on to EEPROM page. * @param whichProperty The desired property from the list of properties in
* @param systemCoreClock Current core clock frequency in kHz. * enum flash_property_tag_t
* @param value A pointer to the value returned for the desired flash property.
* *
* @retval #kStatus_IAP_Success Api was executed successfully. * @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_IAP_InvalidSector Sector number is invalid. * @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_IAP_SrcAddrNotMapped Source address is not mapped in the memory map. * @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
*
* @note Value 0xFFFFFFFF of systemCoreClock will retain the timing and clock settings for
* EEPROM]
*/ */
status_t IAP_WriteEEPROMPage(uint32_t pageNumber, uint32_t *srcAddr, uint32_t systemCoreClock); status_t FLASH_GetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t *value);
#endif /* FSL_FEATURE_IAP_HAS_EEPROM_FUNCTION */
/*!
* @brief Sets the desired flash property.
*
* @param config A pointer to the storage for the driver runtime state.
* @param whichProperty The desired property from the list of properties in
* enum flash_property_tag_t
* @param value A to set for the desired flash property.
*
* @retval #kStatus_FLASH_Success API was executed successfully.
* @retval #kStatus_FLASH_InvalidArgument An invalid argument is provided.
* @retval #kStatus_FLASH_UnknownProperty An unknown property tag.
* @retval #kStatus_FLASH_ReadOnlyProperty An read-only property tag.
*/
status_t FLASH_SetProperty(flash_config_t *config, flash_property_tag_t whichProperty, uint32_t value);
/*@}*/
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif
/*@}*/ /*@}*/
#endif /* _FSL_IAP_H_ */ #endif /* __FLASH_FLASH_H_ */

253
ext/hal/nxp/mcux/drivers/lpc/fsl_iap_ffr.h Normal file
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@ -0,0 +1,253 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*
*/
#ifndef __FSL_IAP_FFR_H_
#define __FSL_IAP_FFR_H_
#include "fsl_iap.h"
/*!
* @addtogroup iap_ffr_driver
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @name Flash IFR version
* @{
*/
/*! @brief Flash IFR driver version for SDK*/
#define FSL_FLASH_IFR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
/*@}*/
/*! @brief Alignment(down) utility. */
#if !defined(ALIGN_DOWN)
#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
#endif
/*! @brief Alignment(up) utility. */
#if !defined(ALIGN_UP)
#define ALIGN_UP(x, a) (-((int32_t)((uint32_t)(-((int32_t)(x))) & (uint32_t)(-((int32_t)(a))))))
#endif
#define FLASH_FFR_MAX_PAGE_SIZE (512u)
#define FLASH_FFR_HASH_DIGEST_SIZE (32u)
#define FLASH_FFR_IV_CODE_SIZE (52u)
enum _flash_ffr_page_offset
{
kFfrPageOffset_CFPA = 0, /*!< Customer In-Field programmed area*/
kFfrPageOffset_CFPA_Scratch = 0, /*!< CFPA Scratch page */
kFfrPageOffset_CFPA_Cfg = 1, /*!< CFPA Configuration area (Ping page)*/
kFfrPageOffset_CFPA_CfgPong = 2, /*!< Same as CFPA page (Pong page)*/
kFfrPageOffset_CMPA = 3, /*!< Customer Manufacturing programmed area*/
kFfrPageOffset_CMPA_Cfg = 3, /*!< CMPA Configuration area (Part of CMPA)*/
kFfrPageOffset_CMPA_Key = 4, /*!< Key Store area (Part of CMPA)*/
kFfrPageOffset_NMPA = 7, /*!< NXP Manufacturing programmed area*/
kFfrPageOffset_NMPA_Romcp = 7, /*!< ROM patch area (Part of NMPA)*/
kFfrPageOffset_NMPA_Repair = 9, /*!< Repair area (Part of NMPA)*/
kFfrPageOffset_NMPA_Cfg = 15, /*!< NMPA configuration area (Part of NMPA)*/
kFfrPageOffset_NMPA_End = 16, /*!< Reserved (Part of NMPA)*/
};
enum _flash_ffr_page_num
{
kFfrPageNum_CFPA = 3, /*!< Customer In-Field programmed area*/
kFfrPageNum_CMPA = 4, /*!< Customer Manufacturing programmed area*/
kFfrPageNum_NMPA = 10, /*!< NXP Manufacturing programmed area*/
kFfrPageNum_CMPA_Cfg = 1,
kFfrPageNum_CMPA_Key = 3,
kFfrPageNum_NMPA_Romcp = 2,
kFfrPageNum_SpecArea = kFfrPageNum_CFPA + kFfrPageNum_CMPA,
kFfrPageNum_Total = (kFfrPageNum_CFPA + kFfrPageNum_CMPA + kFfrPageNum_NMPA),
};
enum _flash_ffr_block_size
{
kFfrBlockSize_Key = 52u,
kFfrBlockSize_ActivationCode = 1192u,
};
typedef struct _cfpa_cfg_iv_code
{
uint32_t keycodeHeader;
uint8_t reserved[FLASH_FFR_IV_CODE_SIZE];
} cfpa_cfg_iv_code_t;
typedef struct _cfpa_cfg_info
{
uint32_t header; /*!< [0x000-0x003] */
uint32_t version; /*!< [0x004-0x007 */
uint32_t secureFwVersion; /*!< [0x008-0x00b */
uint32_t nsFwVersion; /*!< [0x00c-0x00f] */
uint32_t imageKeyRevoke; /*!< [0x010-0x013] */
uint8_t reserved0[4]; /*!< [0x014-0x017] */
uint32_t rotkhRevoke; /*!< [0x018-0x01b] */
uint32_t vendorUsage; /*!< [0x01c-0x01f] */
uint32_t dcfgNsPin; /*!< [0x020-0x013] */
uint32_t dcfgNsDflt; /*!< [0x024-0x017] */
uint32_t enableFaMode; /*!< [0x028-0x02b] */
uint8_t reserved1[4]; /*!< [0x02c-0x02f] */
cfpa_cfg_iv_code_t ivCodePrinceRegion[3]; /*!< [0x030-0x0d7] */
uint8_t reserved2[264]; /*!< [0x0d8-0x1df] */
uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */
} cfpa_cfg_info_t;
#define FFR_BOOTCFG_BOOTSPEED_MASK (0x18U)
#define FFR_BOOTCFG_BOOTSPEED_SHIFT (7U)
#define FFR_BOOTCFG_BOOTSPEED_48MHZ (0x0U)
#define FFR_BOOTCFG_BOOTSPEED_96MHZ (0x1U)
#define FFR_USBID_VENDORID_MASK (0xFFFFU)
#define FFR_USBID_VENDORID_SHIFT (0U)
#define FFR_USBID_PRODUCTID_MASK (0xFFFF0000U)
#define FFR_USBID_PRODUCTID_SHIFT (16U)
typedef struct _cmpa_cfg_info
{
uint32_t bootCfg; /*!< [0x000-0x003] */
uint32_t spiFlashCfg; /*!< [0x004-0x007] */
struct
{
uint16_t vid;
uint16_t pid;
} usbId; /*!< [0x008-0x00b] */
uint32_t sdioCfg; /*!< [0x00c-0x00f] */
uint32_t dcfgPin; /*!< [0x010-0x013] */
uint32_t dcfgDflt; /*!< [0x014-0x017] */
uint32_t dapVendorUsage; /*!< [0x018-0x01b] */
uint32_t secureBootCfg; /*!< [0x01c-0x01f] */
uint32_t princeBaseAddr; /*!< [0x020-0x023] */
uint32_t princeSr[3]; /*!< [0x024-0x02f] */
uint8_t reserved0[32]; /*!< [0x030-0x04f] */
uint32_t rotkh[8]; /*!< [0x050-0x06f] */
uint8_t reserved1[368]; /*!< [0x070-0x1df] */
uint8_t sha256[32]; /*!< [0x1e0-0x1ff] */
} cmpa_cfg_info_t;
typedef struct _cmpa_key_store_header
{
uint32_t header;
uint8_t reserved[4];
} cmpa_key_store_header_t;
#define FFR_SYSTEM_SPEED_CODE_MASK (0x3U)
#define FFR_SYSTEM_SPEED_CODE_SHIFT (0U)
#define FFR_SYSTEM_SPEED_CODE_FRO12MHZ_12MHZ (0x0U)
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_24MHZ (0x1U)
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_48MHZ (0x2U)
#define FFR_SYSTEM_SPEED_CODE_FROHF96MHZ_96MHZ (0x3U)
#define FFR_PERIPHERALCFG_PERI_MASK (0x7FFFFFFFU)
#define FFR_PERIPHERALCFG_PERI_SHIFT (0U)
#define FFR_PERIPHERALCFG_COREEN_MASK (0x10000000U)
#define FFR_PERIPHERALCFG_COREEN_SHIFT (31U)
typedef struct _nmpa_cfg_info
{
uint16_t fro32kCfg; /*!< [0x000-0x001] */
uint8_t reserved0[6]; /*!< [0x002-0x007] */
uint8_t sysCfg; /*!< [0x008-0x008] */
uint8_t reserved1[7]; /*!< [0x009-0x00f] */
struct
{
uint32_t data;
uint32_t reserved[3];
} GpoInitData[3]; /*!< [0x010-0x03f] */
uint32_t GpoDataChecksum[4]; /*!< [0x040-0x04f] */
uint32_t finalTestBatchId[4]; /*!< [0x050-0x05f] */
uint32_t deviceType; /*!< [0x060-0x063] */
uint32_t finalTestProgVersion; /*!< [0x064-0x067] */
uint32_t finalTestDate; /*!< [0x068-0x06b] */
uint32_t finalTestTime; /*!< [0x06c-0x06f] */
uint32_t uuid[4]; /*!< [0x070-0x07f] */
uint8_t reserved2[32]; /*!< [0x080-0x09f] */
uint32_t peripheralCfg; /*!< [0x0a0-0x0a3] */
uint32_t ramSizeCfg; /*!< [0x0a4-0x0a7] */
uint32_t flashSizeCfg; /*!< [0x0a8-0x0ab] */
uint8_t reserved3[36]; /*!< [0x0ac-0x0cf] */
uint8_t fro1mCfg; /*!< [0x0d0-0x0d0] */
uint8_t reserved4[15]; /*!< [0x0d1-0x0df] */
uint32_t dcdc[4]; /*!< [0x0e0-0x0ef] */
uint32_t bod; /*!< [0x0f0-0x0f3] */
uint8_t reserved5[12]; /*!< [0x0f4-0x0ff] */
uint8_t calcHashReserved[192]; /*!< [0x100-0x1bf] */
uint8_t sha256[32]; /*!< [0x1c0-0x1df] */
uint32_t ecidBackup[4]; /*!< [0x1e0-0x1ef] */
uint32_t pageChecksum[4]; /*!< [0x1f0-0x1ff] */
} nmpa_cfg_info_t;
typedef struct _ffr_key_store
{
uint8_t reserved[3][FLASH_FFR_MAX_PAGE_SIZE];
} ffr_key_store_t;
typedef enum _ffr_key_type
{
kFFR_KeyTypeSbkek = 0x00U,
kFFR_KeyTypeUser = 0x01U,
kFFR_KeyTypeUds = 0x02U,
kFFR_KeyTypePrinceRegion0 = 0x03U,
kFFR_KeyTypePrinceRegion1 = 0x04U,
kFFR_KeyTypePrinceRegion2 = 0x05U,
} ffr_key_type_t;
typedef enum _ffr_bank_type
{
kFFR_BankTypeBank0_NMPA = 0x00U,
kFFR_BankTypeBank1_CMPA = 0x01U,
kFFR_BankTypeBank2_CFPA = 0x02U
} ffr_bank_type_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*! Generic APIs for FFR */
status_t FFR_Init(flash_config_t *config);
status_t FFR_Deinit(flash_config_t *config);
/*! APIs to access CFPA pages */
status_t FFR_CustomerPagesInit(flash_config_t *config);
status_t FFR_InfieldPageWrite(flash_config_t *config, uint8_t *page_data, uint32_t valid_len);
/*! Read data stored in 'Customer In-field Page'. */
status_t FFR_GetCustomerInfieldData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
/*! APIs to access CMPA pages */
status_t FFR_CustFactoryPageWrite(flash_config_t *config, uint8_t *page_data, bool seal_part);
/*! Read data stored in 'Customer Factory CFG Page'. */
status_t FFR_GetCustomerData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
status_t FFR_KeystoreWrite(flash_config_t *config, ffr_key_store_t *pKeyStore);
status_t FFR_KeystoreGetAC(flash_config_t *config, uint8_t *pActivationCode);
status_t FFR_KeystoreGetKC(flash_config_t *config, uint8_t *pKeyCode, ffr_key_type_t keyIndex);
/*! APIs to access NMPA pages */
status_t FFR_NxpAreaCheckIntegrity(flash_config_t *config);
status_t FFR_GetRompatchData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
/*! Read data stored in 'NXP Manufacuring Programmed CFG Page'. */
status_t FFR_GetManufactureData(flash_config_t *config, uint8_t *pData, uint32_t offset, uint32_t len);
status_t FFR_GetUUID(flash_config_t *config, uint8_t *uuid);
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /*! __FSL_FLASH_FFR_H_ */

497
ext/hal/nxp/mcux/drivers/lpc/fsl_inputmux_connections.h
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@ -3,7 +3,6 @@
* Copyright (c) 2016, NXP * Copyright (c) 2016, NXP
* All rights reserved. * All rights reserved.
* *
*
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -23,133 +22,387 @@
* @{ * @{
*/ */
/*!
* @name Input multiplexing connections
* @{
*/
/*! @brief Periphinmux IDs */ /*! @brief Periphinmux IDs */
#define PINTSEL_PMUX_ID 0xC0U #define SCT0_INMUX0 0x00U
#define DMA_TRIG0_PMUX_ID 0xE0U #define TIMER0CAPTSEL0 0x20U
#define DMA_OTRIG_PMUX_ID 0x160U #define TIMER1CAPTSEL0 0x40U
#define FREQMEAS_PMUX_ID 0x180U #define TIMER2CAPTSEL0 0x60U
#define PINTSEL0 0xC0U
#define DMA0_ITRIG_INMUX0 0xE0U
#define DMA0_OTRIG_INMUX0 0x160U
#define FREQMEAS_REF_REG 0x180U
#define FREQMEAS_TARGET_REG 0x184U
#define TIMER3CAPTSEL0 0x1A0U
#define TIMER4CAPTSEL0 0x1C0U
#define PINTSECSEL0 0x1E0U
#define DMA1_ITRIG_INMUX0 0x200U
#define DMA1_OTRIG_INMUX0 0x240U
#define PMUX_SHIFT 20U #define PMUX_SHIFT 20U
/*! @brief INPUTMUX connections type */ /*! @brief INPUTMUX connections type */
typedef enum _inputmux_connection_t typedef enum _inputmux_connection_t
{ {
/*!< Frequency measure. */ /*!< SCT0 INMUX. */
kINPUTMUX_MainOscToFreqmeas = 0U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi0ToSct0 = 0U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Fro12MhzToFreqmeas = 1U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi1ToSct0 = 1U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_WdtOscToFreqmeas = 2U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi2ToSct0 = 2U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_32KhzOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi3ToSct0 = 3U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_MainClkToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi4ToSct0 = 4U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin4ToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi5ToSct0 = 5U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin20ToFreqmeas = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi6ToSct0 = 6U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin24ToFreqmeas = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_SctGpi7ToSct0 = 7U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin4ToFreqmeas = 8U + (FREQMEAS_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Ctimer0M0ToSct0 = 8U + (SCT0_INMUX0 << PMUX_SHIFT),
/*!< Pin Interrupt. */ kINPUTMUX_Ctimer1M0ToSct0 = 9U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Ctimer2M0ToSct0 = 10U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Ctimer3M0ToSct0 = 11U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Ctimer4M0ToSct0 = 12U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_AdcIrqToSct0 = 13U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpiointBmatchToSct0 = 14U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToSct0 = 15U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToSct0 = 16U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CompOutToSct0 = 17U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedSck0ToSct0 = 18U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedSck1ToSct0 = 19U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs0ToSct0 = 20U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs1ToSct0 = 21U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_ArmTxevToSct0 = 22U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_DebugHaltedToSct0 = 23U + (SCT0_INMUX0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL_PMUX_ID << PMUX_SHIFT), /*!< TIMER0 CAPTSEL. */
kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp0ToTimer0Captsel = 0U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp1ToTimer0Captsel = 1U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp2ToTimer0Captsel = 2U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp3ToTimer0Captsel = 3U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp4ToTimer0Captsel = 4U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp5ToTimer0Captsel = 5U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp6ToTimer0Captsel = 6U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp7ToTimer0Captsel = 7U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp8ToTimer0Captsel = 8U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp9ToTimer0Captsel = 9U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp10ToTimer0Captsel = 10U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp11ToTimer0Captsel = 11U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp12ToTimer0Captsel = 12U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp13ToTimer0Captsel = 13U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp14ToTimer0Captsel = 14U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp15ToTimer0Captsel = 15U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp16ToTimer0Captsel = 16U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp17ToTimer0Captsel = 17U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp18ToTimer0Captsel = 18U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp19ToTimer0Captsel = 19U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer0Captsel = 20U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer0Captsel = 21U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CompOutToTimer0Captsel = 22U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs0ToTimer0Captsel = 23U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs1ToTimer0Captsel = 24U + (TIMER0CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL_PMUX_ID << PMUX_SHIFT), /*!< TIMER1 CAPTSEL. */
kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp0ToTimer1Captsel = 0U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp1ToTimer1Captsel = 1U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp2ToTimer1Captsel = 2U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp3ToTimer1Captsel = 3U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp4ToTimer1Captsel = 4U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp5ToTimer1Captsel = 5U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp6ToTimer1Captsel = 6U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp7ToTimer1Captsel = 7U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp8ToTimer1Captsel = 8U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp9ToTimer1Captsel = 9U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp10ToTimer1Captsel = 10U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp11ToTimer1Captsel = 11U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp12ToTimer1Captsel = 12U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp13ToTimer1Captsel = 13U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp14ToTimer1Captsel = 14U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp15ToTimer1Captsel = 15U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp16ToTimer1Captsel = 16U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp17ToTimer1Captsel = 17U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp18ToTimer1Captsel = 18U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp19ToTimer1Captsel = 19U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer1Captsel = 20U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
/*!< DMA ITRIG. */ kINPUTMUX_Usb1FrameToggleToTimer1Captsel = 21U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Adc0SeqaIrqToDma = 0U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CompOutToTimer1Captsel = 22U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_ADC0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs0ToTimer1Captsel = 23U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs1ToTimer1Captsel = 24U + (TIMER1CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), /*!< TIMER2 CAPTSEL. */
kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp0ToTimer2Captsel = 0U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp1ToTimer2Captsel = 1U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp2ToTimer2Captsel = 2U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp3ToTimer2Captsel = 3U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp4ToTimer2Captsel = 4U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp5ToTimer2Captsel = 5U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp6ToTimer2Captsel = 6U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp7ToTimer2Captsel = 7U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp8ToTimer2Captsel = 8U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp9ToTimer2Captsel = 9U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp10ToTimer2Captsel = 10U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp11ToTimer2Captsel = 11U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp12ToTimer2Captsel = 12U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp13ToTimer2Captsel = 13U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Otrig3ToDma = 19U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp14ToTimer2Captsel = 14U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
/*!< DMA OTRIG. */ kINPUTMUX_CtimerInp15ToTimer2Captsel = 15U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm0RxTrigoutToTriginChannels = 0U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp16ToTimer2Captsel = 16U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm0TxTrigoutToTriginChannels = 1U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp17ToTimer2Captsel = 17U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm1RxTrigoutToTriginChannels = 2U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp18ToTimer2Captsel = 18U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm1TxTrigoutToTriginChannels = 3U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CtimerInp19ToTimer2Captsel = 19U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm2RxTrigoutToTriginChannels = 4U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb0FrameToggleToTimer2Captsel = 20U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm2TxTrigoutToTriginChannels = 5U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_Usb1FrameToggleToTimer2Captsel = 21U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm3RxTrigoutToTriginChannels = 6U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_CompOutToTimer2Captsel = 22U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm3TxTrigoutToTriginChannels = 7U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs0ToTimer2Captsel = 23U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm4RxTrigoutToTriginChannels = 8U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_I2sSharedWs1ToTimer2Captsel = 24U + (TIMER2CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm4TxTrigoutToTriginChannels = 9U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm5RxTrigoutToTriginChannels = 10U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), /*!< Pin interrupt select. */
kINPUTMUX_DmaFlexcomm5TxTrigoutToTriginChannels = 11U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm6RxTrigoutToTriginChannels = 12U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin1ToPintsel = 1U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm6TxTrigoutToTriginChannels = 13U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin2ToPintsel = 2U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm7RxTrigoutToTriginChannels = 14U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin3ToPintsel = 3U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaFlexcomm7TxTrigoutToTriginChannels = 15U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin4ToPintsel = 4U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaDmic0Ch0TrigoutToTriginChannels = 16U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin5ToPintsel = 5U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_Dmamic0Ch1TrigoutToTriginChannels = 17U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin6ToPintsel = 6U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaSpifi0TrigoutToTriginChannels = 18U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin7ToPintsel = 7U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_DmaChannel19_TrigoutToTriginChannels = 19U + (DMA_OTRIG_PMUX_ID << PMUX_SHIFT), kINPUTMUX_GpioPort0Pin8ToPintsel = 8U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin9ToPintsel = 9U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin10ToPintsel = 10U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin11ToPintsel = 11U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin12ToPintsel = 12U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin13ToPintsel = 13U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin14ToPintsel = 14U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin15ToPintsel = 15U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin16ToPintsel = 16U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin17ToPintsel = 17U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin18ToPintsel = 18U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin19ToPintsel = 19U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin20ToPintsel = 20U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin21ToPintsel = 21U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin22ToPintsel = 22U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin23ToPintsel = 23U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin24ToPintsel = 24U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin25ToPintsel = 25U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin26ToPintsel = 26U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin27ToPintsel = 27U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin28ToPintsel = 28U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin29ToPintsel = 29U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin30ToPintsel = 30U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin31ToPintsel = 31U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin0ToPintsel = 32U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin1ToPintsel = 33U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin2ToPintsel = 34U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin3ToPintsel = 35U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin4ToPintsel = 36U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin5ToPintsel = 37U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin6ToPintsel = 38U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin7ToPintsel = 39U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin8ToPintsel = 40U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin9ToPintsel = 41U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin10ToPintsel = 42U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin11ToPintsel = 43U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin12ToPintsel = 44U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin13ToPintsel = 45U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin14ToPintsel = 46U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin15ToPintsel = 47U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin16ToPintsel = 48U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin17ToPintsel = 49U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin18ToPintsel = 50U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin19ToPintsel = 51U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin20ToPintsel = 52U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin21ToPintsel = 53U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin22ToPintsel = 54U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin23ToPintsel = 55U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin24ToPintsel = 56U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin25ToPintsel = 57U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin26ToPintsel = 58U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin27ToPintsel = 59U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin28ToPintsel = 60U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin29ToPintsel = 61U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin30ToPintsel = 62U + (PINTSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort1Pin31ToPintsel = 63U + (PINTSEL0 << PMUX_SHIFT),
/*!< DMA0 Input trigger. */
kINPUTMUX_PinInt0ToDma0 = 0U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt1ToDma0 = 1U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt2ToDma0 = 2U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt3ToDma0 = 3U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer0M0ToDma0 = 4U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer0M1ToDma0 = 5U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer1M0ToDma0 = 6U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer1M1ToDma0 = 7U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer2M0ToDma0 = 8U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer2M1ToDma0 = 9U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer3M0ToDma0 = 10U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer3M1ToDma0 = 11U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer4M0ToDma0 = 12U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer4M1ToDma0 = 13U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_CompOutToDma0 = 14U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig0ToDma0 = 15U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig1ToDma0 = 16U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig2ToDma0 = 17U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig3ToDma0 = 18U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq0ToDma0 = 19U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq1ToDma0 = 20U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_HashDmaRxToDma0 = 21U + (DMA0_ITRIG_INMUX0 << PMUX_SHIFT),
/*!< DMA0 output trigger. */
kINPUTMUX_Dma0Hash0TxTrigoutToTriginChannels = 0U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0HsLspiRxTrigoutToTriginChannels = 2U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0HsLspiTxTrigoutToTriginChannels = 3U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm3RxTrigoutToTriginChannels = 10U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm3TxTrigoutToTriginChannels = 11U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm4RxTrigoutToTriginChannels = 12U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm4TxTrigoutToTriginChannels = 13U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm5RxTrigoutToTriginChannels = 14U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm5TxTrigoutToTriginChannels = 15U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm6RxTrigoutToTriginChannels = 16U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm6TxTrigoutToTriginChannels = 17U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm7RxTrigoutToTriginChannels = 18U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Flexcomm7TxTrigoutToTriginChannels = 19U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Capt0TxTrigoutToTriginChannels = 20U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Adc0Ch0TrigoutToTriginChannels = 21U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma0Adc0Ch1TrigoutToTriginChannels = 22U + (DMA0_OTRIG_INMUX0 << PMUX_SHIFT),
/*!< Selection for frequency measurement reference clock. */
kINPUTMUX_ExternOscToFreqmeasRef = 0U + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_Fro12MhzToFreqmeasRef = 1u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_Fro96MhzToFreqmeasRef = 2u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_WdtOscToFreqmeasRef = 3u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_32KhzOscToFreqmeasRef= 4u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_MainClkToFreqmeasRef = 5u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_FreqmeGpioClk_aRef = 6u + (FREQMEAS_REF_REG << PMUX_SHIFT),
kINPUTMUX_FreqmeGpioClk_bRef = 7u + (FREQMEAS_REF_REG << PMUX_SHIFT),
/*!< Selection for frequency measurement target clock. */
kINPUTMUX_ExternOscToFreqmeasTarget = 0U + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_Fro12MhzToFreqmeasTarget = 1u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_Fro96MhzToFreqmeasTarget = 2u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_WdtOscToFreqmeasTarget = 3u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_32KhzOscToFreqmeasTarget= 4u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_MainClkToFreqmeasTarget = 5u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_FreqmeGpioClk_aTarget = 6u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
kINPUTMUX_FreqmeGpioClk_bTarget = 7u + (FREQMEAS_TARGET_REG << PMUX_SHIFT),
/*!< TIMER3 CAPTSEL. */
kINPUTMUX_CtimerInp0ToTimer3Captsel = 0U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp1ToTimer3Captsel = 1U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp2ToTimer3Captsel = 2U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp3ToTimer3Captsel = 3U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp4ToTimer3Captsel = 4U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp5ToTimer3Captsel = 5U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp6ToTimer3Captsel = 6U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp7ToTimer3Captsel = 7U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp8ToTimer3Captsel = 8U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp9ToTimer3Captsel = 9U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp10ToTimer3Captsel = 10U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp11ToTimer3Captsel = 11U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp12ToTimer3Captsel = 12U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp13ToTimer3Captsel = 13U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp14ToTimer3Captsel = 14U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp15ToTimer3Captsel = 15U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp16ToTimer3Captsel = 16U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp17ToTimer3Captsel = 17U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp18ToTimer3Captsel = 18U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp19ToTimer3Captsel = 19U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Usb0FrameToggleToTimer3Captsel = 20U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Usb1FrameToggleToTimer3Captsel = 21U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CompOutToTimer3Captsel = 22U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_I2sSharedWs0ToTimer3Captsel = 23U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_I2sSharedWs1ToTimer3Captsel = 24U + (TIMER3CAPTSEL0 << PMUX_SHIFT),
/*!< Timer4 CAPTSEL. */
kINPUTMUX_CtimerInp0ToTimer4Captsel = 0U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp1ToTimer4Captsel = 1U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp2ToTimer4Captsel = 2U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp3ToTimer4Captsel = 3U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp4ToTimer4Captsel = 4U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp5ToTimer4Captsel = 5U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp6ToTimer4Captsel = 6U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp7ToTimer4Captsel = 7U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp8ToTimer4Captsel = 8U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp9ToTimer4Captsel = 9U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp10ToTimer4Captsel = 10U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp11ToTimer4Captsel = 11U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp12ToTimer4Captsel = 12U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp13ToTimer4Captsel = 13U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp14ToTimer4Captsel = 14U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp15ToTimer4Captsel = 15U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp16ToTimer4Captsel = 16U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp17ToTimer4Captsel = 17U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp18ToTimer4Captsel = 18U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CtimerInp19ToTimer4Captsel = 19U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Usb0FrameToggleToTimer4Captsel = 20U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_Usb1FrameToggleToTimer4Captsel = 21U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_CompOutToTimer4Captsel = 22U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_I2sSharedWs0ToTimer4Captsel = 23U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
kINPUTMUX_I2sSharedWs1ToTimer4Captsel = 24U + (TIMER4CAPTSEL0 << PMUX_SHIFT),
/*Pin interrupt secure select */
kINPUTMUX_GpioPort0Pin0ToPintSecsel = 0U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin1ToPintSecsel = 1U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin2ToPintSecsel = 2U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin3ToPintSecsel = 3U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin4ToPintSecsel = 4U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin5ToPintSecsel = 5U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin6ToPintSecsel = 6U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin7ToPintSecsel = 7U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin8ToPintSecsel = 8U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin9ToPintSecsel = 9U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin10ToPintSecsel = 10U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin11ToPintSecsel = 11U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin12ToPintSecsel = 12U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin13ToPintSecsel = 13U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin14ToPintSecsel = 14U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin15ToPintSecsel = 15U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin16ToPintSecsel = 16U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin17ToPintSecsel = 17U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin18ToPintSecsel = 18U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin19ToPintSecsel = 19U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin20ToPintSecsel = 20U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin21ToPintSecsel = 21U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin22ToPintSecsel = 22U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin23ToPintSecsel = 23U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin24ToPintSecsel = 24U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin25ToPintSecsel = 25U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin26ToPintSecsel = 26U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin27ToPintSecsel = 27U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin28ToPintSecsel = 28U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin29ToPintSecsel = 29U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin30ToPintSecsel = 30U + (PINTSECSEL0 << PMUX_SHIFT),
kINPUTMUX_GpioPort0Pin31ToPintSecsel = 31U + (PINTSECSEL0 << PMUX_SHIFT),
/*!< DMA1 Input trigger. */
kINPUTMUX_PinInt0ToDma1 = 0U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt1ToDma1 = 1U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt2ToDma1 = 2U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_PinInt3ToDma1 = 3U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer0M0ToDma1 = 4U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer0M1ToDma1 = 5U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer2M0ToDma1 = 6U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Ctimer4M1ToDma1 = 7U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig0ToDma1 = 8U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig1ToDma1 = 9U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig2ToDma1 = 10U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Otrig3ToDma1 = 11U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq0ToDma1 = 12U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq1ToDma1 = 13U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_HashDmaRxToDma1 = 14U + (DMA1_ITRIG_INMUX0 << PMUX_SHIFT),
/*!< DMA1 output trigger. */
kINPUTMUX_Dma1Hash0TxTrigoutToTriginChannels = 0U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1HsLspiRxTrigoutToTriginChannels = 2U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1HsLspiTxTrigoutToTriginChannels = 3U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm0RxTrigoutToTriginChannels = 4U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm0TxTrigoutToTriginChannels = 5U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm1RxTrigoutToTriginChannels = 6U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm1TxTrigoutToTriginChannels = 7U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm2RxTrigoutToTriginChannels = 8U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
kINPUTMUX_Dma1Flexcomm2TxTrigoutToTriginChannels = 9U + (DMA1_OTRIG_INMUX0 << PMUX_SHIFT),
} inputmux_connection_t; } inputmux_connection_t;
/*@}*/ /*@}*/

243
ext/hal/nxp/mcux/drivers/lpc/fsl_iocon.h
View file

@ -2,7 +2,7 @@
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2017 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -27,7 +27,6 @@
#define FSL_COMPONENT_ID "platform.drivers.lpc_iocon" #define FSL_COMPONENT_ID "platform.drivers.lpc_iocon"
#endif #endif
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief IOCON driver version 2.0.0. */ /*! @brief IOCON driver version 2.0.0. */
@ -50,75 +49,183 @@ typedef struct _iocon_group
* @note See the User Manual for specific modes and functions supported by the various pins. * @note See the User Manual for specific modes and functions supported by the various pins.
*/ */
#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4) #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */ #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */ #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */ #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */ #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */ #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */ #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */ #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */ #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */ #if defined(IOCON_PIO_MODE_SHIFT)
#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */ #define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */ #define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */ #define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */ #define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */ #endif
#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */
#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */ #if defined(IOCON_PIO_I2CSLEW_SHIFT)
#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */ #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */ #define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */ #endif
#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */
#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */ #if defined(IOCON_PIO_EGP_SHIFT)
#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */ #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */ #define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */ #endif
#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */
#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */ #if defined(IOCON_PIO_SLEW_SHIFT)
#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */ #define IOCON_SLEW_STANDARD (0x0 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */ #define IOCON_SLEW_FAST (0x1 << IOCON_PIO_SLEW_SHIFT) /*!< Driver Slew Rate Control */
#endif
#if defined(IOCON_PIO_INVERT_SHIFT)
#define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
#endif
#if defined(IOCON_PIO_DIGIMODE_SHIFT)
#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
#define IOCON_DIGITAL_EN \
(0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
#endif
#if defined(IOCON_PIO_FILTEROFF_SHIFT)
#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
#endif
#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
#endif
#if defined(IOCON_PIO_OD_SHIFT)
#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
#endif
#if defined(IOCON_PIO_I2CFILTER_SHIFT)
#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled, */
#endif
#if defined(IOCON_PIO_ASW_SHIFT)
#define IOCON_AWS_EN (0x1 << IOCON_PIO_ASW_SHIFT) /*!< Enables analog switch function */
#endif
#if defined(IOCON_PIO_SSEL_SHIFT)
#define IOCON_SSEL_3V3 (0x0 << IOCON_PIO_SSEL_SHIFT) /*!< 3V3 signaling in I2C mode */
#define IOCON_SSEL_1V8 (0x1 << IOCON_PIO_SSEL_SHIFT) /*!< 1V8 signaling in I2C mode */
#endif
#if defined(IOCON_PIO_ECS_SHIFT)
#define IOCON_ECS_OFF (0x0 << IOCON_PIO_ECS_SHIFT) /*!< IO is an open drain cell */
#define IOCON_ECS_ON (0x1 << IOCON_PIO_ECS_SHIFT) /*!< Pull-up resistor is connected */
#endif
#if defined(IOCON_PIO_S_MODE_SHIFT)
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
#define IOCON_S_MODE_1CLK \
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
*/
#define IOCON_S_MODE_2CLK \
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
*/
#define IOCON_S_MODE_3CLK \
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
*/
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
#endif
#if defined(IOCON_PIO_CLK_DIV_SHIFT)
#define IOCON_CLKDIV(div) \ #define IOCON_CLKDIV(div) \
((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ ((div) \
<< IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
#endif
#else #else
#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */ #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */ #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */ #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */ #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */ #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */ #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */ #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */ #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */ #if defined(IOCON_PIO_MODE_SHIFT)
#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */ #define IOCON_MODE_INACT (0x0 << IOCON_PIO_MODE_SHIFT) /*!< No addition pin function */
#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */ #define IOCON_MODE_PULLDOWN (0x1 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-down function */
#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */ #define IOCON_MODE_PULLUP (0x2 << IOCON_PIO_MODE_SHIFT) /*!< Selects pull-up function */
#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */ #define IOCON_MODE_REPEATER (0x3 << IOCON_PIO_MODE_SHIFT) /*!< Selects pin repeater function */
#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */ #endif
#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */ #if defined(IOCON_PIO_I2CSLEW_SHIFT)
#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */ #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_I2CSLEW_SHIFT) /*!< GPIO Mode */
#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */ #define IOCON_I2C_SLEW (0x0 << IOCON_PIO_I2CSLEW_SHIFT) /*!< I2C Slew Rate Control */
#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */ #endif
#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */
#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */ #if defined(IOCON_PIO_EGP_SHIFT)
#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */ #define IOCON_GPIO_MODE (0x1 << IOCON_PIO_EGP_SHIFT) /*!< GPIO Mode */
#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */ #define IOCON_I2C_SLEW (0x0 << IOCON_PIO_EGP_SHIFT) /*!< I2C Slew Rate Control */
#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */ #endif
#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */
#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */ #if defined(IOCON_PIO_INVERT_SHIFT)
#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */ #define IOCON_INV_EN (0x1 << IOCON_PIO_INVERT_SHIFT) /*!< Enables invert function on input */
#endif
#if defined(IOCON_PIO_DIGIMODE_SHIFT)
#define IOCON_ANALOG_EN (0x0 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables analog function by setting 0 to bit 7 */
#define IOCON_DIGITAL_EN \
(0x1 << IOCON_PIO_DIGIMODE_SHIFT) /*!< Enables digital function by setting 1 to bit 7(default) */
#endif
#if defined(IOCON_PIO_FILTEROFF_SHIFT)
#define IOCON_INPFILT_OFF (0x1 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter Off for GPIO pins */
#define IOCON_INPFILT_ON (0x0 << IOCON_PIO_FILTEROFF_SHIFT) /*!< Input filter On for GPIO pins */
#endif
#if defined(IOCON_PIO_I2CDRIVE_SHIFT)
#define IOCON_I2C_LOWDRIVER (0x0 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< Low drive, Output drive sink is 4 mA */
#define IOCON_I2C_HIGHDRIVER (0x1 << IOCON_PIO_I2CDRIVE_SHIFT) /*!< High drive, Output drive sink is 20 mA */
#endif
#if defined(IOCON_PIO_OD_SHIFT)
#define IOCON_OPENDRAIN_EN (0x1 << IOCON_PIO_OD_SHIFT) /*!< Enables open-drain function */
#endif
#if defined(IOCON_PIO_I2CFILTER_SHIFT)
#define IOCON_I2CFILTER_OFF (0x1 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter enabled */
#define IOCON_I2CFILTER_ON (0x0 << IOCON_PIO_I2CFILTER_SHIFT) /*!< I2C 50 ns glitch filter not enabled */
#endif
#if defined(IOCON_PIO_S_MODE_SHIFT)
#define IOCON_S_MODE_0CLK (0x0 << IOCON_PIO_S_MODE_SHIFT) /*!< Bypass input filter */
#define IOCON_S_MODE_1CLK \
(0x1 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 1 filter clock are rejected \ \ \ \ \
*/
#define IOCON_S_MODE_2CLK \
(0x2 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 2 filter clock2 are rejected \ \ \ \ \
*/
#define IOCON_S_MODE_3CLK \
(0x3 << IOCON_PIO_S_MODE_SHIFT) /*!< Input pulses shorter than 3 filter clock2 are rejected \ \ \ \ \
*/
#define IOCON_S_MODE(clks) ((clks) << IOCON_PIO_S_MODE_SHIFT) /*!< Select clocks for digital input filter mode */
#endif
#if defined(IOCON_PIO_CLK_DIV_SHIFT)
#define IOCON_CLKDIV(div) \ #define IOCON_CLKDIV(div) \
((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */ ((div) \
<< IOCON_PIO_CLK_DIV_SHIFT) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
#endif
#endif #endif
#if defined(__cplusplus) #if defined(__cplusplus)
extern "C" { extern "C" {

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ext/hal/nxp/mcux/drivers/lpc/fsl_lpadc.c Normal file
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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_lpadc.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.lpadc"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get instance number for LPADC module.
*
* @param base LPADC peripheral base address
*/
static uint32_t LPADC_GetInstance(ADC_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to LPADC bases for each instance. */
static ADC_Type *const s_lpadcBases[] = ADC_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to LPADC clocks for each instance. */
static const clock_ip_name_t s_lpadcClocks[] = LPADC_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t LPADC_GetInstance(ADC_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_lpadcBases); instance++)
{
if (s_lpadcBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_lpadcBases));
return instance;
}
/*!
* brief Initializes the LPADC module.
*
* param base LPADC peripheral base address.
* param config Pointer to configuration structure. See "lpadc_config_t".
*/
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config)
{
/* Check if the pointer is available. */
assert(config != NULL);
uint32_t tmp32 = 0U;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock for LPADC instance. */
CLOCK_EnableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Reset the module. */
LPADC_DoResetConfig(base);
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
LPADC_DoResetFIFO0(base);
LPADC_DoResetFIFO1(base);
#else
LPADC_DoResetFIFO(base);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/* Disable the module before setting configuration. */
LPADC_Enable(base, false);
/* Configure the module generally. */
if (config->enableInDozeMode)
{
base->CTRL &= ~ADC_CTRL_DOZEN_MASK;
}
else
{
base->CTRL |= ADC_CTRL_DOZEN_MASK;
}
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
/* Set calibration average mode. */
base->CTRL |= ADC_CTRL_CAL_AVGS(config->conversionAverageMode);
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
/* ADCx_CFG. */
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
if (config->enableInternalClock)
{
tmp32 |= ADC_CFG_ADCKEN_MASK;
}
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
if (config->enableVref1LowVoltage)
{
tmp32 |= ADC_CFG_VREF1RNG_MASK;
}
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
if (config->enableAnalogPreliminary)
{
tmp32 |= ADC_CFG_PWREN_MASK;
}
tmp32 |= ADC_CFG_PUDLY(config->powerUpDelay) /* Power up delay. */
| ADC_CFG_REFSEL(config->referenceVoltageSource) /* Reference voltage. */
| ADC_CFG_PWRSEL(config->powerLevelMode) /* Power configuration. */
| ADC_CFG_TPRICTRL(config->triggerPrioirtyPolicy); /* Trigger priority policy. */
base->CFG = tmp32;
/* ADCx_PAUSE. */
if (config->enableConvPause)
{
base->PAUSE = ADC_PAUSE_PAUSEEN_MASK | ADC_PAUSE_PAUSEDLY(config->convPauseDelay);
}
else
{
base->PAUSE = 0U;
}
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/* ADCx_FCTRL0. */
base->FCTRL[0] = ADC_FCTRL_FWMARK(config->FIFO0Watermark);
/* ADCx_FCTRL1. */
base->FCTRL[1] = ADC_FCTRL_FWMARK(config->FIFO1Watermark);
#else
/* ADCx_FCTRL. */
base->FCTRL = ADC_FCTRL_FWMARK(config->FIFOWatermark);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/* Enable the module after setting configuration. */
LPADC_Enable(base, true);
}
/*!
* brief Gets an available pre-defined settings for initial configuration.
*
* This function initializes the converter configuration structure with an available settings. The default values are:
* code
* config->enableInDozeMode = true;
* config->conversionAverageMode = kLPADC_ConversionAverage1;
* config->enableAnalogPreliminary = false;
* config->powerUpDelay = 0x80;
* config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
* config->powerLevelMode = kLPADC_PowerLevelAlt1;
* config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
* config->enableConvPause = false;
* config->convPauseDelay = 0U;
* config->FIFO0Watermark = 0U;
* config->FIFO1Watermark = 0U;
* config->FIFOWatermark = 0U;
* endcode
* param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConfig(lpadc_config_t *config)
{
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
config->enableInternalClock = false;
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
config->enableVref1LowVoltage = false;
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
config->enableInDozeMode = true;
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
/* Set calibration average mode. */
config->conversionAverageMode = kLPADC_ConversionAverage1;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
config->enableAnalogPreliminary = false;
config->powerUpDelay = 0x80;
config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
config->powerLevelMode = kLPADC_PowerLevelAlt1;
config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
config->enableConvPause = false;
config->convPauseDelay = 0U;
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
config->FIFO0Watermark = 0U;
config->FIFO1Watermark = 0U;
#else
config->FIFOWatermark = 0U;
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
}
/*!
* brief De-initializes the LPADC module.
*
* param base LPADC peripheral base address.
*/
void LPADC_Deinit(ADC_Type *base)
{
/* Disable the module. */
LPADC_Enable(base, false);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Gate the clock. */
CLOCK_DisableClock(s_lpadcClocks[LPADC_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/*!
* brief Get the result in conversion FIFOn.
*
* param base LPADC peripheral base address.
* param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
* param index Result FIFO index.
*
* return Status whether FIFOn entry is valid.
*/
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index)
{
assert(result != NULL); /* Check if the input pointer is available. */
uint32_t tmp32;
tmp32 = base->RESFIFO[index];
if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
{
return false; /* FIFO is empty. Discard any read from RESFIFO. */
}
result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
return true;
}
#else
/*!
* brief Get the result in conversion FIFO.
*
* param base LPADC peripheral base address.
* param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
*
* return Status whether FIFO entry is valid.
*/
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result)
{
assert(result != NULL); /* Check if the input pointer is available. */
uint32_t tmp32;
tmp32 = base->RESFIFO;
if (0U == (ADC_RESFIFO_VALID_MASK & tmp32))
{
return false; /* FIFO is empty. Discard any read from RESFIFO. */
}
result->commandIdSource = (tmp32 & ADC_RESFIFO_CMDSRC_MASK) >> ADC_RESFIFO_CMDSRC_SHIFT;
result->loopCountIndex = (tmp32 & ADC_RESFIFO_LOOPCNT_MASK) >> ADC_RESFIFO_LOOPCNT_SHIFT;
result->triggerIdSource = (tmp32 & ADC_RESFIFO_TSRC_MASK) >> ADC_RESFIFO_TSRC_SHIFT;
result->convValue = (uint16_t)(tmp32 & ADC_RESFIFO_D_MASK);
return true;
}
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/*!
* brief Configure the conversion trigger source.
*
* Each programmable trigger can launch the conversion command in command buffer.
*
* param base LPADC peripheral base address.
* param triggerId ID for each trigger. Typically, the available value range is from 0.
* param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
*/
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config)
{
assert(triggerId < ADC_TCTRL_COUNT); /* Check if the triggerId is available in this device. */
assert(config != NULL); /* Check if the input pointer is available. */
uint32_t tmp32;
tmp32 = ADC_TCTRL_TCMD(config->targetCommandId) /* Trigger command select. */
| ADC_TCTRL_TDLY(config->delayPower) /* Trigger delay select. */
| ADC_TCTRL_TPRI(config->priority) /* Trigger priority setting. */
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
| ADC_TCTRL_FIFO_SEL_A(config->channelAFIFOSelect) | ADC_TCTRL_FIFO_SEL_B(config->channelBFIFOSelect)
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
;
if (config->enableHardwareTrigger)
{
tmp32 |= ADC_TCTRL_HTEN_MASK;
}
base->TCTRL[triggerId] = tmp32;
}
/*!
* brief Gets an available pre-defined settings for trigger's configuration.
*
* This function initializes the trigger's configuration structure with an available settings. The default values are:
* code
* config->commandIdSource = 0U;
* config->loopCountIndex = 0U;
* config->triggerIdSource = 0U;
* config->enableHardwareTrigger = false;
* config->channelAFIFOSelect = 0U;
* config->channelBFIFOSelect = 0U;
* endcode
* param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config)
{
assert(config != NULL); /* Check if the input pointer is available. */
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
config->targetCommandId = 0U;
config->delayPower = 0U;
config->priority = 0U;
#if defined(FSL_FEATURE_LPADC_FIFO_COUNT) && FSL_FEATURE_LPADC_FIFO_COUNT
config->channelAFIFOSelect = 0U;
config->channelBFIFOSelect = 0U;
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
config->enableHardwareTrigger = false;
}
/*!
* brief Configure conversion command.
*
* param base LPADC peripheral base address.
* param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
* param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
*/
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config)
{
assert(commandId < (ADC_CMDL_COUNT + 1U)); /* Check if the commandId is available on this device. */
assert(config != NULL); /* Check if the input pointer is available. */
uint32_t tmp32 = 0;
commandId--; /* The available command number are 1-15, while the index of register group are 0-14. */
/* ADCx_CMDL. */
tmp32 = ADC_CMDL_ADCH(config->channelNumber); /* Channel number. */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
tmp32 |= ADC_CMDL_CSCALE(config->sampleScaleMode); /* Full/Part scale input voltage. */
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
tmp32 |= ADC_CMDL_CTYPE(config->sampleChannelMode);
#else
switch (config->sampleChannelMode) /* Sample input. */
{
case kLPADC_SampleChannelSingleEndSideB:
tmp32 |= ADC_CMDL_ABSEL_MASK;
break;
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
case kLPADC_SampleChannelDiffBothSideAB:
tmp32 |= ADC_CMDL_DIFF_MASK;
break;
case kLPADC_SampleChannelDiffBothSideBA:
tmp32 |= ADC_CMDL_ABSEL_MASK | ADC_CMDL_DIFF_MASK;
break;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_DIFF */
default: /* kLPADC_SampleChannelSingleEndSideA. */
break;
}
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CTYPE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
tmp32 |= ADC_CMDL_MODE(config->conversionResoultuionMode);
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
base->CMD[commandId].CMDL = tmp32;
/* ADCx_CMDH. */
tmp32 = ADC_CMDH_NEXT(config->chainedNextCommandNumber) /* Next Command Select. */
| ADC_CMDH_LOOP(config->loopCount) /* Loop Count Select. */
| ADC_CMDH_AVGS(config->hardwareAverageMode) /* Hardware Average Select. */
| ADC_CMDH_STS(config->sampleTimeMode) /* Sample Time Select. */
| ADC_CMDH_CMPEN(config->hardwareCompareMode); /* Hardware compare enable. */
#if (defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG)
if (config->enableWaitTrigger)
{
tmp32 |= ADC_CMDH_WAIT_TRIG_MASK; /* Wait trigger enable. */
}
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
if (config->enableAutoChannelIncrement)
{
tmp32 |= ADC_CMDH_LWI_MASK;
}
base->CMD[commandId].CMDH = tmp32;
/* Hardware compare settings.
* Not all Command Buffers have an associated Compare Value register. The compare function is only available on
* Command Buffers that have a corresponding Compare Value register.
*/
if (kLPADC_HardwareCompareDisabled != config->hardwareCompareMode)
{
/* Check if the hardware compare feature is available for indicated command buffer. */
assert(commandId < ADC_CV_COUNT);
/* Set CV register. */
base->CV[commandId] = ADC_CV_CVH(config->hardwareCompareValueHigh) /* Compare value high. */
| ADC_CV_CVL(config->hardwareCompareValueLow); /* Compare value low. */
}
}
/*!
* brief Gets an available pre-defined settings for conversion command's configuration.
*
* This function initializes the conversion command's configuration structure with an available settings. The default
* values are:
* code
* config->sampleScaleMode = kLPADC_SampleFullScale;
* config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA;
* config->channelNumber = 0U;
* config->chainedNextCmdNumber = 0U;
* config->enableAutoChannelIncrement = false;
* config->loopCount = 0U;
* config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
* config->sampleTimeMode = kLPADC_SampleTimeADCK3;
* config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
* config->hardwareCompareValueHigh = 0U;
* config->hardwareCompareValueLow = 0U;
* config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
* config->enableWaitTrigger = false;
* endcode
* param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config)
{
assert(config != NULL); /* Check if the input pointer is available. */
/* Initializes the configure structure to zero. */
memset(config, 0, sizeof(*config));
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
config->sampleScaleMode = kLPADC_SampleFullScale;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
config->sampleChannelMode = kLPADC_SampleChannelSingleEndSideA;
config->channelNumber = 0U;
config->chainedNextCommandNumber = 0U; /* No next command defined. */
config->enableAutoChannelIncrement = false;
config->loopCount = 0U;
config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
config->sampleTimeMode = kLPADC_SampleTimeADCK3;
config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
config->hardwareCompareValueHigh = 0U; /* No used. */
config->hardwareCompareValueLow = 0U; /* No used. */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
config->enableWaitTrigger = false;
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
}
#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
/*!
* brief Enable the calibration function.
*
* When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
* a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
* between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
* bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
* OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
*
* param base LPADC peripheral base address.
* bool enable switcher to the calibration function.
*/
void LPADC_EnableCalibration(ADC_Type *base, bool enable)
{
LPADC_Enable(base, false);
if (enable)
{
base->CFG |= ADC_CFG_CALOFS_MASK;
}
else
{
base->CFG &= ~ADC_CFG_CALOFS_MASK;
}
LPADC_Enable(base, true);
}
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
/*!
* brief Do auto calibration.
*
* Calibration function should be executed before using converter in application. It used the software trigger and a
* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:
* -LPADC_EnableCalibration(...)
* -LPADC_LPADC_SetOffsetValue(...)
* -LPADC_SetConvCommandConfig(...)
* -LPADC_SetConvTriggerConfig(...)
*
* param base LPADC peripheral base address.
*/
void LPADC_DoAutoCalibration(ADC_Type *base)
{
assert(0u == LPADC_GetConvResultCount(base));
uint32_t mLpadcCMDL;
uint32_t mLpadcCMDH;
uint32_t mLpadcTrigger;
lpadc_conv_trigger_config_t mLpadcTriggerConfigStruct;
lpadc_conv_command_config_t mLpadcCommandConfigStruct;
lpadc_conv_result_t mLpadcResultConfigStruct;
/* Enable the calibration function. */
LPADC_EnableCalibration(base, true);
/* Keep the CMD and TRG state here and restore it later if the calibration completes.*/
mLpadcCMDL = base->CMD[0].CMDL; /* CMD1L. */
mLpadcCMDH = base->CMD[0].CMDH; /* CMD1H. */
mLpadcTrigger = base->TCTRL[0]; /* Trigger0. */
/* Set trigger0 configuration - for software trigger. */
LPADC_GetDefaultConvTriggerConfig(&mLpadcTriggerConfigStruct);
mLpadcTriggerConfigStruct.targetCommandId = 1U; /* CMD1 is executed. */
LPADC_SetConvTriggerConfig(base, 0U, &mLpadcTriggerConfigStruct); /* Configurate the trigger0. */
/* Set conversion CMD configuration. */
LPADC_GetDefaultConvCommandConfig(&mLpadcCommandConfigStruct);
mLpadcCommandConfigStruct.hardwareAverageMode = kLPADC_HardwareAverageCount128;
LPADC_SetConvCommandConfig(base, 1U, &mLpadcCommandConfigStruct); /* Set CMD1 configuration. */
/* Do calibration. */
LPADC_DoSoftwareTrigger(base, 1U); /* 1U is trigger0 mask. */
while (!LPADC_GetConvResult(base, &mLpadcResultConfigStruct))
{
}
/* The valid bits of data are bits 14:3 in the RESFIFO register. */
LPADC_SetOffsetValue(base, (mLpadcResultConfigStruct.convValue) >> 3U);
/* Disable the calibration function. */
LPADC_EnableCalibration(base, false);
/* restore CMD and TRG registers. */
base->CMD[0].CMDL = mLpadcCMDL; /* CMD1L. */
base->CMD[0].CMDH = mLpadcCMDH; /* CMD1H. */
base->TCTRL[0] = mLpadcTrigger; /* Trigger0. */
}
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
/*!
* brief Do offset calibration.
*
* param base LPADC peripheral base address.
*/
void LPADC_DoOffsetCalibration(ADC_Type *base)
{
LPADC_EnableOffsetCalibration(base, true);
while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
{
}
}
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
/*!
* brief Do auto calibration.
*
* param base LPADC peripheral base address.
*/
void LPADC_DoAutoCalibration(ADC_Type *base)
{
assert((0u == LPADC_GetConvResultCount(base, 0)) && (0u == LPADC_GetConvResultCount(base, 1)));
uint32_t GCCa;
uint32_t GCCb;
uint32_t GCRa;
uint32_t GCRb;
/* Request gain calibration. */
base->CTRL |= ADC_CTRL_CAL_REQ_MASK;
while ((ADC_GCC_RDY_MASK != (base->GCC[0] & ADC_GCC_RDY_MASK)) ||
(ADC_GCC_RDY_MASK != (base->GCC[1] & ADC_GCC_RDY_MASK)))
{
}
/* Calculate gain offset. */
GCCa = (base->GCC[0] & ADC_GCC_GAIN_CAL_MASK);
GCCb = (base->GCC[1] & ADC_GCC_GAIN_CAL_MASK);
GCRa = (uint16_t)((GCCa << 16U) /
(0xFFFFU - GCCa)); /* Gain_CalA = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[0])). */
GCRb = (uint16_t)((GCCb << 16U) /
(0xFFFFU - GCCb)); /* Gain_CalB = (65536 / (65536-(ADC_GCC_GAIN_CAL(ADC0->GCC[1])). */
base->GCR[0] = ADC_GCR_GCALR(GCRa);
base->GCR[1] = ADC_GCR_GCALR(GCRb);
/* Indicate the values are valid. */
base->GCR[0] |= ADC_GCR_RDY_MASK;
base->GCR[1] |= ADC_GCR_RDY_MASK;
while (ADC_STAT_CAL_RDY_MASK != (base->STAT & ADC_STAT_CAL_RDY_MASK))
{
}
}
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_LPADC_H_
#define _FSL_LPADC_H_
#include "fsl_common.h"
/*!
* @addtogroup lpadc
* @{
*/
/*! @file */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief LPADC driver version 2.0.3. */
#define FSL_LPADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 3))
/*@}*/
/*!
* @brief Define the MACRO function to get command status from status value.
*
* The statusVal is the return value from LPADC_GetStatusFlags().
*/
#define LPADC_GET_ACTIVE_COMMAND_STATUS(statusVal) ((statusVal & ADC_STAT_CMDACT_MASK) >> ADC_STAT_CMDACT_SHIFT)
/*!
* @brief Define the MACRO function to get trigger status from status value.
*
* The statusVal is the return value from LPADC_GetStatusFlags().
*/
#define LPADC_GET_ACTIVE_TRIGGER_STATUE(statusVal) ((statusVal & ADC_STAT_TRGACT_MASK) >> ADC_STAT_TRGACT_SHIFT)
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/*!
* @brief Define hardware flags of the module.
*/
enum _lpadc_status_flags
{
kLPADC_ResultFIFO0OverflowFlag = ADC_STAT_FOF0_MASK, /*!< Indicates that more data has been written to the Result
FIFO 0 than it can hold. */
kLPADC_ResultFIFO0ReadyFlag = ADC_STAT_RDY0_MASK, /*!< Indicates when the number of valid datawords in the result
FIFO 0 is greater than the setting watermark level. */
kLPADC_ResultFIFO1OverflowFlag = ADC_STAT_FOF1_MASK, /*!< Indicates that more data has been written to the Result
FIFO 1 than it can hold. */
kLPADC_ResultFIFO1ReadyFlag = ADC_STAT_RDY1_MASK, /*!< Indicates when the number of valid datawords in the result
FIFO 1 is greater than the setting watermark level. */
};
/*!
* @brief Define interrupt switchers of the module.
*/
enum _lpadc_interrupt_enable
{
kLPADC_ResultFIFO0OverflowInterruptEnable = ADC_IE_FOFIE0_MASK, /*!< Configures ADC to generate overflow interrupt
requests when FOF0 flag is asserted. */
kLPADC_FIFO0WatermarkInterruptEnable = ADC_IE_FWMIE0_MASK, /*!< Configures ADC to generate watermark interrupt
requests when RDY0 flag is asserted. */
kLPADC_ResultFIFO1OverflowInterruptEnable = ADC_IE_FOFIE1_MASK, /*!< Configures ADC to generate overflow interrupt
requests when FOF1 flag is asserted. */
kLPADC_FIFO1WatermarkInterruptEnable = ADC_IE_FWMIE1_MASK, /*!< Configures ADC to generate watermark interrupt
requests when RDY1 flag is asserted. */
};
#else
/*!
* @brief Define hardware flags of the module.
*/
enum _lpadc_status_flags
{
kLPADC_ResultFIFOOverflowFlag = ADC_STAT_FOF_MASK, /*!< Indicates that more data has been written to the Result FIFO
than it can hold. */
kLPADC_ResultFIFOReadyFlag = ADC_STAT_RDY_MASK, /*!< Indicates when the number of valid datawords in the result FIFO
is greater than the setting watermark level. */
};
/*!
* @brief Define interrupt switchers of the module.
*/
enum _lpadc_interrupt_enable
{
kLPADC_ResultFIFOOverflowInterruptEnable = ADC_IE_FOFIE_MASK, /*!< Configures ADC to generate overflow interrupt
requests when FOF flag is asserted. */
kLPADC_FIFOWatermarkInterruptEnable = ADC_IE_FWMIE_MASK, /*!< Configures ADC to generate watermark interrupt
requests when RDY flag is asserted. */
};
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/*!
* @brief Define enumeration of sample scale mode.
*
* The sample scale mode is used to reduce the selected ADC analog channel input voltage level by a factor. The maximum
* possible voltage on the ADC channel input should be considered when selecting a scale mode to ensure that the
* reducing factor always results voltage level at or below the VREFH reference. This reducing capability allows
* conversion of analog inputs higher than VREFH. A-side and B-side channel inputs are both scaled using the scale mode.
*/
typedef enum _lpadc_sample_scale_mode
{
kLPADC_SamplePartScale = 0U, /*!< Use divided input voltage signal. (Factor of 30/64). */
kLPADC_SampleFullScale = 1U, /*!< Full scale (Factor of 1). */
} lpadc_sample_scale_mode_t;
/*!
* @brief Define enumeration of channel sample mode.
*
* The channel sample mode configures the channel with single-end/differential/dual-single-end, side A/B.
*/
typedef enum _lpadc_sample_channel_mode
{
kLPADC_SampleChannelSingleEndSideA = 0U, /*!< Single end mode, using side A. */
kLPADC_SampleChannelSingleEndSideB = 1U, /*!< Single end mode, using side B. */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_DIFF) && FSL_FEATURE_LPADC_HAS_CMDL_DIFF
kLPADC_SampleChannelDiffBothSideAB = 2U, /*!< Differential mode, using A as plus side and B as minue side. */
kLPADC_SampleChannelDiffBothSideBA = 3U, /*!< Differential mode, using B as plus side and A as minue side. */
#elif defined(FSL_FEATURE_LPADC_HAS_CMDL_CTYPE) && FSL_FEATURE_LPADC_HAS_CMDL_CTYPE
kLPADC_SampleChannelDiffBothSide = 2U, /*!< Differential mode, using A and B. */
kLPADC_SampleChannelDualSingleEndBothSide =
3U, /*!< Dual-Single-Ended Mode. Both A side and B side channels are converted independently. */
#endif
} lpadc_sample_channel_mode_t;
/*!
* @brief Define enumeration of hardware average selection.
*
* It Selects how many ADC conversions are averaged to create the ADC result. An internal storage buffer is used to
* capture temporary results while the averaging iterations are executed.
*/
typedef enum _lpadc_hardware_average_mode
{
kLPADC_HardwareAverageCount1 = 0U, /*!< Single conversion. */
kLPADC_HardwareAverageCount2 = 1U, /*!< 2 conversions averaged. */
kLPADC_HardwareAverageCount4 = 2U, /*!< 4 conversions averaged. */
kLPADC_HardwareAverageCount8 = 3U, /*!< 8 conversions averaged. */
kLPADC_HardwareAverageCount16 = 4U, /*!< 16 conversions averaged. */
kLPADC_HardwareAverageCount32 = 5U, /*!< 32 conversions averaged. */
kLPADC_HardwareAverageCount64 = 6U, /*!< 64 conversions averaged. */
kLPADC_HardwareAverageCount128 = 7U, /*!< 128 conversions averaged. */
} lpadc_hardware_average_mode_t;
/*!
* @brief Define enumeration of sample time selection.
*
* The shortest sample time maximizes conversion speed for lower impedance inputs. Extending sample time allows higher
* impedance inputs to be accurately sampled. Longer sample times can also be used to lower overall power consumption
* when command looping and sequencing is configured and high conversion rates are not required.
*/
typedef enum _lpadc_sample_time_mode
{
kLPADC_SampleTimeADCK3 = 0U, /*!< 3 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK5 = 1U, /*!< 5 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK7 = 2U, /*!< 7 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK11 = 3U, /*!< 11 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK19 = 4U, /*!< 19 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK35 = 5U, /*!< 35 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK67 = 6U, /*!< 69 ADCK cycles total sample time. */
kLPADC_SampleTimeADCK131 = 7U, /*!< 131 ADCK cycles total sample time. */
} lpadc_sample_time_mode_t;
/*!
* @brief Define enumeration of hardware compare mode.
*
* After an ADC channel input is sampled and converted and any averaging iterations are performed, this mode setting
* guides operation of the automatic compare function to optionally only store when the compare operation is true.
* When compare is enabled, the conversion result is compared to the compare values.
*/
typedef enum _lpadc_hardware_compare_mode
{
kLPADC_HardwareCompareDisabled = 0U, /*!< Compare disabled. */
kLPADC_HardwareCompareStoreOnTrue = 2U, /*!< Compare enabled. Store on true. */
kLPADC_HardwareCompareRepeatUntilTrue = 3U, /*!< Compare enabled. Repeat channel acquisition until true. */
} lpadc_hardware_compare_mode_t;
/*!
* @brief Define enumeration of conversion resolution mode.
*
* Configure the resolution bit in specific conversion type. For detailed resolution accuracy, see to
* #_lpadc_sample_channel_mode
*/
typedef enum _lpadc_conversion_resolution_mode
{
kLPADC_ConversionResolutionStandard = 0U, /*!< Standard resolution. Single-ended 12-bit conversion, Differential
13-bit conversion with 2’s complement output. */
kLPADC_ConversionResolutionHigh = 1U, /*!< High resolution. Single-ended 16-bit conversion; Differential 16-bit
conversion with 2’s complement output. */
} lpadc_conversion_resolution_mode_t;
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
/*!
* @brief Define enumeration of conversion averages mode.
*
* Configure the converion average number for auto-calibration.
*/
typedef enum _lpadc_conversion_average_mode
{
kLPADC_ConversionAverage1 = 0U, /*!< Single conversion. */
kLPADC_ConversionAverage2 = 1U, /*!< 2 conversions averaged. */
kLPADC_ConversionAverage4 = 2U, /*!< 4 conversions averaged. */
kLPADC_ConversionAverage8 = 3U, /*!< 8 conversions averaged. */
kLPADC_ConversionAverage16 = 4U, /*!< 16 conversions averaged. */
kLPADC_ConversionAverage32 = 5U, /*!< 32 conversions averaged. */
kLPADC_ConversionAverage64 = 6U, /*!< 64 conversions averaged. */
kLPADC_ConversionAverage128 = 7U, /*!< 128 conversions averaged. */
} lpadc_conversion_average_mode_t;
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
/*!
* @brief Define enumeration of reference voltage source.
*
* For detail information, need to check the SoC's specification.
*/
typedef enum _lpadc_reference_voltage_mode
{
kLPADC_ReferenceVoltageAlt1 = 0U, /*!< Option 1 setting. */
kLPADC_ReferenceVoltageAlt2 = 1U, /*!< Option 2 setting. */
kLPADC_ReferenceVoltageAlt3 = 2U, /*!< Option 3 setting. */
} lpadc_reference_voltage_source_t;
/*!
* @brief Define enumeration of power configuration.
*
* Configures the ADC for power and performance. In the highest power setting the highest conversion rates will be
* possible. Refer to the device data sheet for power and performance capabilities for each setting.
*/
typedef enum _lpadc_power_level_mode
{
kLPADC_PowerLevelAlt1 = 0U, /*!< Lowest power setting. */
kLPADC_PowerLevelAlt2 = 1U, /*!< Next lowest power setting. */
kLPADC_PowerLevelAlt3 = 2U, /*!< ... */
kLPADC_PowerLevelAlt4 = 3U, /*!< Highest power setting. */
} lpadc_power_level_mode_t;
/*!
* @brief Define enumeration of trigger priority policy.
*
* This selection controls how higher priority triggers are handled.
*/
typedef enum _lpadc_trigger_priority_policy
{
kLPADC_TriggerPriorityPreemptImmediately = 0U, /*!< If a higher priority trigger is detected during command
processing, the current conversion is aborted and the new
command specified by the trigger is started. */
kLPADC_TriggerPriorityPreemptSoftly = 1U, /*!< If a higher priority trigger is received during command processing,
the current conversion is completed (including averaging iterations
and compare function if enabled) and stored to the result FIFO
before the higher priority trigger/command is initiated. */
kLPADC_TriggerPriorityPreemptSubsequently =
2U, /*!< If a higher priority trigger is received during command processing, the current
command will be completed (averaging, looping, compare) before servicing the
higher priority trigger. */
} lpadc_trigger_priority_policy_t;
/*!
* @beief LPADC global configuration.
*
* This structure would used to keep the settings for initialization.
*/
typedef struct
{
#if defined(FSL_FEATURE_LPADC_HAS_CFG_ADCKEN) && FSL_FEATURE_LPADC_HAS_CFG_ADCKEN
bool enableInternalClock; /*!< Enables the internally generated clock source. The clock source is used in clock
selection logic at the chip level and is optionally used for the ADC clock source. */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_ADCKEN */
#if defined(FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG) && FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG
bool enableVref1LowVoltage; /*!< If voltage reference option1 input is below 1.8V, it should be "true".
If voltage reference option1 input is above 1.8V, it should be "false". */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_VREF1RNG */
bool enableInDozeMode; /*!< Control system transition to Stop and Wait power modes while ADC is converting. When
enabled in Doze mode, immediate entries to Wait or Stop are allowed. When disabled, the
ADC will wait for the current averaging iteration/FIFO storage to complete before
acknowledging stop or wait mode entry. */
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS
lpadc_conversion_average_mode_t conversionAverageMode; /*!< Auto-Calibration Averages. */
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_AVGS */
bool enableAnalogPreliminary; /*!< ADC analog circuits are pre-enabled and ready to execute conversions without
startup delays(at the cost of higher DC current consumption). */
uint32_t powerUpDelay; /*!< When the analog circuits are not pre-enabled, the ADC analog circuits are only powered
while the ADC is active and there is a counted delay defined by this field after an
initial trigger transitions the ADC from its Idle state to allow time for the analog
circuits to stabilize. The startup delay count of (powerUpDelay * 4) ADCK cycles must
result in a longer delay than the analog startup time. */
lpadc_reference_voltage_source_t referenceVoltageSource; /*!< Selects the voltage reference high used for
conversions.*/
lpadc_power_level_mode_t powerLevelMode; /*!< Power Configuration Selection. */
lpadc_trigger_priority_policy_t triggerPrioirtyPolicy; /*!< Control how higher priority triggers are handled, see to
#lpadc_trigger_priority_policy_mode_t. */
bool enableConvPause; /*!< Enables the ADC pausing function. When enabled, a programmable delay is inserted during
command execution sequencing between LOOP iterations, between commands in a sequence, and
between conversions when command is executing in "Compare Until True" configuration. */
uint32_t convPauseDelay; /*!< Controls the duration of pausing during command execution sequencing. The pause delay
is a count of (convPauseDelay*4) ADCK cycles. Only available when ADC pausing
function is enabled. The available value range is in 9-bit. */
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/* for FIFO0. */
uint32_t
FIFO0Watermark; /*!< FIFO0Watermark is a programmable threshold setting. When the number of datawords stored
in the ADC Result FIFO0 is greater than the value in this field, the ready flag would be
asserted to indicate stored data has reached the programmable threshold. */
/* for FIFO1. */
uint32_t
FIFO1Watermark; /*!< FIFO1Watermark is a programmable threshold setting. When the number of datawords stored
in the ADC Result FIFO1 is greater than the value in this field, the ready flag would be
asserted to indicate stored data has reached the programmable threshold. */
#else
/* for FIFO. */
uint32_t FIFOWatermark; /*!< FIFOWatermark is a programmable threshold setting. When the number of datawords stored
in the ADC Result FIFO is greater than the value in this field, the ready flag would be
asserted to indicate stored data has reached the programmable threshold. */
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
} lpadc_config_t;
/*!
* @brief Define structure to keep the configuration for conversion command.
*/
typedef struct
{
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_CSCALE) && FSL_FEATURE_LPADC_HAS_CMDL_CSCALE
lpadc_sample_scale_mode_t sampleScaleMode; /*!< Sample scale mode. */
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_CSCALE */
lpadc_sample_channel_mode_t sampleChannelMode; /*!< Channel sample mode. */
uint32_t channelNumber; /*!< Channel number, select the channel or channel pair. */
uint32_t chainedNextCommandNumber; /*!< Selects the next command to be executed after this command completes.
1-15 is available, 0 is to terminate the chain after this command. */
bool enableAutoChannelIncrement; /*!< Loop with increment: when disabled, the "loopCount" field selects the number
of times the selected channel is converted consecutively; when enabled, the
"loopCount" field defines how many consecutive channels are converted as part
of the command execution. */
uint32_t loopCount; /*!< Selects how many times this command executes before finish and transition to the next
command or Idle state. Command executes LOOP+1 times. 0-15 is available. */
lpadc_hardware_average_mode_t hardwareAverageMode; /*!< Hardware average selection. */
lpadc_sample_time_mode_t sampleTimeMode; /*!< Sample time selection. */
lpadc_hardware_compare_mode_t hardwareCompareMode; /*!< Hardware compare selection. */
uint32_t hardwareCompareValueHigh; /*!< Compare Value High. The available value range is in 16-bit. */
uint32_t hardwareCompareValueLow; /*!< Compare Value Low. The available value range is in 16-bit. */
#if defined(FSL_FEATURE_LPADC_HAS_CMDL_MODE) && FSL_FEATURE_LPADC_HAS_CMDL_MODE
lpadc_conversion_resolution_mode_t conversionResoultuionMode; /*!< Conversion resolution mode. */
#endif /* FSL_FEATURE_LPADC_HAS_CMDL_MODE */
#if defined(FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG) && FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG
bool enableWaitTrigger; /*!< Wait for trigger assertion before execution: when disabled, this command will be
automatically executed; when enabled, the active trigger must be asserted again before
executing this command. */
#endif /* FSL_FEATURE_LPADC_HAS_CMDH_WAIT_TRIG */
} lpadc_conv_command_config_t;
/*!
* @brief Define structure to keep the configuration for conversion trigger.
*/
typedef struct
{
uint32_t targetCommandId; /*!< Select the command from command buffer to execute upon detect of the associated
trigger event. */
uint32_t delayPower; /*!< Select the trigger delay duration to wait at the start of servicing a trigger event.
When this field is clear, then no delay is incurred. When this field is set to a non-zero
value, the duration for the delay is 2^delayPower ADCK cycles. The available value range
is 4-bit. */
uint32_t priority; /*!< Sets the priority of the associated trigger source. If two or more triggers have the same
priority level setting, the lower order trigger event has the higher priority. The lower
value for this field is for the higher priority, the available value range is 1-bit. */
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
uint8_t channelAFIFOSelect; /* SAR Result Destination For Channel A. */
uint8_t channelBFIFOSelect; /* SAR Result Destination For Channel B. */
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
bool enableHardwareTrigger; /*!< Enable hardware trigger source to initiate conversion on the rising edge of the
input trigger source or not. THe software trigger is always available. */
} lpadc_conv_trigger_config_t;
/*!
* @brief Define the structure to keep the conversion result.
*/
typedef struct
{
uint32_t commandIdSource; /*!< Indicate the command buffer being executed that generated this result. */
uint32_t loopCountIndex; /*!< Indicate the loop count value during command execution that generated this result. */
uint32_t triggerIdSource; /*!< Indicate the trigger source that initiated a conversion and generated this result. */
uint16_t convValue; /*!< Data result. */
} lpadc_conv_result_t;
#if defined(__cplusplus)
extern "C" {
#endif
/*******************************************************************************
* API
******************************************************************************/
/*!
* @name Initialization & de-initialization.
* @{
*/
/*!
* @brief Initializes the LPADC module.
*
* @param base LPADC peripheral base address.
* @param config Pointer to configuration structure. See "lpadc_config_t".
*/
void LPADC_Init(ADC_Type *base, const lpadc_config_t *config);
/*!
* @brief Gets an available pre-defined settings for initial configuration.
*
* This function initializes the converter configuration structure with an available settings. The default values are:
* @code
* config->enableInDozeMode = true;
* config->enableAnalogPreliminary = false;
* config->powerUpDelay = 0x80;
* config->referenceVoltageSource = kLPADC_ReferenceVoltageAlt1;
* config->powerLevelMode = kLPADC_PowerLevelAlt1;
* config->triggerPrioirtyPolicy = kLPADC_TriggerPriorityPreemptImmediately;
* config->enableConvPause = false;
* config->convPauseDelay = 0U;
* config->FIFOWatermark = 0U;
* @endcode
* @param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConfig(lpadc_config_t *config);
/*!
* @brief De-initializes the LPADC module.
*
* @param base LPADC peripheral base address.
*/
void LPADC_Deinit(ADC_Type *base);
/*!
* @brief Switch on/off the LPADC module.
*
* @param base LPADC peripheral base address.
* @param enable switcher to the module.
*/
static inline void LPADC_Enable(ADC_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= ADC_CTRL_ADCEN_MASK;
}
else
{
base->CTRL &= ~ADC_CTRL_ADCEN_MASK;
}
}
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/*!
* @brief Do reset the conversion FIFO0.
*
* @param base LPADC peripheral base address.
*/
static inline void LPADC_DoResetFIFO0(ADC_Type *base)
{
base->CTRL |= ADC_CTRL_RSTFIFO0_MASK;
}
/*!
* @brief Do reset the conversion FIFO1.
*
* @param base LPADC peripheral base address.
*/
static inline void LPADC_DoResetFIFO1(ADC_Type *base)
{
base->CTRL |= ADC_CTRL_RSTFIFO1_MASK;
}
#else
/*!
* @brief Do reset the conversion FIFO.
*
* @param base LPADC peripheral base address.
*/
static inline void LPADC_DoResetFIFO(ADC_Type *base)
{
base->CTRL |= ADC_CTRL_RSTFIFO_MASK;
}
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/*!
* @brief Do reset the module's configuration.
*
* Reset all ADC internal logic and registers, except the Control Register (ADCx_CTRL).
*
* @param base LPADC peripheral base address.
*/
static inline void LPADC_DoResetConfig(ADC_Type *base)
{
base->CTRL |= ADC_CTRL_RST_MASK;
base->CTRL &= ~ADC_CTRL_RST_MASK;
}
/* @} */
/*!
* @name Status
* @{
*/
/*!
* @brief Get status flags.
*
* @param base LPADC peripheral base address.
* @return status flags' mask. See to #_lpadc_status_flags.
*/
static inline uint32_t LPADC_GetStatusFlags(ADC_Type *base)
{
return base->STAT;
}
/*!
* @brief Clear status flags.
*
* Only the flags can be cleared by writing ADCx_STATUS register would be cleared by this API.
*
* @param base LPADC peripheral base address.
* @param mask Mask value for flags to be cleared. See to #_lpadc_status_flags.
*/
static inline void LPADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
{
base->STAT = mask;
}
/* @} */
/*!
* @name Interrupts
* @{
*/
/*!
* @brief Enable interrupts.
*
* @param base LPADC peripheral base address.
* @mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
*/
static inline void LPADC_EnableInterrupts(ADC_Type *base, uint32_t mask)
{
base->IE |= mask;
}
/*!
* @brief Disable interrupts.
*
* @param base LPADC peripheral base address.
* @param mask Mask value for interrupt events. See to #_lpadc_interrupt_enable.
*/
static inline void LPADC_DisableInterrupts(ADC_Type *base, uint32_t mask)
{
base->IE &= ~mask;
}
/*!
* @name DMA Control
* @{
*/
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/*!
* @brief Switch on/off the DMA trigger for FIFO0 watermark event.
*
* @param base LPADC peripheral base address.
* @param enable Switcher to the event.
*/
static inline void LPADC_EnableFIFO0WatermarkDMA(ADC_Type *base, bool enable)
{
if (enable)
{
base->DE |= ADC_DE_FWMDE0_MASK;
}
else
{
base->DE &= ~ADC_DE_FWMDE0_MASK;
}
}
/*!
* @brief Switch on/off the DMA trigger for FIFO1 watermark event.
*
* @param base LPADC peripheral base address.
* @param enable Switcher to the event.
*/
static inline void LPADC_EnableFIFO1WatermarkDMA(ADC_Type *base, bool enable)
{
if (enable)
{
base->DE |= ADC_DE_FWMDE1_MASK;
}
else
{
base->DE &= ~ADC_DE_FWMDE1_MASK;
}
}
#else
/*!
* @brief Switch on/off the DMA trigger for FIFO watermark event.
*
* @param base LPADC peripheral base address.
* @param enable Switcher to the event.
*/
static inline void LPADC_EnableFIFOWatermarkDMA(ADC_Type *base, bool enable)
{
if (enable)
{
base->DE |= ADC_DE_FWMDE_MASK;
}
else
{
base->DE &= ~ADC_DE_FWMDE_MASK;
}
}
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/* @} */
/*!
* @name Trigger and conversion with FIFO.
* @{
*/
#if (defined(FSL_FEATURE_LPADC_FIFO_COUNT) && (FSL_FEATURE_LPADC_FIFO_COUNT == 2))
/*!
* @brief Get the count of result kept in conversion FIFOn.
*
* @param base LPADC peripheral base address.
* @param index Result FIFO index.
* @return The count of result kept in conversion FIFOn.
*/
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base, uint8_t index)
{
return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL[index]) >> ADC_FCTRL_FCOUNT_SHIFT;
}
/*!
* brief Get the result in conversion FIFOn.
*
* param base LPADC peripheral base address.
* param result Pointer to structure variable that keeps the conversion result in conversion FIFOn.
* param index Result FIFO index.
*
* return Status whether FIFOn entry is valid.
*/
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result, uint8_t index);
#else
/*!
* @brief Get the count of result kept in conversion FIFO.
*
* @param base LPADC peripheral base address.
* @return The count of result kept in conversion FIFO.
*/
static inline uint32_t LPADC_GetConvResultCount(ADC_Type *base)
{
return (ADC_FCTRL_FCOUNT_MASK & base->FCTRL) >> ADC_FCTRL_FCOUNT_SHIFT;
}
/*!
* @brief Get the result in conversion FIFO.
*
* @param base LPADC peripheral base address.
* @param result Pointer to structure variable that keeps the conversion result in conversion FIFO.
*
* @return Status whether FIFO entry is valid.
*/
bool LPADC_GetConvResult(ADC_Type *base, lpadc_conv_result_t *result);
#endif /* FSL_FEATURE_LPADC_FIFO_COUNT */
/*!
* @brief Configure the conversion trigger source.
*
* Each programmable trigger can launch the conversion command in command buffer.
*
* @param base LPADC peripheral base address.
* @param triggerId ID for each trigger. Typically, the available value range is from 0.
* @param config Pointer to configuration structure. See to #lpadc_conv_trigger_config_t.
*/
void LPADC_SetConvTriggerConfig(ADC_Type *base, uint32_t triggerId, const lpadc_conv_trigger_config_t *config);
/*!
* @brief Gets an available pre-defined settings for trigger's configuration.
*
* This function initializes the trigger's configuration structure with an available settings. The default values are:
* @code
* config->commandIdSource = 0U;
* config->loopCountIndex = 0U;
* config->triggerIdSource = 0U;
* config->enableHardwareTrigger = false;
* @endcode
* @param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConvTriggerConfig(lpadc_conv_trigger_config_t *config);
/*!
* @brief Do software trigger to conversion command.
*
* @param base LPADC peripheral base address.
* @param triggerIdMask Mask value for software trigger indexes, which count from zero.
*/
static inline void LPADC_DoSoftwareTrigger(ADC_Type *base, uint32_t triggerIdMask)
{
/* Writes to ADCx_SWTRIG register are ignored while ADCx_CTRL[ADCEN] is clear. */
base->SWTRIG = triggerIdMask;
}
/*!
* @brief Configure conversion command.
*
* @param base LPADC peripheral base address.
* @param commandId ID for command in command buffer. Typically, the available value range is 1 - 15.
* @param config Pointer to configuration structure. See to #lpadc_conv_command_config_t.
*/
void LPADC_SetConvCommandConfig(ADC_Type *base, uint32_t commandId, const lpadc_conv_command_config_t *config);
/*!
* @brief Gets an available pre-defined settings for conversion command's configuration.
*
* This function initializes the conversion command's configuration structure with an available settings. The default
* values are:
* @code
* config->sampleScaleMode = kLPADC_SampleFullScale;
* config->channelSampleMode = kLPADC_SampleChannelSingleEndSideA;
* config->channelNumber = 0U;
* config->chainedNextCmdNumber = 0U;
* config->enableAutoChannelIncrement = false;
* config->loopCount = 0U;
* config->hardwareAverageMode = kLPADC_HardwareAverageCount1;
* config->sampleTimeMode = kLPADC_SampleTimeADCK3;
* config->hardwareCompareMode = kLPADC_HardwareCompareDisabled;
* config->hardwareCompareValueHigh = 0U;
* config->hardwareCompareValueLow = 0U;
* config->conversionResoultuionMode = kLPADC_ConversionResolutionStandard;
* config->enableWaitTrigger = false;
* @endcode
* @param config Pointer to configuration structure.
*/
void LPADC_GetDefaultConvCommandConfig(lpadc_conv_command_config_t *config);
#if defined(FSL_FEATURE_LPADC_HAS_CFG_CALOFS) && FSL_FEATURE_LPADC_HAS_CFG_CALOFS
/*!
* @brief Enable the calibration function.
*
* When CALOFS is set, the ADC is configured to perform a calibration function anytime the ADC executes
* a conversion. Any channel selected is ignored and the value returned in the RESFIFO is a signed value
* between -31 and 31. -32 is not a valid and is never a returned value. Software should copy the lower 6-
* bits of the conversion result stored in the RESFIFO after a completed calibration conversion to the
* OFSTRIM field. The OFSTRIM field is used in normal operation for offset correction.
*
* @param base LPADC peripheral base address.
* @bool enable switcher to the calibration function.
*/
void LPADC_EnableCalibration(ADC_Type *base, bool enable);
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
/*!
* @brief Set proper offset value to trim ADC.
*
* To minimize the offset during normal operation, software should read the conversion result from
* the RESFIFO calibration operation and write the lower 6 bits to the OFSTRIM register.
*
* @param base LPADC peripheral base address.
* @param value Setting offset value.
*/
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t value)
{
base->OFSTRIM = (value & ADC_OFSTRIM_OFSTRIM_MASK) >> ADC_OFSTRIM_OFSTRIM_SHIFT;
}
/*!
* @brief Do auto calibration.
*
* Calibration function should be executed before using converter in application. It used the software trigger and a
* dummy conversion, get the offset and write them into the OFSTRIM register. It called some of functional API including:
* -LPADC_EnableCalibration(...)
* -LPADC_LPADC_SetOffsetValue(...)
* -LPADC_SetConvCommandConfig(...)
* -LPADC_SetConvTriggerConfig(...)
*
* @param base LPADC peripheral base address.
*/
void LPADC_DoAutoCalibration(ADC_Type *base);
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
#endif /* FSL_FEATURE_LPADC_HAS_CFG_CALOFS */
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CALOFS) && FSL_FEATURE_LPADC_HAS_CTRL_CALOFS
#if defined(FSL_FEATURE_LPADC_HAS_OFSTRIM) && FSL_FEATURE_LPADC_HAS_OFSTRIM
/*!
* @brief Set proper offset value to trim ADC.
*
* Set the offset trim value for offset calibration manually.
*
* @param base LPADC peripheral base address.
* @param valueA Setting offset value A.
* @param valueB Setting offset value B.
* @note In normal adc sequence, the values are automatically calculated by LPADC_EnableOffsetCalibration.
*/
static inline void LPADC_SetOffsetValue(ADC_Type *base, uint32_t valueA, uint32_t valueB)
{
base->OFSTRIM = ADC_OFSTRIM_OFSTRIM_A(valueA) | ADC_OFSTRIM_OFSTRIM_B(valueB);
}
#endif /* FSL_FEATURE_LPADC_HAS_OFSTRIM */
/*!
* @brief Enable the offset calibration function.
*
* @param base LPADC peripheral base address.
* @bool enable switcher to the calibration function.
*/
static inline void LPADC_EnableOffsetCalibration(ADC_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= ADC_CTRL_CALOFS_MASK;
}
else
{
base->CTRL &= ~ADC_CTRL_CALOFS_MASK;
}
}
/*!
* @brief Do offset calibration.
*
* @param base LPADC peripheral base address.
*/
void LPADC_DoOffsetCalibration(ADC_Type *base);
#if defined(FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ) && FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ
/*!
* brief Do auto calibration.
*
* param base LPADC peripheral base address.
*/
void LPADC_DoAutoCalibration(ADC_Type *base);
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CAL_REQ */
#endif /* FSL_FEATURE_LPADC_HAS_CTRL_CALOFS */
/* @} */
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_LPADC_H_ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_ostimer.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.ostimer"
#endif
/* Typedef for interrupt handler. */
typedef void (*ostimer_isr_t)(OSTIMER_Type *base, ostimer_callback_t cb);
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Gets the instance from the base address
*
* @param base OSTIMER peripheral base address
*
* @return The OSTIMER instance
*/
static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/* Array of OSTIMER handle. */
static ostimer_callback_t s_ostimerHandle[FSL_FEATURE_SOC_OSTIMER_COUNT];
/* Array of OSTIMER peripheral base address. */
static OSTIMER_Type *const s_ostimerBases[] = OSTIMER_BASE_PTRS;
/* Array of OSTIMER IRQ number. */
static const IRQn_Type s_ostimerIRQ[] = OSTIMER_IRQS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Array of OSTIMER clock name. */
static const clock_ip_name_t s_ostimerClock[] = OSTIMER_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Array of OSTIMER reset name. */
static const reset_ip_name_t s_ostimerReset[] = OSTIMER_RSTS;
/* OSTIMER ISR for transactional APIs. */
static ostimer_isr_t s_ostimerIsr;
/*******************************************************************************
* Code
******************************************************************************/
/* @brief Function for getting the instance number of OS timer. */
static uint32_t OSTIMER_GetInstance(OSTIMER_Type *base)
{
uint32_t instance;
/* Find the instance index from base address mappings. */
for (instance = 0; instance < ARRAY_SIZE(s_ostimerBases); instance++)
{
if (s_ostimerBases[instance] == base)
{
break;
}
}
assert(instance < ARRAY_SIZE(s_ostimerBases));
return instance;
}
/* @brief Translate the value from gray-code to decimal. */
static uint64_t OSTIMER_GrayToDecimal(uint64_t gray)
{
uint64_t temp = gray;
while (temp)
{
temp >>= 1U;
gray ^= temp;
}
return gray;
}
/* @brief Translate the value from decimal to gray-code. */
static uint64_t OSTIMER_DecimalToGray(uint64_t dec)
{
return (dec ^ (dec >> 1U));
}
/*!
* @brief Initializes an OSTIMER by turning it's clock on.
*
*/
void OSTIMER_Init(OSTIMER_Type *base)
{
assert(base);
uint32_t instance = OSTIMER_GetInstance(base);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the OSTIMER 32k clock in PMC module. */
PMC->OSTIMERr |= PMC_OSTIMER_CLOCKENABLE_MASK;
PMC->OSTIMERr &= ~PMC_OSTIMER_OSC32KPD_MASK;
/* Enable clock for OSTIMER. */
CLOCK_EnableClock(s_ostimerClock[instance]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_FEATURE_OSTIMER_HAS_NO_RESET) && FSL_FEATURE_OSTIMER_HAS_NO_RESET)
/* Reset the OSTIMER. */
RESET_PeripheralReset(s_ostimerReset[instance]);
#endif
}
/*!
* @brief Deinitializes a OSTIMER instance.
*
* This function shuts down OSTIMER clock
*
* @param base OSTIMER peripheral base address.
*/
void OSTIMER_Deinit(OSTIMER_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable clock for OSTIMER. */
CLOCK_DisableClock(s_ostimerClock[OSTIMER_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
/*!
* @brief Get OSTIMER status Flags.
*
* This returns the status flag.
* Currently, only match interrupt flag can be got.
*
* @param base OSTIMER peripheral base address.
* @return status register value
*/
uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base)
{
return base->OSEVENT_CTRL & OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK;
}
/*!
* @brief Clear Status Interrupt Flags.
*
* This clears intr status flag.
* Currently, only match interrupt flag can be cleared.
*
* @param base OSTIMER peripheral base address.
* @return none
*/
void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask)
{
base->OSEVENT_CTRL |= mask;
}
/*!
* @brief Set the match raw value for OSTIMER.
*
* This function will set a match value for OSTIMER with an optional callback. And this callback
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
* Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue().
*
* @param base OSTIMER peripheral base address.
* @param count OSTIMER timer match value.(Value is gray-code format)
*
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
* @return none
*/
void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)
{
uint64_t tmp = count;
uint32_t instance = OSTIMER_GetInstance(base);
s_ostimerIsr = OSTIMER_HandleIRQ;
s_ostimerHandle[instance] = cb;
/* Set the match value. */
base->MATCHN_L = tmp;
base->MATCHN_H = tmp >> 32U;
/*
* Enable deep sleep IRQ directly for some times the OS timer may run in deep sleep mode.
* Please note that while enabling deep sleep IRQ, the NVIC will be also enabled.
*/
base->OSEVENT_CTRL |= OSTIMER_OSEVENT_CTRL_OSTIMER_INTENA_MASK;
PMC->OSTIMERr |= PMC_OSTIMER_DPDWAKEUPENABLE_MASK;
EnableDeepSleepIRQ(s_ostimerIRQ[instance]);
}
/*!
* @brief Set the match value for OSTIMER.
*
* This function will set a match value for OSTIMER with an optional callback. And this callback
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
*
* @param base OSTIMER peripheral base address.
* @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code in
* API. )
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
* @return none
*/
void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb)
{
uint64_t tmp = OSTIMER_DecimalToGray(count);
OSTIMER_SetMatchRawValue(base, tmp, cb);
}
/*!
* @brief Get current timer count value from OSTIMER.
*
* This function will get a decimal timer count value.
* The RAW value of timer count is gray code format, will be translated to decimal data internally.
*
* @param base OSTIMER peripheral base address.
* @return Value of OSTIMER which will formated to decimal value.
*/
uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base)
{
uint64_t tmp = 0U;
tmp = OSTIMER_GetCurrentTimerRawValue(base);
return OSTIMER_GrayToDecimal(tmp);
}
/*!
* @brief Get the capture value from OSTIMER.
*
* This function will get a capture decimal-value from OSTIMER.
* The RAW value of timer capture is gray code format, will be translated to decimal data internally.
*
* @param base OSTIMER peripheral base address.
* @return Value of capture register, data format is decimal.
*/
uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base)
{
uint64_t tmp = 0U;
tmp = OSTIMER_GetCaptureRawValue(base);
return OSTIMER_GrayToDecimal(tmp);
}
void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb)
{
/* Clear the match interrupt flag. */
OSTIMER_ClearStatusFlags(base, kOSTIMER_MatchInterruptFlag);
if (cb)
{
cb();
}
}
#if defined(OSTIMER)
void OS_EVENT_DriverIRQHandler(void)
{
s_ostimerIsr(OSTIMER, s_ostimerHandle[0]);
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
#endif

219
ext/hal/nxp/mcux/drivers/lpc/fsl_ostimer.h Normal file
View file

@ -0,0 +1,219 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_OSTIMER_H_
#define _FSL_OSTIMER_H_
#include "fsl_common.h"
/*!
* @addtogroup ostimer
* @{
*/
/*! @file*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief OSTIMER driver version 2.0.0. */
#define FSL_OSTIMER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*!
* @brief OSTIMER status flags.
*/
enum _ostimer_flags
{
kOSTIMER_MatchInterruptFlag = (OSTIMER_OSEVENT_CTRL_OSTIMER_INTRFLAG_MASK), /*!< Match interrupt flag bit, sets if
the match value was reached. */
};
/*! @brief ostimer callback function. */
typedef void (*ostimer_callback_t)(void);
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* _cplusplus */
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Initializes an OSTIMER by turning its bus clock on
*
*/
void OSTIMER_Init(OSTIMER_Type *base);
/*!
* @brief Deinitializes a OSTIMER instance.
*
* This function shuts down OSTIMER bus clock
*
* @param base OSTIMER peripheral base address.
*/
void OSTIMER_Deinit(OSTIMER_Type *base);
/*!
* @brief OSTIMER software reset.
*
* This function will use software to trigger an OSTIMER reset.
* Please note that, the OS timer reset bit was in PMC->OSTIMERr register.
*
* @param base OSTIMER peripheral base address.
*/
static inline void OSTIMER_SoftwareReset(OSTIMER_Type *base)
{
PMC->OSTIMERr |= PMC_OSTIMER_SOFTRESET_MASK;
PMC->OSTIMERr &= ~PMC_OSTIMER_SOFTRESET_MASK;
}
/*!
* @brief Get OSTIMER status Flags.
*
* This returns the status flag.
* Currently, only match interrupt flag can be got.
*
* @param base OSTIMER peripheral base address.
* @return status register value
*/
uint32_t OSTIMER_GetStatusFlags(OSTIMER_Type *base);
/*!
* @brief Clear Status Interrupt Flags.
*
* This clears intrrupt status flag.
* Currently, only match interrupt flag can be cleared.
*
* @param base OSTIMER peripheral base address.
* @return none
*/
void OSTIMER_ClearStatusFlags(OSTIMER_Type *base, uint32_t mask);
/*!
* @brief Set the match raw value for OSTIMER.
*
* This function will set a match value for OSTIMER with an optional callback. And this callback
* will be called while the data in dedicated pair match register is equals to the value of central EVTIMER.
* Please note that, the data format is gray-code, if decimal data was desired, please using OSTIMER_SetMatchValue().
*
* @param base OSTIMER peripheral base address.
* @param count OSTIMER timer match value.(Value is gray-code format)
*
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
* @return none
*/
void OSTIMER_SetMatchRawValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb);
/*!
* @brief Set the match value for OSTIMER.
*
* This function will set a match value for OSTIMER with an optional callback. And this callback
* will be called while the data in dedicated pair match register is equals to the value of central OS TIMER.
*
* @param base OSTIMER peripheral base address.
* @param count OSTIMER timer match value.(Value is decimal format, and this value will be translate to Gray code
* internally.)
*
* @param cb OSTIMER callback (can be left as NULL if none, otherwise should be a void func(void)).
* @return none
*/
void OSTIMER_SetMatchValue(OSTIMER_Type *base, uint64_t count, ostimer_callback_t cb);
/*!
* @brief Get current timer raw count value from OSTIMER.
*
* This function will get a gray code type timer count value from OS timer register.
* The raw value of timer count is gray code format.
*
* @param base OSTIMER peripheral base address.
* @return Raw value of OSTIMER, gray code format.
*/
static inline uint64_t OSTIMER_GetCurrentTimerRawValue(OSTIMER_Type *base)
{
uint64_t tmp = 0U;
tmp = base->EVTIMERL;
tmp |= (uint64_t)(base->EVTIMERH) << 32U;
return tmp;
}
/*!
* @brief Get current timer count value from OSTIMER.
*
* This function will get a decimal timer count value.
* The RAW value of timer count is gray code format, will be translated to decimal data internally.
*
* @param base OSTIMER peripheral base address.
* @return Value of OSTIMER which will be formated to decimal value.
*/
uint64_t OSTIMER_GetCurrentTimerValue(OSTIMER_Type *base);
/*!
* @brief Get the capture value from OSTIMER.
*
* This function will get a captured gray-code value from OSTIMER.
* The Raw value of timer capture is gray code format.
*
* @param base OSTIMER peripheral base address.
* @return Raw value of capture register, data format is gray code.
*/
static inline uint64_t OSTIMER_GetCaptureRawValue(OSTIMER_Type *base)
{
uint64_t tmp = 0U;
tmp = base->CAPTUREN_L;
tmp |= (uint64_t)(base->CAPTUREN_H) << 32U;
return tmp;
}
/*!
* @brief Get the capture value from OSTIMER.
*
* This function will get a capture decimal-value from OSTIMER.
* The RAW value of timer capture is gray code format, will be translated to decimal data internally.
*
* @param base OSTIMER peripheral base address.
* @return Value of capture register, data format is decimal.
*/
uint64_t OSTIMER_GetCaptureValue(OSTIMER_Type *base);
/*!
* @brief OS timer interrupt Service Handler.
*
* This function handles the interrupt and refers to the callback array in the driver to callback user (as per request
* in OSTIMER_SetMatchValue()).
* if no user callback is scheduled, the interrupt will simply be cleared.
*
* @param base OS timer peripheral base address.
* @param cb callback scheduled for this instance of OS timer
* @return none
*/
void OSTIMER_HandleIRQ(OSTIMER_Type *base, ostimer_callback_t cb);
/*!
* @}
*/
#if defined(__cplusplus)
}
#endif
/*!
* @}
*/
#endif /* _FSL_OSTIMER_H_ */

163
ext/hal/nxp/mcux/drivers/lpc/fsl_pint.c
View file

@ -19,7 +19,6 @@
/*! @brief Irq number array */ /*! @brief Irq number array */
static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS; static const IRQn_Type s_pintIRQ[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS] = PINT_IRQS;
/*! @brief Callback function array for PINT(s). */ /*! @brief Callback function array for PINT(s). */
static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS]; static pint_cb_t s_pintCallback[FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS];
@ -49,12 +48,22 @@ void PINT_Init(PINT_Type *base)
s_pintCallback[i] = NULL; s_pintCallback[i] = NULL;
} }
/* Disable all bit slices */ if (base == SECPINT)
for (i = 0; i < PINT_PIN_INT_COUNT; i++)
{ {
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U))); /* Disable all bit slices for secure pint*/
for (i = 0; i < SEC_PINT_PIN_INT_COUNT; i++)
{
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
}
}
else
{
/* Disable all bit slices for pint*/
for (i = 0; i < PINT_PIN_INT_COUNT; i++)
{
pmcfg = pmcfg | (kPINT_PatternMatchNever << (PININT_BITSLICE_CFG_START + (i * 3U)));
}
} }
#if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1) #if defined(FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE) && (FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE == 1)
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */ /* Enable the clock. */
@ -77,16 +86,42 @@ void PINT_Init(PINT_Type *base)
RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn); RESET_PeripheralReset(kGPIO0_RST_N_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#else
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */ /* Enable the clock. */
CLOCK_EnableClock(kCLOCK_Pint); CLOCK_EnableClock(kCLOCK_Gpio_Sec);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */ /* Reset the module. */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#else
/* if need config SECURE PINT device,then enable secure pint interrupt clock */
if (base == SECPINT)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(kCLOCK_Gpio_sec_Int);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
}
else
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the clock. */
CLOCK_EnableClock(kCLOCK_Pint);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
}
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/ #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE && FSL_FEATURE_CLOCK_HAS_NO_GPIOINT_CLOCK_SOURCE*/
/* Disable all pattern match bit slices */ /* Disable all pattern match bit slices */
@ -135,7 +170,15 @@ void PINT_PinInterruptConfig(PINT_Type *base, pint_pin_int_t intr, pint_pin_enab
{ {
base->CIENF = 1U << intr; base->CIENF = 1U << intr;
} }
/* Handle secure pint interrupt*/
if ((base == SECPINT) && (intr == kPINT_PinInt0))
{
intr = kPINT_SecPinInt0;
}
else if ((base == SECPINT) && (intr == kPINT_PinInt1))
{
intr = kPINT_SecPinInt1;
}
s_pintCallback[intr] = callback; s_pintCallback[intr] = callback;
} }
@ -251,7 +294,15 @@ void PINT_PatternMatchConfig(PINT_Type *base, pint_pmatch_bslice_t bslice, pint_
} }
base->PMCFG = pmcfg; base->PMCFG = pmcfg;
/* Handle secure pint pattern match*/
if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice0))
{
bslice = kSECPINT_PatternMatchBSlice0;
}
else if ((base == SECPINT) && (bslice == kPINT_PatternMatchBSlice1))
{
bslice = kSECPINT_PatternMatchBSlice1;
}
/* Save callback pointer */ /* Save callback pointer */
s_pintCallback[bslice] = cfg->callback; s_pintCallback[bslice] = cfg->callback;
} }
@ -307,7 +358,7 @@ uint32_t PINT_PatternMatchResetDetectLogic(PINT_Type *base)
uint32_t pmstatus; uint32_t pmstatus;
uint32_t pmsrc; uint32_t pmsrc;
pmctrl = PINT->PMCTRL; pmctrl = base->PMCTRL;
pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT; pmstatus = pmctrl >> PINT_PMCTRL_PMAT_SHIFT;
if (pmstatus) if (pmstatus)
{ {
@ -357,6 +408,10 @@ void PINT_EnableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
{ {
assert(base); assert(base);
if (base == SECPINT)
{
pintIdx += 8;
}
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
EnableIRQ(s_pintIRQ[pintIdx]); EnableIRQ(s_pintIRQ[pintIdx]);
@ -400,11 +455,14 @@ void PINT_DisableCallbackByIndex(PINT_Type *base, pint_pin_int_t pintIdx)
{ {
assert(base); assert(base);
if (base == SECPINT)
{
pintIdx += 8;
}
DisableIRQ(s_pintIRQ[pintIdx]); DisableIRQ(s_pintIRQ[pintIdx]);
PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx); PINT_PinInterruptClrStatus(base, (pint_pin_int_t)pintIdx);
NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]); NVIC_ClearPendingIRQ(s_pintIRQ[pintIdx]);
} }
/*! /*!
* brief Deinitialize PINT peripheral. * brief Deinitialize PINT peripheral.
@ -449,19 +507,92 @@ void PINT_Deinit(PINT_Type *base)
CLOCK_DisableClock(kCLOCK_Gpio0); CLOCK_DisableClock(kCLOCK_Gpio0);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#else
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */ /* Reset the module. */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn); RESET_PeripheralReset(kGPIOSEC_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */ /* Enable the clock. */
CLOCK_DisableClock(kCLOCK_Pint); CLOCK_DisableClock(kCLOCK_Gpio_Sec);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#else
if (base == SECPINT)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(kGPIOSECINT_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(kCLOCK_Gpio_sec_Int);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
else
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(kPINT_RST_SHIFT_RSTn);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable the clock. */
CLOCK_DisableClock(kCLOCK_Pint);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
#endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */ #endif /* FSL_FEATURE_CLOCK_HAS_GPIOINT_CLOCK_SOURCE */
} }
/* IRQ handler functions overloading weak symbols in the startup */
void SEC_GPIO_INT0_IRQ0_DriverIRQHandler(void)
{
uint32_t pmstatus = 0;
/* Reset pattern match detection */
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
/* Call user function */
if (s_pintCallback[kPINT_SecPinInt0] != NULL)
{
s_pintCallback[kPINT_SecPinInt0](kPINT_SecPinInt0, pmstatus);
}
if ((SECPINT->ISEL & 0x1U) == 0x0U)
{
/* Edge sensitive: clear Pin interrupt after callback */
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt0);
}
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
/* IRQ handler functions overloading weak symbols in the startup */
void SEC_GPIO_INT0_IRQ1_DriverIRQHandler(void)
{
uint32_t pmstatus;
/* Reset pattern match detection */
pmstatus = PINT_PatternMatchResetDetectLogic(SECPINT);
/* Call user function */
if (s_pintCallback[kPINT_SecPinInt1] != NULL)
{
s_pintCallback[kPINT_SecPinInt1](kPINT_SecPinInt1, pmstatus);
}
if ((SECPINT->ISEL & 0x1U) == 0x0U)
{
/* Edge sensitive: clear Pin interrupt after callback */
PINT_PinInterruptClrStatus(SECPINT, kPINT_PinInt1);
}
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
exception return operation might vector to incorrect interrupt */
#if defined __CORTEX_M && (__CORTEX_M == 4U)
__DSB();
#endif
}
#endif
/* IRQ handler functions overloading weak symbols in the startup */ /* IRQ handler functions overloading weak symbols in the startup */
void PIN_INT0_DriverIRQHandler(void) void PIN_INT0_DriverIRQHandler(void)
{ {

17
ext/hal/nxp/mcux/drivers/lpc/fsl_pint.h
View file

@ -24,12 +24,15 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
#define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2 */ #define FSL_PINT_DRIVER_VERSION (MAKE_VERSION(2, 0, 4)) /*!< Version 2.0.4 */
/*@}*/ /*@}*/
/* Number of interrupt line supported by PINT */ /* Number of interrupt line supported by PINT */
#define PINT_PIN_INT_COUNT 8U #define PINT_PIN_INT_COUNT 8U
/* Number of interrupt line supported by SECURE PINT */
#define SEC_PINT_PIN_INT_COUNT 2U
/* Number of input sources supported by PINT */ /* Number of input sources supported by PINT */
#define PINT_INPUT_COUNT 8U #define PINT_INPUT_COUNT 8U
@ -88,6 +91,12 @@ typedef enum _pint_int
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */ kPINT_PinInt7 = 7U, /*!< Pin Interrupt 7 */
#endif #endif
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U)
kPINT_SecPinInt0 = 8U, /*!< Secure Pin Interrupt 0 */
#endif
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
kPINT_SecPinInt1 = 9U, /*!< Secure Pin Interrupt 1 */
#endif
} pint_pin_int_t; } pint_pin_int_t;
/*! @brief PINT Pattern Match bit slice input source type */ /*! @brief PINT Pattern Match bit slice input source type */
@ -128,6 +137,12 @@ typedef enum _pint_pmatch_bslice
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U) #if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 7U)
kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */ kPINT_PatternMatchBSlice7 = 7U, /*!< Bit slice 7 */
#endif #endif
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 0U)
kSECPINT_PatternMatchBSlice0 = 8U, /*!< Bit slice 0 */
#endif
#if (FSL_FEATURE_SECPINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
kSECPINT_PatternMatchBSlice1 = 9U, /*!< Bit slice 1 */
#endif
} pint_pmatch_bslice_t; } pint_pmatch_bslice_t;
/*! @brief PINT Pattern Match configuration type */ /*! @brief PINT Pattern Match configuration type */

97
ext/hal/nxp/mcux/drivers/lpc/fsl_plu.c Normal file
View file

@ -0,0 +1,97 @@
/*
* Copyright (c) 2018, NXP Semiconductors, Inc.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_plu.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.plu"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Gets the instance from the base address
*
* @param base PLU peripheral base address
*
* @return The PLU instance
*/
static uint32_t PLU_GetInstance(PLU_Type *base);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief Pointers to PLU bases for each instance. */
static PLU_Type *const s_pluBases[] = PLU_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief Pointers to PLU clocks for each instance. */
static const clock_ip_name_t s_pluClocks[] = PLU_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/*! @brief Pointers to PLU resets for each instance. */
static const reset_ip_name_t s_lpuResets[] = PLU_RSTS_N;
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static uint32_t PLU_GetInstance(PLU_Type *base)
{
uint32_t instance;
uint32_t pluArrayCount = (sizeof(s_pluBases) / sizeof(s_pluBases[0]));
/* Find the instance index from base address mappings. */
for (instance = 0; instance < pluArrayCount; instance++)
{
if (s_pluBases[instance] == base)
{
break;
}
}
assert(instance < pluArrayCount);
return instance;
}
/*!
* brief Ungates the PLU clock and reset the module.
*
* note This API should be called at the beginning of the application using the PLU driver.
*
* param base PLU peripheral base address
*/
void PLU_Init(PLU_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable the PLU peripheral clock */
CLOCK_EnableClock(s_pluClocks[PLU_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
/* Reset the module. */
RESET_PeripheralReset(s_lpuResets[PLU_GetInstance(base)]);
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
}
/*!
* brief Gate the PLU clock
*
* param base PLU peripheral base address
*/
void PLU_Deinit(PLU_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Gate the module clock */
CLOCK_DisableClock((s_pluClocks[PLU_GetInstance(base)]));
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}

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/*
* Copyright (c) 2018, NXP Semiconductors, Inc.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PLU_H_
#define _FSL_PLU_H_
#include "fsl_common.h"
/*!
* @addtogroup plu
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
#define FSL_PLU_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
/*@}*/
/*! @brief Index of LUT */
typedef enum _plu_lut_index
{
kPLU_LUT_0 = 0U, /*!< 5-input Look-up Table 0 */
kPLU_LUT_1 = 1U, /*!< 5-input Look-up Table 1 */
kPLU_LUT_2 = 2U, /*!< 5-input Look-up Table 2 */
kPLU_LUT_3 = 3U, /*!< 5-input Look-up Table 3 */
kPLU_LUT_4 = 4U, /*!< 5-input Look-up Table 4 */
kPLU_LUT_5 = 5U, /*!< 5-input Look-up Table 5 */
kPLU_LUT_6 = 6U, /*!< 5-input Look-up Table 6 */
kPLU_LUT_7 = 7U, /*!< 5-input Look-up Table 7 */
kPLU_LUT_8 = 8U, /*!< 5-input Look-up Table 8 */
kPLU_LUT_9 = 9U, /*!< 5-input Look-up Table 9 */
kPLU_LUT_10 = 10U, /*!< 5-input Look-up Table 10 */
kPLU_LUT_11 = 11U, /*!< 5-input Look-up Table 11 */
kPLU_LUT_12 = 12U, /*!< 5-input Look-up Table 12 */
kPLU_LUT_13 = 13U, /*!< 5-input Look-up Table 13 */
kPLU_LUT_14 = 14U, /*!< 5-input Look-up Table 14 */
kPLU_LUT_15 = 15U, /*!< 5-input Look-up Table 15 */
kPLU_LUT_16 = 16U, /*!< 5-input Look-up Table 16 */
kPLU_LUT_17 = 17U, /*!< 5-input Look-up Table 17 */
kPLU_LUT_18 = 18U, /*!< 5-input Look-up Table 18 */
kPLU_LUT_19 = 19U, /*!< 5-input Look-up Table 19 */
kPLU_LUT_20 = 20U, /*!< 5-input Look-up Table 20 */
kPLU_LUT_21 = 21U, /*!< 5-input Look-up Table 21 */
kPLU_LUT_22 = 22U, /*!< 5-input Look-up Table 22 */
kPLU_LUT_23 = 23U, /*!< 5-input Look-up Table 23 */
kPLU_LUT_24 = 24U, /*!< 5-input Look-up Table 24 */
kPLU_LUT_25 = 25U /*!< 5-input Look-up Table 25 */
} plu_lut_index_t;
/*! @brief Inputs of LUT. 5 input present for each LUT. */
typedef enum _plu_lut_in_index
{
kPLU_LUT_IN_0 = 0U, /*!< LUT input 0 */
kPLU_LUT_IN_1 = 1U, /*!< LUT input 1 */
kPLU_LUT_IN_2 = 2U, /*!< LUT input 2 */
kPLU_LUT_IN_3 = 3U, /*!< LUT input 3 */
kPLU_LUT_IN_4 = 4U /*!< LUT input 4 */
} plu_lut_in_index_t;
/*! @brief Available sources of LUT input */
typedef enum _plu_lut_input_source
{
kPLU_LUT_IN_SRC_PLU_IN_0 = 0U, /*!< Select PLU input 0 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_PLU_IN_1 = 1U, /*!< Select PLU input 1 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_PLU_IN_2 = 2U, /*!< Select PLU input 2 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_PLU_IN_3 = 3U, /*!< Select PLU input 3 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_PLU_IN_4 = 4U, /*!< Select PLU input 4 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_PLU_IN_5 = 5U, /*!< Select PLU input 5 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_0 = 6U, /*!< Select LUT output 0 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_1 = 7U, /*!< Select LUT output 1 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_2 = 8U, /*!< Select LUT output 2 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_3 = 9U, /*!< Select LUT output 3 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_4 = 10U, /*!< Select LUT output 4 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_5 = 11U, /*!< Select LUT output 5 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_6 = 12U, /*!< Select LUT output 6 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_7 = 13U, /*!< Select LUT output 7 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_8 = 14U, /*!< Select LUT output 8 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_9 = 15U, /*!< Select LUT output 9 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_10 = 16U, /*!< Select LUT output 10 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_11 = 17U, /*!< Select LUT output 11 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_12 = 18U, /*!< Select LUT output 12 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_13 = 19U, /*!< Select LUT output 13 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_14 = 20U, /*!< Select LUT output 14 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_15 = 21U, /*!< Select LUT output 15 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_16 = 22U, /*!< Select LUT output 16 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_17 = 23U, /*!< Select LUT output 17 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_18 = 24U, /*!< Select LUT output 18 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_19 = 25U, /*!< Select LUT output 19 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_20 = 26U, /*!< Select LUT output 20 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_21 = 27U, /*!< Select LUT output 21 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_22 = 28U, /*!< Select LUT output 22 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_23 = 29U, /*!< Select LUT output 23 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_24 = 30U, /*!< Select LUT output 24 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_LUT_OUT_25 = 31U, /*!< Select LUT output 25 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_FLIPFLOP_0 = 32U, /*!< Select Flip-Flops state 0 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_FLIPFLOP_1 = 33U, /*!< Select Flip-Flops state 1 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_FLIPFLOP_2 = 34U, /*!< Select Flip-Flops state 2 to be connected to LUTn Input x */
kPLU_LUT_IN_SRC_FLIPFLOP_3 = 35U /*!< Select Flip-Flops state 3 to be connected to LUTn Input x */
} plu_lut_input_source_t;
/*! @brief PLU output multiplexer registers */
typedef enum _plu_output_index
{
kPLU_OUTPUT_0 = 0U, /*!< PLU OUTPUT 0 */
kPLU_OUTPUT_1 = 1U, /*!< PLU OUTPUT 1 */
kPLU_OUTPUT_2 = 2U, /*!< PLU OUTPUT 2 */
kPLU_OUTPUT_3 = 3U, /*!< PLU OUTPUT 3 */
kPLU_OUTPUT_4 = 4U, /*!< PLU OUTPUT 4 */
kPLU_OUTPUT_5 = 5U, /*!< PLU OUTPUT 5 */
kPLU_OUTPUT_6 = 6U, /*!< PLU OUTPUT 6 */
kPLU_OUTPUT_7 = 7U /*!< PLU OUTPUT 7 */
} plu_output_index_t;
/*! @brief Available sources of PLU output */
typedef enum _plu_output_source
{
kPLU_OUT_SRC_LUT_0 = 0U, /*!< Select LUT0 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_1 = 1U, /*!< Select LUT1 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_2 = 2U, /*!< Select LUT2 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_3 = 3U, /*!< Select LUT3 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_4 = 4U, /*!< Select LUT4 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_5 = 5U, /*!< Select LUT5 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_6 = 6U, /*!< Select LUT6 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_7 = 7U, /*!< Select LUT7 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_8 = 8U, /*!< Select LUT8 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_9 = 9U, /*!< Select LUT9 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_10 = 10U, /*!< Select LUT10 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_11 = 11U, /*!< Select LUT11 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_12 = 12U, /*!< Select LUT12 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_13 = 13U, /*!< Select LUT13 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_14 = 14U, /*!< Select LUT14 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_15 = 15U, /*!< Select LUT15 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_16 = 16U, /*!< Select LUT16 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_17 = 17U, /*!< Select LUT17 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_18 = 18U, /*!< Select LUT18 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_19 = 19U, /*!< Select LUT19 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_20 = 20U, /*!< Select LUT20 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_21 = 21U, /*!< Select LUT21 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_22 = 22U, /*!< Select LUT22 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_23 = 23U, /*!< Select LUT23 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_24 = 24U, /*!< Select LUT24 output to be connected to PLU output */
kPLU_OUT_SRC_LUT_25 = 25U, /*!< Select LUT25 output to be connected to PLU output */
kPLU_OUT_SRC_FLIPFLOP_0 = 26U, /*!< Select Flip-Flops state(0) to be connected to PLU output */
kPLU_OUT_SRC_FLIPFLOP_1 = 27U, /*!< Select Flip-Flops state(1) to be connected to PLU output */
kPLU_OUT_SRC_FLIPFLOP_2 = 28U, /*!< Select Flip-Flops state(2) to be connected to PLU output */
kPLU_OUT_SRC_FLIPFLOP_3 = 29U /*!< Select Flip-Flops state(3) to be connected to PLU output */
} plu_output_source_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief Ungates the PLU clock and reset the module.
*
* @note This API should be called at the beginning of the application using the PLU driver.
*
* @param base PLU peripheral base address
*/
void PLU_Init(PLU_Type *base);
/*!
* @brief Gate the PLU clock
*
* @param base PLU peripheral base address
*/
void PLU_Deinit(PLU_Type *base);
/*! @}*/
/*!
* @name Set input/output source and Truth Table
* @{
*/
/*!
* @brief Set Input source of LUT.
*
* Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
* For each LUT, the slot associated with the output from LUTn itself is tied low.
*
* @param base PLU peripheral base address.
* @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
* @param lutInIndex LUT input index (see @ref plu_lut_in_index_t typedef enumeration).
* @param inputSrc LUT input source (see @ref plu_lut_input_source_t typedef enumeration).
*/
static inline void PLU_SetLutInputSource(PLU_Type *base,
plu_lut_index_t lutIndex,
plu_lut_in_index_t lutInIndex,
plu_lut_input_source_t inputSrc)
{
PLU->LUT[lutIndex].INP[lutInIndex] = inputSrc;
}
/*!
* @brief Set Output source of PLU.
*
* Note: An external clock must be applied to the PLU_CLKIN input when using FFs.
*
* @param base PLU peripheral base address.
* @param outputIndex PLU output index (see @ref plu_output_index_t typedef enumeration).
* @param outputSrc PLU output source (see @ref plu_output_source_t typedef enumeration).
*/
static inline void PLU_SetOutputSource(PLU_Type *base, plu_output_index_t outputIndex, plu_output_source_t outputSrc)
{
base->OUTPUT_MUX[outputIndex] = outputSrc;
}
/*!
* @brief Set Truth Table of LUT.
*
* @param base PLU peripheral base address.
* @param lutIndex LUT index (see @ref plu_lut_index_t typedef enumeration).
* @param truthTable Truth Table value.
*/
static inline void PLU_SetLutTruthTable(PLU_Type *base, plu_lut_index_t lutIndex, uint32_t truthTable)
{
base->LUT_TRUTH[lutIndex] = truthTable;
}
/*! @}*/
/*!
* @name Read current Output State
* @{
*/
/*!
* @brief Read the current state of the 8 designated PLU Outputs.
*
* Note: The PLU bus clock must be re-enabled prior to reading the Outpus Register if PLU bus clock is
* shut-off.
*
* @param base PLU peripheral base address.
* @return Current PLU output state value.
*/
static inline uint32_t PLU_ReadOutputState(PLU_Type *base)
{
return (base->OUTPUTS & PLU_OUTPUTS_OUTPUT_STATE_MASK);
}
/*! @}*/
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /* _FSL_PLU_H_ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_powerquad.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad_basic"
#endif
/*******************************************************************************
* Code
******************************************************************************/
void PQ_GetDefaultConfig(pq_config_t *config)
{
config->inputAFormat = kPQ_Float;
config->inputAPrescale = 0;
config->inputBFormat = kPQ_Float;
config->inputBPrescale = 0;
config->outputFormat = kPQ_Float;
config->outputPrescale = 0;
config->tmpFormat = kPQ_Float;
config->tmpPrescale = 0;
config->machineFormat = kPQ_Float;
config->tmpBase = (void *)0xE0000000U;
}
void PQ_SetConfig(POWERQUAD_Type *base, const pq_config_t *config)
{
assert(config);
base->TMPBASE = (uint32_t)config->tmpBase;
base->INAFORMAT =
((uint32_t)config->inputAPrescale << 8U) | ((uint32_t)config->inputAFormat << 4U) | config->machineFormat;
base->INBFORMAT =
((uint32_t)config->inputBPrescale << 8U) | ((uint32_t)config->inputBFormat << 4U) | config->machineFormat;
base->TMPFORMAT =
((uint32_t)config->tmpPrescale << 8U) | ((uint32_t)config->tmpFormat << 4U) | config->machineFormat;
base->OUTFORMAT =
((uint32_t)config->outputPrescale << 8U) | ((uint32_t)config->outputFormat << 4U) | config->machineFormat;
}
void PQ_Init(POWERQUAD_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_PowerQuad);
#endif
#if !(defined(FSL_SDK_DISABLE_DRIVER_RESET_CONTROL) && FSL_SDK_DISABLE_DRIVER_RESET_CONTROL)
RESET_PeripheralReset(kPOWERQUAD_RST_SHIFT_RSTn);
#endif
/* Enable event used for WFE. */
base->EVENTEN = POWERQUAD_EVENTEN_EVENT_OFLOW_MASK | POWERQUAD_EVENTEN_EVENT_NAN_MASK |
POWERQUAD_EVENTEN_EVENT_FIXED_MASK | POWERQUAD_EVENTEN_EVENT_UFLOW_MASK |
POWERQUAD_EVENTEN_EVENT_BERR_MASK | POWERQUAD_EVENTEN_EVENT_COMP_MASK;
}
void PQ_Deinit(POWERQUAD_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_PowerQuad);
#endif
}
void PQ_SetFormat(POWERQUAD_Type *base, pq_computationengine_t engine, pq_format_t format)
{
pq_config_t config;
PQ_GetDefaultConfig(&config);
/* 32-bit Float point */
if (kPQ_Float == format)
{
config.inputAFormat = kPQ_Float;
config.inputAPrescale = 0;
config.inputBFormat = kPQ_Float;
config.inputBPrescale = 0;
config.outputFormat = kPQ_Float;
config.outputPrescale = 0;
config.tmpFormat = kPQ_Float;
config.tmpPrescale = 0;
}
/* 32-bit Fixed point */
if (kPQ_32Bit == format)
{
config.inputAFormat = kPQ_32Bit;
config.inputAPrescale = 0;
config.inputBFormat = kPQ_32Bit;
config.inputBPrescale = 0;
config.outputFormat = kPQ_32Bit;
config.outputPrescale = 0;
config.tmpFormat = kPQ_Float;
config.tmpPrescale = 0;
}
/* 16-bit Fixed point */
if (kPQ_16Bit == format)
{
config.inputAFormat = kPQ_16Bit;
config.inputAPrescale = 0;
config.inputBFormat = kPQ_16Bit;
config.inputBPrescale = 0;
config.outputFormat = kPQ_16Bit;
config.outputPrescale = 0;
config.tmpFormat = kPQ_Float;
config.tmpPrescale = 0;
}
if (CP_FFT == engine)
{
config.machineFormat = kPQ_32Bit;
}
else
{
config.machineFormat = kPQ_Float;
}
PQ_SetConfig(base, &config);
}

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <stdint.h>
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad"
#endif
/*******************************************************************************
* Definitions
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*!
* @brief MATLAB script for calculating twiddle factor table for DCT is below,this gives phasor for FFTs twiddle at end
* of DCT,
* note that y is raw, scaled y is for fixed point multiplication.
*
* N=32;
* n=0;
* while(n<N)
* y(n+1)= exp(-1*i*n*(pi/(2*N)));
*
* if (n==0)
* y(n+1) = y(n+1) * sqrt(1/N);
* else
* y(n+1) = y(n+1) * sqrt(2/N);
* end
*
* scaledy(n+1) = y(n+1) * 1024*1024*16;
* n=n+1;
* end
*
* Use real(int32(scaledy)) to get co-efficients for real side and imag(int32(scaledy)) to get co-efficients for
* imaginary side
* or simply int32(scaledy) to get list of co-efficients for both.
*/
int32_t dct16_twiddle[32] = {4194304, 0, 5903079, -581403, 5817667, -1157206, 5676227, -1721865,
5480122, -2269941, 5231241, -2796157, 4931980, -3295444, 4585221, -3762994,
4194304, -4194304, 3762994, -4585221, 3295444, -4931980, 2796157, -5231241,
2269941, -5480122, 1721865, -5676227, 1157206, -5817667, 581403, -5903079};
int32_t dct32_twiddle[64] = {
2965821, 0, 4189252, -205805, 4174107, -411114, 4148907, -615432, 4113712, -818268, 4068606,
-1019133, 4013699, -1217542, 3949122, -1413018, 3875032, -1605091, 3791606, -1793296, 3699046, -1977181,
3597575, -2156303, 3487436, -2330230, 3368897, -2498544, 3242241, -2660838, 3107774, -2816722, 2965821,
-2965821, 2816722, -3107774, 2660838, -3242241, 2498544, -3368897, 2330230, -3487436, 2156303, -3597575,
1977181, -3699046, 1793296, -3791606, 1605091, -3875032, 1413018, -3949122, 1217542, -4013699, 1019133,
-4068606, 818268, -4113712, 615432, -4148907, 411114, -4174107, 205805, -4189252};
int32_t dct64_twiddle[128] = {
2097152, 0, 2964928, -72785, 2962248, -145526, 2957785, -218179, 2951540, -290701, 2943516, -363048,
2933720, -435176, 2922157, -507042, 2908833, -578603, 2893758, -649815, 2876939, -720636, 2858387, -791022,
2838114, -860932, 2816130, -930324, 2792451, -999155, 2767089, -1067384, 2740061, -1134970, 2711382, -1201873,
2681070, -1268052, 2649143, -1333467, 2615620, -1398078, 2580522, -1461848, 2543869, -1524737, 2505684, -1586707,
2465990, -1647722, 2424810, -1707744, 2382170, -1766737, 2338094, -1824667, 2292610, -1881497, 2245746, -1937194,
2197528, -1991724, 2147987, -2045054, 2097152, -2097152, 2045054, -2147987, 1991724, -2197528, 1937194, -2245746,
1881497, -2292610, 1824667, -2338094, 1766737, -2382170, 1707744, -2424810, 1647722, -2465990, 1586707, -2505684,
1524737, -2543869, 1461848, -2580522, 1398078, -2615620, 1333467, -2649143, 1268052, -2681070, 1201873, -2711382,
1134970, -2740061, 1067384, -2767089, 999155, -2792451, 930324, -2816130, 860932, -2838114, 791022, -2858387,
720636, -2876939, 649815, -2893758, 578603, -2908833, 507042, -2922157, 435176, -2933720, 363048, -2943516,
290701, -2951540, 218179, -2957785, 145526, -2962248, 72785, -2964928};
int32_t dct128_twiddle[256] = {
1482910, 0, 2096994, -25735, 2096520, -51467, 2095731, -77190, 2094626, -102902, 2093205, -128599,
2091470, -154276, 2089419, -179930, 2087054, -205557, 2084374, -231153, 2081380, -256714, 2078073, -282236,
2074453, -307716, 2070521, -333150, 2066277, -358533, 2061722, -383862, 2056856, -409134, 2051680, -434344,
2046196, -459489, 2040403, -484564, 2034303, -509566, 2027897, -534492, 2021185, -559337, 2014169, -584098,
2006849, -608771, 1999228, -633352, 1991305, -657838, 1983082, -682225, 1974561, -706509, 1965742, -730687,
1956628, -754755, 1947218, -778709, 1937516, -802545, 1927521, -826261, 1917237, -849853, 1906663, -873316,
1895803, -896648, 1884657, -919845, 1873227, -942903, 1861515, -965820, 1849523, -988591, 1837252, -1011213,
1824705, -1033682, 1811882, -1055997, 1798787, -1078152, 1785421, -1100144, 1771786, -1121971, 1757885, -1143629,
1743718, -1165115, 1729289, -1186426, 1714600, -1207557, 1699652, -1228507, 1684448, -1249272, 1668991, -1269849,
1653282, -1290234, 1637325, -1310425, 1621120, -1330419, 1604672, -1350213, 1587982, -1369803, 1571053, -1389187,
1553887, -1408361, 1536487, -1427324, 1518856, -1446071, 1500996, -1464601, 1482910, -1482910, 1464601, -1500996,
1446071, -1518856, 1427324, -1536487, 1408361, -1553887, 1389187, -1571053, 1369803, -1587982, 1350213, -1604672,
1330419, -1621120, 1310425, -1637325, 1290234, -1653282, 1269849, -1668991, 1249272, -1684448, 1228507, -1699652,
1207557, -1714600, 1186426, -1729289, 1165115, -1743718, 1143629, -1757885, 1121971, -1771786, 1100144, -1785421,
1078152, -1798787, 1055997, -1811882, 1033682, -1824705, 1011213, -1837252, 988591, -1849523, 965820, -1861515,
942903, -1873227, 919845, -1884657, 896648, -1895803, 873316, -1906663, 849853, -1917237, 826261, -1927521,
802545, -1937516, 778709, -1947218, 754755, -1956628, 730687, -1965742, 706509, -1974561, 682225, -1983082,
657838, -1991305, 633352, -1999228, 608771, -2006849, 584098, -2014169, 559337, -2021185, 534492, -2027897,
509566, -2034303, 484564, -2040403, 459489, -2046196, 434344, -2051680, 409134, -2056856, 383862, -2061722,
358533, -2066277, 333150, -2070521, 307716, -2074453, 282236, -2078073, 256714, -2081380, 231153, -2084374,
205557, -2087054, 179930, -2089419, 154276, -2091470, 128599, -2093205, 102902, -2094626, 77190, -2095731,
51467, -2096520, 25735, -2096994};
int32_t dct256_twiddle[512] = {
1048576, 0, 1482882, -9099, 1482799, -18198, 1482659, -27296, 1482464, -36392, 1482213, -45488,
1481906, -54582, 1481543, -63674, 1481124, -72763, 1480650, -81850, 1480120, -90933, 1479534, -100013,
1478892, -109090, 1478195, -118162, 1477442, -127230, 1476634, -136293, 1475770, -145351, 1474850, -154403,
1473875, -163450, 1472844, -172490, 1471758, -181524, 1470617, -190551, 1469420, -199571, 1468168, -208584,
1466860, -217588, 1465497, -226585, 1464080, -235572, 1462607, -244551, 1461078, -253521, 1459495, -262481,
1457857, -271432, 1456164, -280372, 1454417, -289301, 1452614, -298220, 1450757, -307128, 1448845, -316024,
1446879, -324908, 1444858, -333779, 1442783, -342638, 1440653, -351485, 1438469, -360318, 1436231, -369137,
1433939, -377943, 1431593, -386734, 1429194, -395511, 1426740, -404273, 1424232, -413020, 1421671, -421751,
1419057, -430466, 1416389, -439165, 1413667, -447848, 1410893, -456513, 1408065, -465162, 1405185, -473793,
1402251, -482406, 1399265, -491001, 1396225, -499577, 1393134, -508135, 1389990, -516674, 1386793, -525193,
1383545, -533692, 1380244, -542171, 1376891, -550630, 1373487, -559068, 1370031, -567485, 1366523, -575881,
1362963, -584255, 1359353, -592607, 1355691, -600937, 1351978, -609244, 1348215, -617528, 1344400, -625789,
1340535, -634026, 1336620, -642239, 1332654, -650429, 1328638, -658593, 1324572, -666733, 1320456, -674848,
1316290, -682938, 1312075, -691001, 1307810, -699039, 1303496, -707051, 1299133, -715035, 1294722, -722993,
1290261, -730924, 1285752, -738827, 1281194, -746702, 1276589, -754550, 1271935, -762368, 1267233, -770158,
1262483, -777919, 1257686, -785651, 1252842, -793354, 1247951, -801026, 1243012, -808668, 1238027, -816280,
1232995, -823861, 1227917, -831411, 1222792, -838930, 1217621, -846417, 1212405, -853872, 1207143, -861295,
1201835, -868686, 1196483, -876044, 1191085, -883369, 1185642, -890660, 1180155, -897919, 1174623, -905143,
1169047, -912333, 1163427, -919489, 1157763, -926611, 1152056, -933697, 1146305, -940748, 1140511, -947764,
1134674, -954744, 1128795, -961689, 1122873, -968597, 1116909, -975468, 1110902, -982303, 1104854, -989101,
1098764, -995862, 1092633, -1002585, 1086461, -1009270, 1080247, -1015918, 1073994, -1022527, 1067699, -1029097,
1061365, -1035629, 1054990, -1042122, 1048576, -1048576, 1042122, -1054990, 1035629, -1061365, 1029097, -1067699,
1022527, -1073994, 1015918, -1080247, 1009270, -1086461, 1002585, -1092633, 995862, -1098764, 989101, -1104854,
982303, -1110902, 975468, -1116909, 968597, -1122873, 961689, -1128795, 954744, -1134674, 947764, -1140511,
940748, -1146305, 933697, -1152056, 926611, -1157763, 919489, -1163427, 912333, -1169047, 905143, -1174623,
897919, -1180155, 890660, -1185642, 883369, -1191085, 876044, -1196483, 868686, -1201835, 861295, -1207143,
853872, -1212405, 846417, -1217621, 838930, -1222792, 831411, -1227917, 823861, -1232995, 816280, -1238027,
808668, -1243012, 801026, -1247951, 793354, -1252842, 785651, -1257686, 777919, -1262483, 770158, -1267233,
762368, -1271935, 754550, -1276589, 746702, -1281194, 738827, -1285752, 730924, -1290261, 722993, -1294722,
715035, -1299133, 707051, -1303496, 699039, -1307810, 691001, -1312075, 682938, -1316290, 674848, -1320456,
666733, -1324572, 658593, -1328638, 650429, -1332654, 642239, -1336620, 634026, -1340535, 625789, -1344400,
617528, -1348215, 609244, -1351978, 600937, -1355691, 592607, -1359353, 584255, -1362963, 575881, -1366523,
567485, -1370031, 559068, -1373487, 550630, -1376891, 542171, -1380244, 533692, -1383545, 525193, -1386793,
516674, -1389990, 508135, -1393134, 499577, -1396225, 491001, -1399265, 482406, -1402251, 473793, -1405185,
465162, -1408065, 456513, -1410893, 447848, -1413667, 439165, -1416389, 430466, -1419057, 421751, -1421671,
413020, -1424232, 404273, -1426740, 395511, -1429194, 386734, -1431593, 377943, -1433939, 369137, -1436231,
360318, -1438469, 351485, -1440653, 342638, -1442783, 333779, -1444858, 324908, -1446879, 316024, -1448845,
307128, -1450757, 298220, -1452614, 289301, -1454417, 280372, -1456164, 271432, -1457857, 262481, -1459495,
253521, -1461078, 244551, -1462607, 235572, -1464080, 226585, -1465497, 217588, -1466860, 208584, -1468168,
199571, -1469420, 190551, -1470617, 181524, -1471758, 172490, -1472844, 163450, -1473875, 154403, -1474850,
145351, -1475770, 136293, -1476634, 127230, -1477442, 118162, -1478195, 109090, -1478892, 100013, -1479534,
90933, -1480120, 81850, -1480650, 72763, -1481124, 63674, -1481543, 54582, -1481906, 45488, -1482213,
36392, -1482464, 27296, -1482659, 18198, -1482799, 9099, -1482882};
int32_t dct512_twiddle[1024] = {
741455, 0, 1048571, -3217, 1048556, -6434, 1048532, -9651, 1048497, -12868, 1048453, -16084,
1048398, -19301, 1048334, -22517, 1048260, -25733, 1048176, -28949, 1048083, -32165, 1047979, -35380,
1047865, -38595, 1047742, -41810, 1047609, -45024, 1047466, -48238, 1047313, -51451, 1047150, -54664,
1046978, -57876, 1046795, -61088, 1046603, -64299, 1046401, -67510, 1046188, -70720, 1045967, -73929,
1045735, -77138, 1045493, -80346, 1045242, -83553, 1044981, -86759, 1044709, -89965, 1044429, -93170,
1044138, -96374, 1043837, -99576, 1043527, -102778, 1043207, -105979, 1042877, -109179, 1042537, -112378,
1042187, -115576, 1041828, -118773, 1041458, -121969, 1041079, -125163, 1040690, -128357, 1040292, -131549,
1039883, -134740, 1039465, -137930, 1039037, -141118, 1038599, -144305, 1038151, -147491, 1037694, -150675,
1037227, -153858, 1036750, -157039, 1036263, -160219, 1035767, -163398, 1035261, -166575, 1034745, -169750,
1034219, -172924, 1033684, -176096, 1033138, -179267, 1032584, -182435, 1032019, -185602, 1031445, -188768,
1030861, -191931, 1030267, -195093, 1029664, -198253, 1029051, -201411, 1028428, -204567, 1027795, -207721,
1027153, -210873, 1026502, -214024, 1025840, -217172, 1025169, -220318, 1024488, -223462, 1023798, -226604,
1023098, -229744, 1022388, -232882, 1021669, -236018, 1020940, -239151, 1020201, -242282, 1019453, -245411,
1018696, -248537, 1017928, -251661, 1017151, -254783, 1016365, -257903, 1015569, -261020, 1014763, -264134,
1013948, -267246, 1013124, -270356, 1012289, -273462, 1011446, -276567, 1010592, -279669, 1009730, -282768,
1008857, -285864, 1007976, -288958, 1007084, -292049, 1006184, -295137, 1005273, -298223, 1004354, -301306,
1003425, -304386, 1002486, -307463, 1001538, -310537, 1000581, -313608, 999614, -316676, 998638, -319741,
997652, -322804, 996657, -325863, 995652, -328919, 994639, -331972, 993616, -335022, 992583, -338069,
991541, -341113, 990490, -344153, 989429, -347190, 988360, -350224, 987281, -353255, 986192, -356282,
985094, -359306, 983987, -362326, 982871, -365343, 981746, -368357, 980611, -371367, 979467, -374374,
978314, -377377, 977151, -380377, 975980, -383373, 974799, -386365, 973609, -389354, 972410, -392339,
971202, -395321, 969984, -398299, 968758, -401273, 967522, -404243, 966278, -407209, 965024, -410172,
963761, -413131, 962489, -416085, 961208, -419036, 959918, -421983, 958618, -424926, 957310, -427865,
955993, -430800, 954667, -433731, 953332, -436658, 951988, -439581, 950634, -442499, 949272, -445414,
947901, -448324, 946522, -451230, 945133, -454132, 943735, -457029, 942328, -459922, 940913, -462811,
939489, -465696, 938056, -468576, 936614, -471452, 935163, -474323, 933703, -477190, 932235, -480052,
930758, -482910, 929272, -485763, 927777, -488612, 926274, -491456, 924761, -494295, 923241, -497130,
921711, -499960, 920173, -502786, 918626, -505606, 917071, -508422, 915506, -511233, 913934, -514040,
912352, -516841, 910762, -519638, 909164, -522430, 907557, -525216, 905941, -527998, 904317, -530775,
902684, -533547, 901043, -536314, 899394, -539076, 897736, -541833, 896069, -544584, 894394, -547331,
892711, -550072, 891019, -552808, 889319, -555539, 887610, -558265, 885893, -560986, 884168, -563701,
882434, -566411, 880692, -569115, 878942, -571815, 877184, -574509, 875417, -577197, 873642, -579880,
871859, -582558, 870068, -585230, 868268, -587896, 866460, -590557, 864645, -593213, 862821, -595863,
860988, -598507, 859148, -601146, 857300, -603779, 855443, -606406, 853579, -609028, 851706, -611643,
849826, -614254, 847937, -616858, 846041, -619456, 844137, -622049, 842224, -624636, 840304, -627217,
838376, -629792, 836439, -632361, 834495, -634924, 832544, -637482, 830584, -640033, 828616, -642578,
826641, -645117, 824658, -647650, 822667, -650177, 820669, -652698, 818662, -655213, 816648, -657721,
814627, -660224, 812597, -662720, 810560, -665210, 808516, -667693, 806463, -670171, 804403, -672642,
802336, -675106, 800261, -677565, 798179, -680017, 796089, -682462, 793991, -684901, 791886, -687334,
789774, -689760, 787654, -692180, 785526, -694593, 783392, -697000, 781250, -699400, 779100, -701794,
776944, -704181, 774780, -706561, 772608, -708935, 770430, -711302, 768244, -713662, 766051, -716015,
763850, -718362, 761643, -720702, 759428, -723036, 757206, -725362, 754977, -727682, 752741, -729995,
750498, -732301, 748248, -734600, 745991, -736892, 743726, -739177, 741455, -741455, 739177, -743726,
736892, -745991, 734600, -748248, 732301, -750498, 729995, -752741, 727682, -754977, 725362, -757206,
723036, -759428, 720702, -761643, 718362, -763850, 716015, -766051, 713662, -768244, 711302, -770430,
708935, -772608, 706561, -774780, 704181, -776944, 701794, -779100, 699400, -781250, 697000, -783392,
694593, -785526, 692180, -787654, 689760, -789774, 687334, -791886, 684901, -793991, 682462, -796089,
680017, -798179, 677565, -800261, 675106, -802336, 672642, -804403, 670171, -806463, 667693, -808516,
665210, -810560, 662720, -812597, 660224, -814627, 657721, -816648, 655213, -818662, 652698, -820669,
650177, -822667, 647650, -824658, 645117, -826641, 642578, -828616, 640033, -830584, 637482, -832544,
634924, -834495, 632361, -836439, 629792, -838376, 627217, -840304, 624636, -842224, 622049, -844137,
619456, -846041, 616858, -847937, 614254, -849826, 611643, -851706, 609028, -853579, 606406, -855443,
603779, -857300, 601146, -859148, 598507, -860988, 595863, -862821, 593213, -864645, 590557, -866460,
587896, -868268, 585230, -870068, 582558, -871859, 579880, -873642, 577197, -875417, 574509, -877184,
571815, -878942, 569115, -880692, 566411, -882434, 563701, -884168, 560986, -885893, 558265, -887610,
555539, -889319, 552808, -891019, 550072, -892711, 547331, -894394, 544584, -896069, 541833, -897736,
539076, -899394, 536314, -901043, 533547, -902684, 530775, -904317, 527998, -905941, 525216, -907557,
522430, -909164, 519638, -910762, 516841, -912352, 514040, -913934, 511233, -915506, 508422, -917071,
505606, -918626, 502786, -920173, 499960, -921711, 497130, -923241, 494295, -924761, 491456, -926274,
488612, -927777, 485763, -929272, 482910, -930758, 480052, -932235, 477190, -933703, 474323, -935163,
471452, -936614, 468576, -938056, 465696, -939489, 462811, -940913, 459922, -942328, 457029, -943735,
454132, -945133, 451230, -946522, 448324, -947901, 445414, -949272, 442499, -950634, 439581, -951988,
436658, -953332, 433731, -954667, 430800, -955993, 427865, -957310, 424926, -958618, 421983, -959918,
419036, -961208, 416085, -962489, 413131, -963761, 410172, -965024, 407209, -966278, 404243, -967522,
401273, -968758, 398299, -969984, 395321, -971202, 392339, -972410, 389354, -973609, 386365, -974799,
383373, -975980, 380377, -977151, 377377, -978314, 374374, -979467, 371367, -980611, 368357, -981746,
365343, -982871, 362326, -983987, 359306, -985094, 356282, -986192, 353255, -987281, 350224, -988360,
347190, -989429, 344153, -990490, 341113, -991541, 338069, -992583, 335022, -993616, 331972, -994639,
328919, -995652, 325863, -996657, 322804, -997652, 319741, -998638, 316676, -999614, 313608, -1000581,
310537, -1001538, 307463, -1002486, 304386, -1003425, 301306, -1004354, 298223, -1005273, 295137, -1006184,
292049, -1007084, 288958, -1007976, 285864, -1008857, 282768, -1009730, 279669, -1010592, 276567, -1011446,
273462, -1012289, 270356, -1013124, 267246, -1013948, 264134, -1014763, 261020, -1015569, 257903, -1016365,
254783, -1017151, 251661, -1017928, 248537, -1018696, 245411, -1019453, 242282, -1020201, 239151, -1020940,
236018, -1021669, 232882, -1022388, 229744, -1023098, 226604, -1023798, 223462, -1024488, 220318, -1025169,
217172, -1025840, 214024, -1026502, 210873, -1027153, 207721, -1027795, 204567, -1028428, 201411, -1029051,
198253, -1029664, 195093, -1030267, 191931, -1030861, 188768, -1031445, 185602, -1032019, 182435, -1032584,
179267, -1033138, 176096, -1033684, 172924, -1034219, 169750, -1034745, 166575, -1035261, 163398, -1035767,
160219, -1036263, 157039, -1036750, 153858, -1037227, 150675, -1037694, 147491, -1038151, 144305, -1038599,
141118, -1039037, 137930, -1039465, 134740, -1039883, 131549, -1040292, 128357, -1040690, 125163, -1041079,
121969, -1041458, 118773, -1041828, 115576, -1042187, 112378, -1042537, 109179, -1042877, 105979, -1043207,
102778, -1043527, 99576, -1043837, 96374, -1044138, 93170, -1044429, 89965, -1044709, 86759, -1044981,
83553, -1045242, 80346, -1045493, 77138, -1045735, 73929, -1045967, 70720, -1046188, 67510, -1046401,
64299, -1046603, 61088, -1046795, 57876, -1046978, 54664, -1047150, 51451, -1047313, 48238, -1047466,
45024, -1047609, 41810, -1047742, 38595, -1047865, 35380, -1047979, 32165, -1048083, 28949, -1048176,
25733, -1048260, 22517, -1048334, 19301, -1048398, 16084, -1048453, 12868, -1048497, 9651, -1048532,
6434, -1048556, 3217, -1048571};
/*!
* @brief MATLAB script for calculating twiddle factor table for IDCT is below.
*
* N = 32;
* Q=exp(pi*1i*((0:(N-1))')/(2*N)); % Generate e^(jnPi/2N) table
* Q(2:N)=Q(2:N)/sqrt(2); % scale twiddle by dividing by sqrt(2)
* int32(Q*1024*1024*16*1/sqrt(1/N))
*
* Note that for twiddle table, we can already scale by 1/sqrt(1/N) by running following command
*/
int32_t idct16_twiddle[32] = {67108864, 0, 47224633, 4651220, 46541334, 9257647, 45409817, 13774917,
43840978, 18159528, 41849927, 22369252, 39455838, 26363548, 36681768, 30103949,
33554432, 33554432, 30103949, 36681768, 26363548, 39455838, 22369252, 41849927,
18159528, 43840978, 13774917, 45409817, 9257647, 46541334, 4651220, 47224633};
int32_t idct32_twiddle[64] = {
94906266, 0, 67028028, 3292876, 66785716, 6577819, 66382512, 9846915, 65819386, 13092290, 65097695,
16306124, 64219179, 19480675, 63185953, 22608295, 62000506, 25681450, 60665695, 28692737, 59184734, 31634900,
57561193, 34500851, 55798981, 37283687, 53902345, 39976704, 51875853, 42573413, 49724388, 45067559, 47453133,
47453133, 45067559, 49724388, 42573413, 51875853, 39976704, 53902345, 37283687, 55798981, 34500851, 57561193,
31634900, 59184734, 28692737, 60665695, 25681450, 62000506, 22608295, 63185953, 19480675, 64219179, 16306124,
65097695, 13092290, 65819386, 9846915, 66382512, 6577819, 66785716, 3292876, 67028028};
int32_t idct64_twiddle[128] = {
134217728, 0, 94877682, 2329116, 94791947, 4656830, 94649113, 6981738, 94449266, 9302441, 94192526,
11617540, 93879049, 13925641, 93509022, 16225354, 93082668, 18515294, 92600246, 20794080, 92062044, 23060341,
91468387, 25312712, 90819634, 27549835, 90116174, 29770363, 89358431, 31972958, 88546862, 34156294, 87681956,
36319055, 86764234, 38459940, 85794248, 40577657, 84772583, 42670932, 83699854, 44738504, 82576707, 46779127,
81403819, 48791572, 80181897, 50774626, 78911676, 52727096, 77593921, 54647805, 76229427, 56535596, 74819015,
58389333, 73363535, 60207898, 71863864, 61990195, 70320904, 63735153, 68735586, 65441718, 67108864, 67108864,
65441718, 68735586, 63735153, 70320904, 61990195, 71863864, 60207898, 73363535, 58389333, 74819015, 56535596,
76229427, 54647805, 77593921, 52727096, 78911676, 50774626, 80181897, 48791572, 81403819, 46779127, 82576707,
44738504, 83699854, 42670932, 84772583, 40577657, 85794248, 38459940, 86764234, 36319055, 87681956, 34156294,
88546862, 31972958, 89358431, 29770363, 90116174, 27549835, 90819634, 25312712, 91468387, 23060341, 92062044,
20794080, 92600246, 18515294, 93082668, 16225354, 93509022, 13925641, 93879049, 11617540, 94192526, 9302441,
94449266, 6981738, 94649113, 4656830, 94791947, 2329116, 94877682};
int32_t idct128_twiddle[256] = {
189812531, 0, 134207622, 1647058, 134177304, 3293868, 134126780, 4940182, 134056057, 6585752,
133965145, 8230330, 133854059, 9873669, 133722815, 11515520, 133571433, 13155638, 133399935, 14793774,
133208348, 16429683, 132996700, 18063117, 132765024, 19693831, 132513353, 21321579, 132241727, 22946116,
131950185, 24567198, 131638772, 26184580, 131307535, 27798018, 130956523, 29407271, 130585790, 31012094,
130195391, 32612248, 129785385, 34207490, 129355834, 35797580, 128906802, 37382280, 128438358, 38961350,
127950571, 40534552, 127443515, 42101651, 126917267, 43662408, 126371905, 45216591, 125807513, 46763964,
125224174, 48304294, 124621977, 49837350, 124001012, 51362901, 123361373, 52880716, 122703156, 54390568,
122026461, 55892229, 121331389, 57385473, 120618045, 58870075, 119886536, 60345811, 119136973, 61812459,
118369468, 63269799, 117584138, 64717610, 116781099, 66155675, 115960474, 67583778, 115122385, 69001702,
114266960, 70409235, 113394326, 71806165, 112504616, 73192281, 111597962, 74567374, 110674503, 75931238,
109734376, 77283667, 108777724, 78624457, 107804690, 79953407, 106815421, 81270316, 105810066, 82574986,
104788777, 83867221, 103751707, 85146825, 102699012, 86413607, 101630851, 87667375, 100547385, 88907941,
99448777, 90135117, 98335192, 91348720, 97206798, 92548565, 96063765, 93734473, 94906266, 94906266,
93734473, 96063765, 92548565, 97206798, 91348720, 98335192, 90135117, 99448777, 88907941, 100547385,
87667375, 101630851, 86413607, 102699012, 85146825, 103751707, 83867221, 104788777, 82574986, 105810066,
81270316, 106815421, 79953407, 107804690, 78624457, 108777724, 77283667, 109734376, 75931238, 110674503,
74567374, 111597962, 73192281, 112504616, 71806165, 113394326, 70409235, 114266960, 69001702, 115122385,
67583778, 115960474, 66155675, 116781099, 64717610, 117584138, 63269799, 118369468, 61812459, 119136973,
60345811, 119886536, 58870075, 120618045, 57385473, 121331389, 55892229, 122026461, 54390568, 122703156,
52880716, 123361373, 51362901, 124001012, 49837350, 124621977, 48304294, 125224174, 46763964, 125807513,
45216591, 126371905, 43662408, 126917267, 42101651, 127443515, 40534552, 127950571, 38961350, 128438358,
37382280, 128906802, 35797580, 129355834, 34207490, 129785385, 32612248, 130195391, 31012094, 130585790,
29407271, 130956523, 27798018, 131307535, 26184580, 131638772, 24567198, 131950185, 22946116, 132241727,
21321579, 132513353, 19693831, 132765024, 18063117, 132996700, 16429683, 133208348, 14793774, 133399935,
13155638, 133571433, 11515520, 133722815, 9873669, 133854059, 8230330, 133965145, 6585752, 134056057,
4940182, 134126780, 3293868, 134177304, 1647058, 134207622};
int32_t idct256_twiddle[512] = {
268435456, 0, 189808958, 1164668, 189798239, 2329292, 189780374, 3493828, 189755363, 4658233,
189723209, 5822462, 189683911, 6986472, 189637472, 8150219, 189583894, 9313659, 189523177, 10476749,
189455325, 11639444, 189380341, 12801701, 189298226, 13963476, 189208984, 15124725, 189112619, 16285405,
189009133, 17445472, 188898532, 18604882, 188780819, 19763591, 188655998, 20921556, 188524074, 22078734,
188385053, 23235080, 188238939, 24390552, 188085737, 25545105, 187925455, 26698696, 187758097, 27851283,
187583670, 29002821, 187402181, 30153266, 187213637, 31302577, 187018043, 32450709, 186815409, 33597619,
186605741, 34743264, 186389048, 35887602, 186165337, 37030588, 185934617, 38172180, 185696897, 39312335,
185452185, 40451009, 185200491, 41588161, 184941825, 42723747, 184676195, 43857724, 184403613, 44990051,
184124088, 46120683, 183837630, 47249579, 183544252, 48376696, 183243963, 49501992, 182936775, 50625424,
182622699, 51746950, 182301748, 52866527, 181973933, 53984115, 181639267, 55099669, 181297763, 56213150,
180949433, 57324514, 180594290, 58433719, 180232347, 59540725, 179863620, 60645489, 179488120, 61747970,
179105863, 62848126, 178716862, 63945916, 178321133, 65041298, 177918690, 66134232, 177509549, 67224675,
177093725, 68312588, 176671233, 69397929, 176242089, 70480656, 175806311, 71560731, 175363913, 72638111,
174914912, 73712756, 174459327, 74784626, 173997173, 75853681, 173528468, 76919880, 173053230, 77983182,
172571476, 79043549, 172083225, 80100940, 171588496, 81155315, 171087306, 82206634, 170579675, 83254858,
170065622, 84299948, 169545166, 85341865, 169018326, 86380568, 168485123, 87416018, 167945577, 88448178,
167399708, 89477008, 166847536, 90502469, 166289082, 91524522, 165724368, 92543130, 165153414, 93558254,
164576243, 94569855, 163992875, 95577895, 163403333, 96582337, 162807639, 97583143, 162205815, 98580275,
161597884, 99573696, 160983869, 100563367, 160363794, 101549252, 159737680, 102531315, 159105553, 103509516,
158467436, 104483821, 157823352, 105454192, 157173326, 106420593, 156517383, 107382987, 155855547, 108341338,
155187843, 109295610, 154514296, 110245768, 153834932, 111191774, 153149776, 112133594, 152458855, 113071193,
151762193, 114004534, 151059817, 114933583, 150351754, 115858305, 149638031, 116778666, 148918674, 117694629,
148193710, 118606161, 147463166, 119513228, 146727071, 120415795, 145985451, 121313829, 145238336, 122207295,
144485752, 123096160, 143727728, 123980391, 142964293, 124859954, 142195475, 125734815, 141421304, 126604944,
140641809, 127470305, 139857018, 128330867, 139066962, 129186598, 138271670, 130037465, 137471172, 130883436,
136665499, 131724480, 135854680, 132560564, 135038746, 133391657, 134217728, 134217728, 133391657, 135038746,
132560564, 135854680, 131724480, 136665499, 130883436, 137471172, 130037465, 138271670, 129186598, 139066962,
128330867, 139857018, 127470305, 140641809, 126604944, 141421304, 125734815, 142195475, 124859954, 142964293,
123980391, 143727728, 123096160, 144485752, 122207295, 145238336, 121313829, 145985451, 120415795, 146727071,
119513228, 147463166, 118606161, 148193710, 117694629, 148918674, 116778666, 149638031, 115858305, 150351754,
114933583, 151059817, 114004534, 151762193, 113071193, 152458855, 112133594, 153149776, 111191774, 153834932,
110245768, 154514296, 109295610, 155187843, 108341338, 155855547, 107382987, 156517383, 106420593, 157173326,
105454192, 157823352, 104483821, 158467436, 103509516, 159105553, 102531315, 159737680, 101549252, 160363794,
100563367, 160983869, 99573696, 161597884, 98580275, 162205815, 97583143, 162807639, 96582337, 163403333,
95577895, 163992875, 94569855, 164576243, 93558254, 165153414, 92543130, 165724368, 91524522, 166289082,
90502469, 166847536, 89477008, 167399708, 88448178, 167945577, 87416018, 168485123, 86380568, 169018326,
85341865, 169545166, 84299948, 170065622, 83254858, 170579675, 82206634, 171087306, 81155315, 171588496,
80100940, 172083225, 79043549, 172571476, 77983182, 173053230, 76919880, 173528468, 75853681, 173997173,
74784626, 174459327, 73712756, 174914912, 72638111, 175363913, 71560731, 175806311, 70480656, 176242089,
69397929, 176671233, 68312588, 177093725, 67224675, 177509549, 66134232, 177918690, 65041298, 178321133,
63945916, 178716862, 62848126, 179105863, 61747970, 179488120, 60645489, 179863620, 59540725, 180232347,
58433719, 180594290, 57324514, 180949433, 56213150, 181297763, 55099669, 181639267, 53984115, 181973933,
52866527, 182301748, 51746950, 182622699, 50625424, 182936775, 49501992, 183243963, 48376696, 183544252,
47249579, 183837630, 46120683, 184124088, 44990051, 184403613, 43857724, 184676195, 42723747, 184941825,
41588161, 185200491, 40451009, 185452185, 39312335, 185696897, 38172180, 185934617, 37030588, 186165337,
35887602, 186389048, 34743264, 186605741, 33597619, 186815409, 32450709, 187018043, 31302577, 187213637,
30153266, 187402181, 29002821, 187583670, 27851283, 187758097, 26698696, 187925455, 25545105, 188085737,
24390552, 188238939, 23235080, 188385053, 22078734, 188524074, 20921556, 188655998, 19763591, 188780819,
18604882, 188898532, 17445472, 189009133, 16285405, 189112619, 15124725, 189208984, 13963476, 189298226,
12801701, 189380341, 11639444, 189455325, 10476749, 189523177, 9313659, 189583894, 8150219, 189637472,
6986472, 189683911, 5822462, 189723209, 4658233, 189755363, 3493828, 189780374, 2329292, 189798239,
1164668, 189808958};
int32_t idct512_twiddle[1024] = {
379625062, 0, 268434193, 823548, 268430403, 1647089, 268424086, 2470614, 268415243, 3294116,
268403874, 4117587, 268389978, 4941019, 268373556, 5764405, 268354608, 6587736, 268333134, 7411005,
268309135, 8234205, 268282610, 9057327, 268253560, 9880364, 268221985, 10703307, 268187885, 11526151,
268151262, 12348885, 268112114, 13171504, 268070442, 13993998, 268026248, 14816361, 267979530, 15638584,
267930291, 16460660, 267878529, 17282581, 267824246, 18104339, 267767443, 18925927, 267708119, 19747337,
267646275, 20568561, 267581912, 21389592, 267515030, 22210421, 267445630, 23031041, 267373713, 23851444,
267299280, 24671623, 267222331, 25491569, 267142866, 26311276, 267060887, 27130735, 266976394, 27949938,
266889388, 28768879, 266799871, 29587548, 266707842, 30405940, 266613302, 31224045, 266516254, 32041856,
266416696, 32859365, 266314632, 33676566, 266210060, 34493449, 266102983, 35310008, 265993401, 36126234,
265881315, 36942120, 265766727, 37757659, 265649638, 38572842, 265530048, 39387662, 265407958, 40202111,
265283371, 41016182, 265156286, 41829867, 265026706, 42643158, 264894632, 43456048, 264760064, 44268529,
264623004, 45080593, 264483453, 45892233, 264341413, 46703440, 264196885, 47514209, 264049870, 48324530,
263900370, 49134396, 263748386, 49943799, 263593919, 50752733, 263436971, 51561189, 263277544, 52369160,
263115639, 53176637, 262951257, 53983614, 262784400, 54790083, 262615070, 55596037, 262443267, 56401467,
262268995, 57206366, 262092254, 58010727, 261913046, 58814541, 261731373, 59617802, 261547237, 60420502,
261360638, 61222634, 261171580, 62024189, 260980063, 62825160, 260786090, 63625540, 260589662, 64425321,
260390782, 65224495, 260189450, 66023056, 259985670, 66820995, 259779443, 67618306, 259570770, 68414980,
259359654, 69211009, 259146097, 70006388, 258930101, 70801108, 258711668, 71595161, 258490799, 72388540,
258267498, 73181238, 258041766, 73973247, 257813604, 74764560, 257583017, 75555169, 257350004, 76345067,
257114570, 77134246, 256876715, 77922700, 256636443, 78710420, 256393755, 79497399, 256148654, 80283630,
255901142, 81069105, 255651221, 81853817, 255398894, 82637759, 255144163, 83420922, 254887030, 84203301,
254627499, 84984887, 254365570, 85765673, 254101248, 86545652, 253834534, 87324817, 253565430, 88103159,
253293940, 88880672, 253020066, 89657349, 252743810, 90433181, 252465176, 91208163, 252184165, 91982286,
251900781, 92755543, 251615025, 93527927, 251326901, 94299431, 251036412, 95070047, 250743560, 95839769,
250448347, 96608588, 250150778, 97376498, 249850854, 98143492, 249548578, 98909562, 249243953, 99674700,
248936982, 100438901, 248627669, 101202156, 248316015, 101964459, 248002024, 102725802, 247685698, 103486178,
247367041, 104245580, 247046056, 105004000, 246722746, 105761433, 246397113, 106517870, 246069161, 107273304,
245738894, 108027729, 245406313, 108781137, 245071422, 109533521, 244734224, 110284874, 244394723, 111035189,
244052922, 111784459, 243708824, 112532677, 243362431, 113279835, 243013748, 114025927, 242662778, 114770946,
242309524, 115514885, 241953989, 116257737, 241596176, 116999494, 241236090, 117740150, 240873733, 118479698,
240509109, 119218130, 240142221, 119955441, 239773073, 120691622, 239401668, 121426668, 239028009, 122160570,
238652101, 122893323, 238273946, 123624919, 237893549, 124355351, 237510913, 125084613, 237126041, 125812698,
236738937, 126539598, 236349605, 127265307, 235958048, 127989819, 235564270, 128713125, 235168275, 129435221,
234770067, 130156098, 234369649, 130875750, 233967025, 131594170, 233562198, 132311351, 233155174, 133027287,
232745954, 133741971, 232334544, 134455396, 231920948, 135167556, 231505168, 135878443, 231087209, 136588051,
230667075, 137296374, 230244771, 138003405, 229820298, 138709136, 229393663, 139413562, 228964869, 140116676,
228533919, 140818471, 228100819, 141518940, 227665572, 142218078, 227228181, 142915876, 226788652, 143612330,
226346988, 144307432, 225903194, 145001176, 225457274, 145693554, 225009231, 146384562, 224559071, 147074192,
224106797, 147762437, 223652413, 148449292, 223195925, 149134749, 222737335, 149818802, 222276649, 150501446,
221813871, 151182673, 221349006, 151862477, 220882056, 152540851, 220413028, 153217790, 219941925, 153893286,
219468752, 154567334, 218993513, 155239928, 218516213, 155911060, 218036857, 156580724, 217555448, 157248915,
217071991, 157915626, 216586491, 158580850, 216098952, 159244582, 215609380, 159906814, 215117778, 160567542,
214624151, 161226759, 214128505, 161884457, 213630842, 162540633, 213131169, 163195278, 212629490, 163848387,
212125810, 164499954, 211620133, 165149973, 211112464, 165798437, 210602808, 166445340, 210091170, 167090677,
209577554, 167734442, 209061966, 168376627, 208544410, 169017228, 208024891, 169656238, 207503414, 170293651,
206979983, 170929461, 206454605, 171563662, 205927284, 172196248, 205398024, 172827214, 204866831, 173456553,
204333709, 174084259, 203798665, 174710327, 203261702, 175334750, 202722826, 175957523, 202182042, 176578640,
201639355, 177198094, 201094770, 177815881, 200548292, 178431995, 199999926, 179046428, 199449678, 179659177,
198897553, 180270234, 198343556, 180879595, 197787692, 181487253, 197229966, 182093203, 196670384, 182697439,
196108950, 183299956, 195545671, 183900747, 194980551, 184499807, 194413596, 185097131, 193844811, 185692712,
193274202, 186286546, 192701773, 186878626, 192127530, 187468947, 191551480, 188057504, 190973626, 188644290,
190393975, 189229301, 189812531, 189812531, 189229301, 190393975, 188644290, 190973626, 188057504, 191551480,
187468947, 192127530, 186878626, 192701773, 186286546, 193274202, 185692712, 193844811, 185097131, 194413596,
184499807, 194980551, 183900747, 195545671, 183299956, 196108950, 182697439, 196670384, 182093203, 197229966,
181487253, 197787692, 180879595, 198343556, 180270234, 198897553, 179659177, 199449678, 179046428, 199999926,
178431995, 200548292, 177815881, 201094770, 177198094, 201639355, 176578640, 202182042, 175957523, 202722826,
175334750, 203261702, 174710327, 203798665, 174084259, 204333709, 173456553, 204866831, 172827214, 205398024,
172196248, 205927284, 171563662, 206454605, 170929461, 206979983, 170293651, 207503414, 169656238, 208024891,
169017228, 208544410, 168376627, 209061966, 167734442, 209577554, 167090677, 210091170, 166445340, 210602808,
165798437, 211112464, 165149973, 211620133, 164499954, 212125810, 163848387, 212629490, 163195278, 213131169,
162540633, 213630842, 161884457, 214128505, 161226759, 214624151, 160567542, 215117778, 159906814, 215609380,
159244582, 216098952, 158580850, 216586491, 157915626, 217071991, 157248915, 217555448, 156580724, 218036857,
155911060, 218516213, 155239928, 218993513, 154567334, 219468752, 153893286, 219941925, 153217790, 220413028,
152540851, 220882056, 151862477, 221349006, 151182673, 221813871, 150501446, 222276649, 149818802, 222737335,
149134749, 223195925, 148449292, 223652413, 147762437, 224106797, 147074192, 224559071, 146384562, 225009231,
145693554, 225457274, 145001176, 225903194, 144307432, 226346988, 143612330, 226788652, 142915876, 227228181,
142218078, 227665572, 141518940, 228100819, 140818471, 228533919, 140116676, 228964869, 139413562, 229393663,
138709136, 229820298, 138003405, 230244771, 137296374, 230667075, 136588051, 231087209, 135878443, 231505168,
135167556, 231920948, 134455396, 232334544, 133741971, 232745954, 133027287, 233155174, 132311351, 233562198,
131594170, 233967025, 130875750, 234369649, 130156098, 234770067, 129435221, 235168275, 128713125, 235564270,
127989819, 235958048, 127265307, 236349605, 126539598, 236738937, 125812698, 237126041, 125084613, 237510913,
124355351, 237893549, 123624919, 238273946, 122893323, 238652101, 122160570, 239028009, 121426668, 239401668,
120691622, 239773073, 119955441, 240142221, 119218130, 240509109, 118479698, 240873733, 117740150, 241236090,
116999494, 241596176, 116257737, 241953989, 115514885, 242309524, 114770946, 242662778, 114025927, 243013748,
113279835, 243362431, 112532677, 243708824, 111784459, 244052922, 111035189, 244394723, 110284874, 244734224,
109533521, 245071422, 108781137, 245406313, 108027729, 245738894, 107273304, 246069161, 106517870, 246397113,
105761433, 246722746, 105004000, 247046056, 104245580, 247367041, 103486178, 247685698, 102725802, 248002024,
101964459, 248316015, 101202156, 248627669, 100438901, 248936982, 99674700, 249243953, 98909562, 249548578,
98143492, 249850854, 97376498, 250150778, 96608588, 250448347, 95839769, 250743560, 95070047, 251036412,
94299431, 251326901, 93527927, 251615025, 92755543, 251900781, 91982286, 252184165, 91208163, 252465176,
90433181, 252743810, 89657349, 253020066, 88880672, 253293940, 88103159, 253565430, 87324817, 253834534,
86545652, 254101248, 85765673, 254365570, 84984887, 254627499, 84203301, 254887030, 83420922, 255144163,
82637759, 255398894, 81853817, 255651221, 81069105, 255901142, 80283630, 256148654, 79497399, 256393755,
78710420, 256636443, 77922700, 256876715, 77134246, 257114570, 76345067, 257350004, 75555169, 257583017,
74764560, 257813604, 73973247, 258041766, 73181238, 258267498, 72388540, 258490799, 71595161, 258711668,
70801108, 258930101, 70006388, 259146097, 69211009, 259359654, 68414980, 259570770, 67618306, 259779443,
66820995, 259985670, 66023056, 260189450, 65224495, 260390782, 64425321, 260589662, 63625540, 260786090,
62825160, 260980063, 62024189, 261171580, 61222634, 261360638, 60420502, 261547237, 59617802, 261731373,
58814541, 261913046, 58010727, 262092254, 57206366, 262268995, 56401467, 262443267, 55596037, 262615070,
54790083, 262784400, 53983614, 262951257, 53176637, 263115639, 52369160, 263277544, 51561189, 263436971,
50752733, 263593919, 49943799, 263748386, 49134396, 263900370, 48324530, 264049870, 47514209, 264196885,
46703440, 264341413, 45892233, 264483453, 45080593, 264623004, 44268529, 264760064, 43456048, 264894632,
42643158, 265026706, 41829867, 265156286, 41016182, 265283371, 40202111, 265407958, 39387662, 265530048,
38572842, 265649638, 37757659, 265766727, 36942120, 265881315, 36126234, 265993401, 35310008, 266102983,
34493449, 266210060, 33676566, 266314632, 32859365, 266416696, 32041856, 266516254, 31224045, 266613302,
30405940, 266707842, 29587548, 266799871, 28768879, 266889388, 27949938, 266976394, 27130735, 267060887,
26311276, 267142866, 25491569, 267222331, 24671623, 267299280, 23851444, 267373713, 23031041, 267445630,
22210421, 267515030, 21389592, 267581912, 20568561, 267646275, 19747337, 267708119, 18925927, 267767443,
18104339, 267824246, 17282581, 267878529, 16460660, 267930291, 15638584, 267979530, 14816361, 268026248,
13993998, 268070442, 13171504, 268112114, 12348885, 268151262, 11526151, 268187885, 10703307, 268221985,
9880364, 268253560, 9057327, 268282610, 8234205, 268309135, 7411005, 268333134, 6587736, 268354608,
5764405, 268373556, 4941019, 268389978, 4117587, 268403874, 3294116, 268415243, 2470614, 268424086,
1647089, 268430403, 823548, 268434193};
/*
* Using python [int(2147483648.0 * np.cos(np.pi * (2.0*n+1.0) / (4.0*N))) for n in xrange(N)]
* Q31.
*/
int32_t dct16_cosFactor[16] = {2144896909, 2124240380, 2083126254, 2021950483, 1941302224, 1841958164,
1724875039, 1591180425, 1442161874, 1279254515, 1104027236, 918167571,
723465451, 521795963, 315101294, 105372028};
int32_t dct32_cosFactor[32] = {2146836866, 2141664948, 2131333571, 2115867625, 2095304369, 2069693341, 2039096241,
2003586779, 1963250501, 1918184580, 1868497585, 1814309216, 1755750017, 1692961062,
1626093615, 1555308767, 1480777044, 1402677999, 1321199780, 1236538675, 1148898640,
1058490807, 965532978, 870249095, 772868705, 673626408, 572761285, 470516330,
367137860, 262874923, 157978697, 52701886};
int32_t dct64_cosFactor[64] = {
2147321946, 2146028479, 2143442326, 2139565042, 2134398965, 2127947206, 2120213651, 2111202958,
2100920556, 2089372637, 2076566159, 2062508835, 2047209133, 2030676268, 2012920200, 1993951624,
1973781967, 1952423376, 1929888719, 1906191570, 1881346201, 1855367580, 1828271355, 1800073848,
1770792044, 1740443580, 1709046739, 1676620431, 1643184190, 1608758157, 1573363068, 1537020243,
1499751575, 1461579513, 1422527050, 1382617710, 1341875533, 1300325060, 1257991319, 1214899812,
1171076495, 1126547765, 1081340445, 1035481765, 988999351, 941921200, 894275670, 846091463,
797397602, 748223418, 698598532, 648552837, 598116478, 547319836, 496193509, 444768293,
393075166, 341145265, 289009870, 236700387, 184248325, 131685278, 79042909, 26352927};
int32_t dct128_cosFactor[128] = {
2147443222, 2147119825, 2146473079, 2145503083, 2144209982, 2142593970, 2140655292, 2138394239, 2135811152,
2132906419, 2129680479, 2126133817, 2122266966, 2118080510, 2113575079, 2108751351, 2103610053, 2098151959,
2092377892, 2086288719, 2079885360, 2073168777, 2066139983, 2058800035, 2051150040, 2043191149, 2034924561,
2026351521, 2017473320, 2008291295, 1998806829, 1989021349, 1978936330, 1968553291, 1957873795, 1946899450,
1935631910, 1924072870, 1912224072, 1900087300, 1887664382, 1874957189, 1861967634, 1848697673, 1835149306,
1821324572, 1807225552, 1792854372, 1778213194, 1763304224, 1748129706, 1732691927, 1716993211, 1701035922,
1684822463, 1668355276, 1651636841, 1634669675, 1617456334, 1599999411, 1582301533, 1564365366, 1546193612,
1527789007, 1509154322, 1490292364, 1471205974, 1451898025, 1432371426, 1412629117, 1392674071, 1372509294,
1352137822, 1331562723, 1310787095, 1289814068, 1268646799, 1247288477, 1225742318, 1204011566, 1182099495,
1160009404, 1137744620, 1115308496, 1092704410, 1069935767, 1047005996, 1023918549, 1000676905, 977284561,
953745043, 930061894, 906238680, 882278991, 858186434, 833964637, 809617248, 785147934, 760560379,
735858287, 711045377, 686125386, 661102068, 635979189, 610760535, 585449902, 560051103, 534567962,
509004318, 483364019, 457650927, 431868914, 406021864, 380113668, 354148229, 328129456, 302061268,
275947591, 249792357, 223599506, 197372981, 171116732, 144834714, 118530884, 92209204, 65873638,
39528151, 13176711};
int32_t dct256_cosFactor[256] = {
2147473541, 2147392690, 2147230991, 2146988449, 2146665075, 2146260880, 2145775880, 2145210092, 2144563538,
2143836243, 2143028234, 2142139540, 2141170197, 2140120239, 2138989707, 2137778644, 2136487094, 2135115107,
2133662734, 2132130029, 2130517052, 2128823861, 2127050522, 2125197100, 2123263665, 2121250291, 2119157054,
2116984031, 2114731305, 2112398960, 2109987085, 2107495770, 2104925109, 2102275198, 2099546138, 2096738032,
2093850984, 2090885105, 2087840504, 2084717298, 2081515603, 2078235540, 2074877233, 2071440808, 2067926394,
2064334124, 2060664133, 2056916559, 2053091544, 2049189230, 2045209766, 2041153301, 2037019988, 2032809982,
2028523441, 2024160528, 2019721407, 2015206244, 2010615210, 2005948477, 2001206222, 1996388622, 1991495859,
1986528118, 1981485585, 1976368450, 1971176906, 1965911148, 1960571375, 1955157787, 1949670589, 1944109987,
1938476190, 1932769411, 1926989864, 1921137766, 1915213340, 1909216806, 1903148391, 1897008325, 1890796836,
1884514161, 1878160534, 1871736196, 1865241388, 1858676354, 1852041343, 1845336603, 1838562387, 1831718951,
1824806551, 1817825449, 1810775906, 1803658189, 1796472564, 1789219304, 1781898681, 1774510970, 1767056450,
1759535401, 1751948107, 1744294852, 1736575926, 1728791619, 1720942224, 1713028037, 1705049354, 1697006478,
1688899711, 1680729357, 1672495725, 1664199124, 1655839867, 1647418269, 1638934646, 1630389318, 1621782607,
1613114837, 1604386334, 1595597427, 1586748446, 1577839726, 1568871600, 1559844408, 1550758488, 1541614183,
1532411837, 1523151796, 1513834410, 1504460029, 1495029005, 1485541695, 1475998455, 1466399644, 1456745625,
1447036759, 1437273414, 1427455956, 1417584755, 1407660183, 1397682613, 1387652421, 1377569985, 1367435684,
1357249900, 1347013016, 1336725418, 1326387494, 1315999631, 1305562222, 1295075659, 1284540337, 1273956653,
1263325005, 1252645793, 1241919421, 1231146290, 1220326808, 1209461381, 1198550419, 1187594332, 1176593532,
1165548435, 1154459455, 1143327011, 1132151521, 1120933406, 1109673088, 1098370992, 1087027543, 1075643168,
1064218296, 1052753356, 1041248781, 1029705003, 1018122458, 1006501581, 994842809, 983146583, 971413341,
959643527, 947837582, 935995951, 924119081, 912207419, 900261412, 888281511, 876268167, 864221832,
852142959, 840032003, 827889421, 815715669, 803511206, 791276492, 779011986, 766718151, 754395449,
742044345, 729665303, 717258789, 704825272, 692365218, 679879097, 667367378, 654830534, 642269036,
629683357, 617073970, 604441351, 591785975, 579108319, 566408860, 553688075, 540946445, 528184448,
515402566, 502601279, 489781069, 476942419, 464085812, 451211733, 438320667, 425413097, 412489511,
399550395, 386596237, 373627523, 360644742, 347648383, 334638935, 321616889, 308582733, 295536960,
282480060, 269412525, 256334846, 243247517, 230151030, 217045877, 203932553, 190811551, 177683365,
164548489, 151407418, 138260647, 125108670, 111951983, 98791081, 85626459, 72458614, 59288041,
46115236, 32940694, 19764912, 6588386};
int32_t dct512_cosFactor[512] = {
2147481121, 2147460908, 2147420482, 2147359844, 2147278995, 2147177934, 2147056663, 2146915183, 2146753496,
2146571603, 2146369505, 2146147205, 2145904704, 2145642006, 2145359112, 2145056024, 2144732747, 2144389283,
2144025635, 2143641806, 2143237801, 2142813623, 2142369276, 2141904764, 2141420092, 2140915263, 2140390284,
2139845158, 2139279892, 2138694490, 2138088957, 2137463300, 2136817525, 2136151636, 2135465642, 2134759548,
2134033360, 2133287087, 2132520733, 2131734308, 2130927818, 2130101272, 2129254675, 2128388038, 2127501367,
2126594671, 2125667959, 2124721240, 2123754521, 2122767813, 2121761125, 2120734466, 2119687846, 2118621275,
2117534762, 2116428318, 2115301954, 2114155679, 2112989506, 2111803444, 2110597505, 2109371700, 2108126041,
2106860539, 2105575207, 2104270057, 2102945100, 2101600350, 2100235818, 2098851518, 2097447463, 2096023667,
2094580141, 2093116901, 2091633959, 2090131330, 2088609028, 2087067067, 2085505462, 2083924228, 2082323378,
2080702929, 2079062896, 2077403294, 2075724138, 2074025445, 2072307230, 2070569510, 2068812302, 2067035620,
2065239483, 2063423907, 2061588910, 2059734507, 2057860718, 2055967560, 2054055050, 2052123206, 2050172047,
2048201591, 2046211857, 2044202863, 2042174628, 2040127171, 2038060512, 2035974670, 2033869664, 2031745515,
2029602243, 2027439867, 2025258408, 2023057886, 2020838323, 2018599739, 2016342154, 2014065592, 2011770072,
2009455617, 2007122248, 2004769987, 2002398856, 2000008878, 1997600075, 1995172471, 1992726086, 1990260946,
1987777072, 1985274489, 1982753219, 1980213287, 1977654717, 1975077532, 1972481757, 1969867416, 1967234534,
1964583136, 1961913246, 1959224890, 1956518093, 1953792881, 1951049278, 1948287312, 1945507007, 1942708391,
1939891490, 1937056329, 1934202936, 1931331337, 1928441560, 1925533632, 1922607580, 1919663432, 1916701215,
1913720957, 1910722687, 1907706432, 1904672221, 1901620083, 1898550046, 1895462139, 1892356391, 1889232832,
1886091490, 1882932396, 1879755579, 1876561069, 1873348896, 1870119091, 1866871683, 1863606703, 1860324183,
1857024152, 1853706643, 1850371685, 1847019311, 1843649553, 1840262441, 1836858008, 1833436286, 1829997306,
1826541102, 1823067706, 1819577151, 1816069469, 1812544693, 1809002858, 1805443995, 1801868138, 1798275322,
1794665580, 1791038945, 1787395453, 1783735137, 1780058032, 1776364172, 1772653592, 1768926328, 1765182414,
1761421885, 1757644777, 1753851125, 1750040965, 1746214334, 1742371266, 1738511799, 1734635968, 1730743810,
1726835361, 1722910659, 1718969740, 1715012642, 1711039401, 1707050055, 1703044642, 1699023199, 1694985764,
1690932376, 1686863071, 1682777890, 1678676869, 1674560048, 1670427466, 1666279160, 1662115171, 1657935538,
1653740300, 1649529495, 1645303165, 1641061349, 1636804086, 1632531417, 1628243383, 1623940022, 1619621376,
1615287486, 1610938392, 1606574136, 1602194757, 1597800299, 1593390801, 1588966305, 1584526854, 1580072488,
1575603250, 1571119182, 1566620326, 1562106725, 1557578420, 1553035455, 1548477872, 1543905714, 1539319024,
1534717846, 1530102222, 1525472196, 1520827812, 1516169114, 1511496144, 1506808948, 1502107569, 1497392052,
1492662441, 1487918780, 1483161115, 1478389489, 1473603948, 1468804537, 1463991301, 1459164286, 1454323536,
1449469098, 1444601016, 1439719338, 1434824108, 1429915373, 1424993180, 1420057573, 1415108601, 1410146309,
1405170744, 1400181953, 1395179984, 1390164882, 1385136695, 1380095471, 1375041257, 1369974101, 1364894050,
1359801152, 1354695455, 1349577007, 1344445856, 1339302051, 1334145640, 1328976672, 1323795194, 1318601257,
1313394908, 1308176197, 1302945174, 1297701886, 1292446384, 1287178717, 1281898934, 1276607086, 1271303222,
1265987391, 1260659645, 1255320033, 1249968606, 1244605413, 1239230506, 1233843934, 1228445749, 1223036002,
1217614743, 1212182023, 1206737894, 1201282406, 1195815612, 1190337562, 1184848308, 1179347901, 1173836395,
1168313840, 1162780288, 1157235791, 1151680403, 1146114174, 1140537157, 1134949406, 1129350972, 1123741907,
1118122266, 1112492101, 1106851464, 1101200410, 1095538990, 1089867259, 1084185270, 1078493075, 1072790730,
1067078287, 1061355800, 1055623324, 1049880911, 1044128617, 1038366495, 1032594599, 1026812985, 1021021705,
1015220815, 1009410370, 1003590423, 997761031, 991922247, 986074127, 980216725, 974350098, 968474299,
962589385, 956695410, 950792431, 944880502, 938959680, 933030020, 927091578, 921144410, 915188572,
909224119, 903251109, 897269597, 891279639, 885281293, 879274614, 873259658, 867236484, 861205146,
855165703, 849118210, 843062725, 836999305, 830928007, 824848887, 818762004, 812667415, 806565176,
800455346, 794337981, 788213140, 782080880, 775941259, 769794334, 763640163, 757478805, 751310317,
745134758, 738952185, 732762657, 726566232, 720362968, 714152923, 707936157, 701712728, 695482693,
689246113, 683003045, 676753548, 670497682, 664235504, 657967075, 651692452, 645411696, 639124865,
632832018, 626533214, 620228513, 613917975, 607601658, 601279622, 594951927, 588618631, 582279796,
575935480, 569585742, 563230644, 556870244, 550504603, 544133781, 537757836, 531376830, 524990823,
518599874, 512204044, 505803393, 499397981, 492987869, 486573116, 480153784, 473729932, 467301621,
460868912, 454431865, 447990540, 441544999, 435095302, 428641510, 422183683, 415721883, 409256169,
402786604, 396313247, 389836160, 383355404, 376871039, 370383127, 363891729, 357396906, 350898719,
344397229, 337892498, 331384586, 324873555, 318359466, 311842381, 305322360, 298799466, 292273759,
285745301, 279214154, 272680379, 266144037, 259605190, 253063900, 246520227, 239974235, 233425983,
226875535, 220322951, 213768293, 207211623, 200653003, 194092494, 187530158, 180966058, 174400254,
167832808, 161263783, 154693239, 148121240, 141547847, 134973121, 128397125, 121819920, 115241569,
108662133, 102081674, 95500255, 88917936, 82334781, 75750851, 69166207, 62580913, 55995030,
49408619, 42821744, 36234465, 29646846, 23058947, 16470831, 9882561, 3294197};

49
ext/hal/nxp/mcux/drivers/lpc/fsl_powerquad_data.h Normal file
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@ -0,0 +1,49 @@
/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_POWERQUAD_DATA_H_
#define _FSL_POWERQUAD_DATA_H_
#include <stdint.h>
/*******************************************************************************
* Definitions
******************************************************************************/
extern int32_t dct16_twiddle[32];
extern int32_t dct32_twiddle[64];
extern int32_t dct64_twiddle[128];
extern int32_t dct128_twiddle[256];
extern int32_t dct256_twiddle[512];
extern int32_t dct512_twiddle[1024];
extern int32_t idct16_twiddle[32];
extern int32_t idct32_twiddle[64];
extern int32_t idct64_twiddle[128];
extern int32_t idct128_twiddle[256];
extern int32_t idct256_twiddle[512];
extern int32_t idct512_twiddle[1024];
extern int32_t dct16_cosFactor[32];
extern int32_t dct32_cosFactor[64];
extern int32_t dct64_cosFactor[128];
extern int32_t dct128_cosFactor[256];
extern int32_t dct256_cosFactor[512];
extern int32_t dct512_cosFactor[1024];
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _FSL_POWERQUAD_DATA_H_ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_powerquad.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad_filter"
#endif
/*******************************************************************************
* Code
******************************************************************************/
void PQ_VectorBiqaudDf2F32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_biquad0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readAdd0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8BiquadDf2F32();
PQ_EndVector();
}
}
void PQ_VectorBiqaudDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_biquad0_fx(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8BiquadDf2Fixed32();
PQ_EndVector();
}
}
void PQ_VectorBiqaudDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_biquad0_fx(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8BiquadDf2Fixed16();
PQ_EndVector();
}
}
void PQ_VectorBiqaudCascadeDf2F32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
PQ_Biquad1F32(&pSrc[0], &pDst[0]);
for (int i = 1; i < remainderBy8; i++)
{
_pq_biquad0(*(int32_t *)&pSrc[i - 1]);
_pq_biquad1(*(int32_t *)&pSrc[i]);
*(int32_t *)&pDst[i - 1] = _pq_readAdd0();
*(int32_t *)&pDst[i] = _pq_readAdd1();
}
PQ_BiquadF32(&pSrc[remainderBy8 - 1], &pDst[remainderBy8 - 1]);
}
if (length)
{
PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length);
PQ_Vector8BiqaudDf2CascadeF32();
PQ_EndVector();
}
}
void PQ_VectorBiqaudCascadeDf2Fixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
_pq_biquad1_fx(pSrc[0]);
pDst[0] = _pq_readAdd1_fx();
for (int i = 1; i < remainderBy8; i++)
{
_pq_biquad0_fx(pSrc[i - 1]);
_pq_biquad1_fx(pSrc[i]);
pDst[i - 1] = _pq_readAdd0_fx();
pDst[i] = _pq_readAdd1_fx();
}
_pq_biquad0_fx(pSrc[remainderBy8 - 1]);
pDst[remainderBy8 - 1] = _pq_readAdd0_fx();
}
if (length)
{
PQ_StartVector(&pSrc[remainderBy8], &pDst[remainderBy8], length);
PQ_Vector8BiqaudDf2CascadeFixed32();
PQ_EndVector();
}
}
void PQ_VectorBiqaudCascadeDf2Fixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
_pq_biquad1_fx(pSrc[0]);
pDst[0] = _pq_readAdd1_fx();
for (int i = 1; i < remainderBy8; i++)
{
_pq_biquad0_fx(pSrc[i - 1]);
_pq_biquad1_fx(pSrc[i]);
pDst[i - 1] = _pq_readAdd0_fx();
pDst[i] = _pq_readAdd1_fx();
}
_pq_biquad0_fx(pSrc[remainderBy8 - 1]);
pDst[remainderBy8 - 1] = _pq_readAdd0_fx();
}
if (length)
{
PQ_StartVectorFixed16(&pSrc[remainderBy8], &pDst[remainderBy8], length);
PQ_Vector8BiqaudDf2CascadeFixed16();
PQ_EndVector();
}
}
void PQ_BiquadBackUpInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state)
{
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (0 == biquad_num)
{
state->param = *(volatile pq_biquad_param_t *)&base->GPREG[0];
state->compreg = base->COMPREG[1];
}
else
{
state->param = *(volatile pq_biquad_param_t *)&base->GPREG[8];
state->compreg = base->COMPREG[3];
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
}
void PQ_BiquadRestoreInternalState(POWERQUAD_Type *base, int32_t biquad_num, pq_biquad_state_t *state)
{
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (0 == biquad_num)
{
*(volatile pq_biquad_param_t *)&base->GPREG[0] = state->param;
base->COMPREG[1] = state->compreg;
}
else
{
*(volatile pq_biquad_param_t *)&base->GPREG[8] = state->param;
base->COMPREG[3] = state->compreg;
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
}
void PQ_FIR(
POWERQUAD_Type *base, void *pAData, int32_t ALength, void *pBData, int32_t BLength, void *pResult, uint32_t opType)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->INABASE = (uint32_t)pAData;
base->INBBASE = (uint32_t)pBData;
base->LENGTH = ((uint32_t)BLength << 16U) + (uint32_t)ALength;
base->OUTBASE = (uint32_t)pResult;
base->CONTROL = (CP_FIR << 4U) | opType;
}
void PQ_FIRIncrement(POWERQUAD_Type *base, int32_t ALength, int32_t BLength, int32_t xOffset)
{
base->MISC = xOffset;
base->LENGTH = ((uint32_t)BLength << 16) + (uint32_t)ALength;
base->CONTROL = (CP_FIR << 4) | PQ_FIR_INCREMENTAL;
}
void PQ_BiquadCascadeDf2Init(pq_biquad_cascade_df2_instance *S, uint8_t numStages, pq_biquad_state_t *pState)
{
S->numStages = numStages;
S->pState = pState;
}
void PQ_BiquadCascadeDf2F32(const pq_biquad_cascade_df2_instance *S, float *pSrc, float *pDst, uint32_t blockSize)
{
uint32_t stage = S->numStages;
pq_biquad_state_t *states = S->pState;
if (pDst != pSrc)
{
memcpy(pDst, pSrc, 4 * blockSize);
}
if (stage % 2 != 0)
{
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
PQ_VectorBiqaudDf2F32(pSrc, pDst, blockSize);
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
stage--;
}
do
{
PQ_BiquadRestoreInternalState(POWERQUAD, 1, states);
states++;
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
PQ_VectorBiqaudCascadeDf2F32(pDst, pDst, blockSize);
states--;
PQ_BiquadBackUpInternalState(POWERQUAD, 1, states);
states++;
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
stage -= 2U;
} while (stage > 0U);
}
void PQ_BiquadCascadeDf2Fixed32(const pq_biquad_cascade_df2_instance *S,
int32_t *pSrc,
int32_t *pDst,
uint32_t blockSize)
{
uint32_t stage = S->numStages;
pq_biquad_state_t *states = S->pState;
if (pDst != pSrc)
{
memcpy(pDst, pSrc, 4 * blockSize);
}
if (stage % 2 != 0)
{
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
PQ_VectorBiqaudDf2Fixed32(pSrc, pDst, blockSize);
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
stage--;
}
do
{
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
states++;
PQ_BiquadRestoreInternalState(POWERQUAD, 1, states);
PQ_VectorBiqaudCascadeDf2Fixed32(pDst, pDst, blockSize);
states--;
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
PQ_BiquadBackUpInternalState(POWERQUAD, 1, states);
states++;
stage -= 2U;
} while (stage > 0U);
}
void PQ_BiquadCascadeDf2Fixed16(const pq_biquad_cascade_df2_instance *S,
int16_t *pSrc,
int16_t *pDst,
uint32_t blockSize)
{
uint32_t stage = S->numStages;
pq_biquad_state_t *states = S->pState;
if (pDst != pSrc)
{
memcpy(pDst, pSrc, 2 * blockSize);
}
if (stage % 2 != 0)
{
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
PQ_VectorBiqaudDf2Fixed16(pSrc, pDst, blockSize);
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
stage--;
}
do
{
PQ_BiquadRestoreInternalState(POWERQUAD, 0, states);
states++;
PQ_BiquadRestoreInternalState(POWERQUAD, 1, states);
PQ_VectorBiqaudCascadeDf2Fixed16(pDst, pDst, blockSize);
states--;
PQ_BiquadBackUpInternalState(POWERQUAD, 0, states);
states++;
PQ_BiquadBackUpInternalState(POWERQUAD, 1, states);
states++;
stage -= 2U;
} while (stage > 0U);
}

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_powerquad.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad_math"
#endif
/*******************************************************************************
* Code
******************************************************************************/
void PQ_VectorLnF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_ln0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readAdd0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_LN, 1, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorInvF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_inv0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readMult0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_INV, 0, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorSqrtF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sqrt0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readMult0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_SQRT, 0, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorInvSqrtF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_invsqrt0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readMult0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_INVSQRT, 0, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorEtoxF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etox0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readMult0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_ETOX, 0, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorEtonxF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etonx0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readMult0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_ETONX, 0, PQ_TRANS);
PQ_EndVector();
}
}
void PQ_VectorSinF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sin0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readAdd0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_SIN, 1, PQ_TRIG);
PQ_EndVector();
}
}
void PQ_VectorCosF32(float *pSrc, float *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_cos0(*(int32_t *)pSrc++);
*(int32_t *)pDst++ = _pq_readAdd0();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8F32(PQ_COS, 1, PQ_TRIG);
PQ_EndVector();
}
}
void PQ_VectorLnFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_ln_fx0(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_LN, 1, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorInvFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_inv_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_INV, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sqrt_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_SQRT, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorInvSqrtFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_invsqrt_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_INVSQRT, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorEtoxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etox_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_ETOX, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorEtonxFixed32(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etonx_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_ETONX, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorSinQ31(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
uint32_t cppre;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
const int32_t magic = 0x30c90fdb;
float valFloat;
#endif
cppre = POWERQUAD->CPPRE;
POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31);
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
}
}
while (length > 0)
{
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
length -= 8;
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
#else
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sin_fx0(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_SIN, 1, PQ_TRIG_FIXED);
PQ_EndVector();
}
#endif
POWERQUAD->CPPRE = cppre;
}
void PQ_VectorCosQ31(int32_t *pSrc, int32_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
uint32_t cppre;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
const int32_t magic = 0x30c90fdb;
float valFloat;
#endif
cppre = POWERQUAD->CPPRE;
POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31);
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
}
}
while (length > 0)
{
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
valFloat = *(const float *)(&magic) * (float)(*pSrc++);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx());
length -= 8;
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
#else
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_cos_fx0(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVector(pSrc, pDst, length);
PQ_Vector8Fixed32(PQ_COS, 1, PQ_TRIG_FIXED);
PQ_EndVector();
}
#endif
POWERQUAD->CPPRE = cppre;
}
void PQ_VectorLnFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_ln_fx0(*pSrc++);
*pDst++ = _pq_readAdd0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_LN, 1, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorInvFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_inv_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_INV, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sqrt_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_SQRT, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorInvSqrtFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_invsqrt_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_INVSQRT, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorEtoxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etox_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_ETOX, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorEtonxFixed16(int16_t *pSrc, int16_t *pDst, int32_t length)
{
int32_t remainderBy8 = length % 8;
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_etonx_fx0(*pSrc++);
*pDst++ = _pq_readMult0_fx();
}
}
if (length)
{
PQ_StartVectorFixed16(pSrc, pDst, length);
PQ_Vector8Fixed16(PQ_ETONX, 0, PQ_TRANS_FIXED);
PQ_EndVector();
}
}
void PQ_VectorSinQ15(int16_t *pSrc, int16_t *pDst, int32_t length)
{
uint32_t cppre;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
const int32_t magic = 0x30c90fdb;
float valFloat;
#endif
cppre = POWERQUAD->CPPRE;
POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31);
int32_t remainderBy8 = length % 8;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
}
}
while (length > 0)
{
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_sin0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
length -= 8;
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
#else
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_sin_fx0((uint32_t)(*pSrc++) << 16);
*pDst++ = (_pq_readAdd0_fx()) >> 16;
}
}
if (length)
{
PQ_StartVectorQ15(pSrc, pDst, length);
PQ_Vector8Q15(PQ_SIN, 1, PQ_TRIG_FIXED);
PQ_EndVector();
}
#endif
POWERQUAD->CPPRE = cppre;
}
void PQ_VectorCosQ15(int16_t *pSrc, int16_t *pDst, int32_t length)
{
uint32_t cppre;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
const int32_t magic = 0x30c90fdb;
float valFloat;
#endif
cppre = POWERQUAD->CPPRE;
POWERQUAD->CPPRE = POWERQUAD_CPPRE_CPPRE_OUT(31);
int32_t remainderBy8 = length % 8;
#if defined(FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA) && FSL_FEATURE_POWERQUAD_SIN_COS_FIX_ERRATA
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
}
}
while (length > 0)
{
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
valFloat = *(const float *)(&magic) * (float)((uint32_t)(*pSrc++) << 16);
_pq_cos0(*(int32_t *)(&valFloat));
_pq_readAdd0();
*pDst++ = (_pq_readAdd0_fx()) >> 16;
length -= 8;
}
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
#else
if (remainderBy8)
{
length -= remainderBy8;
while (remainderBy8--)
{
_pq_cos_fx0((uint32_t)(*pSrc++) << 16);
*pDst++ = (_pq_readAdd0_fx()) >> 16;
}
}
if (length)
{
PQ_StartVectorQ15(pSrc, pDst, length);
PQ_Vector8Q15(PQ_COS, 1, PQ_TRIG_FIXED);
PQ_EndVector();
}
#endif
POWERQUAD->CPPRE = cppre;
}
int32_t PQ_ArctanFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration)
{
base->CORDIC_X = x;
base->CORDIC_Y = y;
base->CORDIC_Z = 0;
base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTAN | CORDIC_ITER(iteration);
PQ_WaitDone(base);
return base->CORDIC_Z;
}
int32_t PQ_ArctanhFixed(POWERQUAD_Type *base, int32_t x, int32_t y, pq_cordic_iter_t iteration)
{
base->CORDIC_X = x;
base->CORDIC_Y = y;
base->CORDIC_Z = 0;
base->CONTROL = (CP_CORDIC << 4) | CORDIC_ARCTANH | CORDIC_ITER(iteration);
PQ_WaitDone(base);
return base->CORDIC_Z;
}

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_powerquad.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad_matrix"
#endif
/*******************************************************************************
* Code
******************************************************************************/
void PQ_MatrixAddition(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pAData;
base->INBBASE = (int32_t)pBData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_ADD;
}
void PQ_MatrixSubtraction(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pAData;
base->INBBASE = (int32_t)pBData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_SUB;
}
void PQ_MatrixMultiplication(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pAData;
base->INBBASE = (int32_t)pBData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_MULT;
}
void PQ_MatrixProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pAData;
base->INBBASE = (int32_t)pBData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_PROD;
}
void PQ_VectorDotProduct(POWERQUAD_Type *base, uint32_t length, void *pAData, void *pBData, void *pResult)
{
assert(pAData);
assert(pBData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pAData;
base->INBBASE = (int32_t)pBData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_VEC_DOTP;
}
void PQ_MatrixInversion(POWERQUAD_Type *base, uint32_t length, void *pData, void *pTmpData, void *pResult)
{
assert(pData);
assert(pTmpData);
assert(pResult);
/* Workaround:
*
* Matrix inv depends on the coproc 1/x function, this puts coproc to right state.
*/
_pq_inv0(1.0);
base->INABASE = (uint32_t)pData;
base->TMPBASE = (uint32_t)pTmpData;
base->OUTBASE = (uint32_t)pResult;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_INV;
}
void PQ_MatrixTranspose(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_MTX << 4) | PQ_MTX_TRAN;
}
void PQ_MatrixScale(POWERQUAD_Type *base, uint32_t length, float misc, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
#if defined(__GNUC__)
#pragma GCC diagnostic push
#pragma GCC diagnostic ignored "-Wstrict-aliasing"
#endif
base->MISC = *(uint32_t *)&misc;
#if defined(__GNUC__)
#pragma GCC diagnostic pop
#endif
base->CONTROL = (CP_MTX << 4) | PQ_MTX_SCALE;
}

103
ext/hal/nxp/mcux/drivers/lpc/fsl_powerquad_transform.c Normal file
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_powerquad.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.powerquad_transform"
#endif
/*******************************************************************************
* Code
******************************************************************************/
void PQ_TransformCFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CFFT;
}
void PQ_TransformRFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
/* Set 0's for imaginary inputs as not be reading them in by the machine */
base->GPREG[1] = 0;
base->GPREG[3] = 0;
base->GPREG[5] = 0;
base->GPREG[7] = 0;
base->GPREG[9] = 0;
base->GPREG[11] = 0;
base->GPREG[13] = 0;
base->GPREG[15] = 0;
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RFFT;
}
void PQ_TransformIFFT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IFFT;
}
void PQ_TransformCDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_CDCT;
}
void PQ_TransformRDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->GPREG[1] = 0;
base->GPREG[3] = 0;
base->GPREG[5] = 0;
base->GPREG[7] = 0;
base->GPREG[9] = 0;
base->GPREG[11] = 0;
base->GPREG[13] = 0;
base->GPREG[15] = 0;
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_RDCT;
}
void PQ_TransformIDCT(POWERQUAD_Type *base, uint32_t length, void *pData, void *pResult)
{
assert(pData);
assert(pResult);
base->OUTBASE = (int32_t)pResult;
base->INABASE = (int32_t)pData;
base->LENGTH = length;
base->CONTROL = (CP_FFT << 4) | PQ_TRANS_IDCT;
}

454
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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_prince.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.prince"
#endif
/*******************************************************************************
* Variables
******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
/*!
* brief Generate new IV code.
*
* This function generates new IV code and stores it into the persistent memory.
* Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true!
*
* param region PRINCE region index.
* param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code.
* param store flag to allow storing the newly generated IV code into the persistent memory (FFR).
* param flash_context pointer to the flash driver context structure.
*
* return kStatus_Success upon success
* return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular
* PRINCE region is not present in the keystore (though new IV code has been provided)
*/
status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context)
{
status_t retVal = kStatus_Fail;
uint8_t prince_iv_code[FLASH_FFR_IV_CODE_SIZE] = {0};
uint8_t tempBuffer[FLASH_FFR_MAX_PAGE_SIZE] = {0};
if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false)
{
return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */
}
/* Make sure PUF is started to allow key and IV code decryption and generation */
if (true != PUF_IsGetKeyAllowed(PUF))
{
return retVal;
}
/* Generate new IV code for the PRINCE region */
retVal = PUF_SetIntrinsicKey(PUF, (puf_key_index_register_t)(kPUF_KeyIndex_02 + (puf_key_index_register_t)region),
8, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE);
if ((kStatus_Success == retVal) && (true == store))
{
/* Store the new IV code for the PRINCE region into the respective FFRs. */
/* Create a new version of "Customer Field Programmable" (CFP) page. */
if (kStatus_FLASH_Success ==
FFR_GetCustomerInfieldData(flash_context, (uint8_t *)tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE))
{
/* Set the IV code in the page */
memcpy(&tempBuffer[offsetof(cfpa_cfg_info_t, ivCodePrinceRegion) + ((region * sizeof(cfpa_cfg_iv_code_t))) +
4],
&prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE);
uint32_t *p32 = (uint32_t *)tempBuffer;
uint32_t version = p32[1];
if (version == 0xFFFFFFFFu)
{
return kStatus_Fail;
}
version++;
p32[1] = version;
/* Program the page and enable firewall for "Customer field area" */
if (kStatus_FLASH_Success ==
FFR_InfieldPageWrite(flash_context, (uint8_t *)tempBuffer, FLASH_FFR_MAX_PAGE_SIZE))
{
retVal = kStatus_Success;
}
else
{
retVal = kStatus_Fail;
}
}
}
if (retVal == kStatus_Success)
{
/* Pass the new IV code */
memcpy(iv_code, &prince_iv_code[0], FLASH_FFR_IV_CODE_SIZE);
}
return retVal;
}
/*!
* brief Load IV code.
*
* This function enables IV code loading into the PRINCE bus encryption engine.
*
* param region PRINCE region index.
* param iv_code IV code pointer used for passing the IV code.
*
* return kStatus_Success upon success
* return kStatus_Fail otherwise
*/
status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code)
{
status_t retVal = kStatus_Fail;
uint32_t keyIndex = 0x0Fu & iv_code[1];
uint8_t prince_iv[8] = {0};
if (((SYSCON->PERIPHENCFG & SYSCON_PERIPHENCFG_PRINCEEN_MASK) ? true : false) == false)
{
return retVal; /* PRINCE peripheral not enabled, return kStatus_Fail. */
}
/* Make sure PUF is started to allow key and IV code decryption and generation */
if (true != PUF_IsGetKeyAllowed(PUF))
{
return retVal;
}
/* Check if region number matches the PUF index value */
if ((kPUF_KeyIndex_02 + (puf_key_index_register_t)region) == (puf_key_index_register_t)keyIndex)
{
/* Decrypt the IV */
if (kStatus_Success == PUF_GetKey(PUF, iv_code, FLASH_FFR_IV_CODE_SIZE, &prince_iv[0], 8))
{
/* Store the new IV for the PRINCE region into PRINCE registers. */
PRINCE_SetRegionIV(PRINCE, (prince_region_t)region, prince_iv);
retVal = kStatus_Success;
}
}
return retVal;
}
/*!
* brief Allow encryption/decryption for specified address range.
*
* This function sets the encryption/decryption for specified address range.
* Ensure about 800 bytes free space on the stack when calling this routine!
*
* param region PRINCE region index.
* param start_address start address of the area to be encrypted/decrypted.
* param length length of the area to be encrypted/decrypted.
* param flash_context pointer to the flash driver context structure.
*
* return kStatus_Success upon success
* return kStatus_Fail otherwise
*/
status_t PRINCE_SetEncryptForAddressRange(prince_region_t region,
uint32_t start_address,
uint32_t length,
flash_config_t *flash_context)
{
status_t retVal = kStatus_Fail;
uint32_t srEnableRegister = 0;
uint32_t alignedStartAddress;
uint32_t end_address = start_address + length;
uint32_t prince_region_base_address = 0;
uint8_t my_prince_iv_code[52] = {0};
uint8_t tempBuffer[512] = {0};
uint32_t prince_base_addr_ffr_word = 0;
/* Check the address range, regions overlaping. */
if ((start_address > 0xA0000) || ((start_address < 0x40000) && (end_address > 0x40000)) ||
((start_address < 0x80000) && (end_address > 0x80000)) ||
((start_address < 0xA0000) && (end_address > 0xA0000)))
{
return kStatus_Fail;
}
/* Generate new IV code for the PRINCE region and store the new IV into the respective FFRs */
retVal = PRINCE_GenNewIV((prince_region_t)region, &my_prince_iv_code[0], true, flash_context);
if (kStatus_Success != retVal)
{
return kStatus_Fail;
}
/* Store the new IV for the PRINCE region into PRINCE registers. */
retVal = PRINCE_LoadIV((prince_region_t)region, &my_prince_iv_code[0]);
if (kStatus_Success != retVal)
{
return kStatus_Fail;
}
alignedStartAddress = ALIGN_DOWN(start_address, FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024);
uint32_t subregion = alignedStartAddress / (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024);
if (subregion < (32))
{
/* PRINCE_Region0 */
prince_region_base_address = 0;
}
else if (subregion < (64))
{
/* PRINCE_Region1 */
subregion = subregion - 32;
prince_region_base_address = 0x40000;
}
else
{
/* PRINCE_Region2 */
subregion = subregion - 64;
prince_region_base_address = 0x80000;
}
srEnableRegister = (1 << subregion);
alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024);
while (alignedStartAddress < (start_address + length))
{
subregion++;
srEnableRegister |= (1 << subregion);
alignedStartAddress += (FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB * 1024);
}
/* Store BASE_ADDR into PRINCE register before storing the SR to avoid en/decryption triggering
from addresses being defined by current BASE_ADDR register content (could be 0 and the decryption
of actually executed code can be started causing the hardfault then). */
retVal = PRINCE_SetRegionBaseAddress(PRINCE, (prince_region_t)region, prince_region_base_address);
if (kStatus_Success != retVal)
{
return retVal;
}
/* Store SR into PRINCE register */
retVal = PRINCE_SetRegionSREnable(PRINCE, (prince_region_t)region, srEnableRegister);
if (kStatus_Success != retVal)
{
return retVal;
}
/* Store SR and BASE_ADDR into CMPA FFR */
if (kStatus_Success == FFR_GetCustomerData(flash_context, (uint8_t *)&tempBuffer, 0, FLASH_FFR_MAX_PAGE_SIZE))
{
/* Set the PRINCE_SR_X in the page */
memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeSr) + (region * sizeof(uint32_t))], &srEnableRegister,
sizeof(uint32_t));
/* Set the ADDRX_PRG in the page */
memcpy(&prince_base_addr_ffr_word, &tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], sizeof(uint32_t));
prince_base_addr_ffr_word &= ~((FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4));
prince_base_addr_ffr_word |=
(((prince_region_base_address >> 18) & FLASH_CMPA_PRINCE_BASE_ADDR_ADDR0_PRG_MASK) << (region * 4));
memcpy(&tempBuffer[offsetof(cmpa_cfg_info_t, princeBaseAddr)], &prince_base_addr_ffr_word, sizeof(uint32_t));
/* Program the CMPA page, set seal_part parameter to false (used during development to avoid sealing the part)
*/
retVal = FFR_CustFactoryPageWrite(flash_context, (uint8_t *)tempBuffer, false);
}
return retVal;
}
/*!
* brief Gets the PRINCE Sub-Region Enable register.
*
* This function gets PRINCE SR_ENABLE register.
*
* param base PRINCE peripheral address.
* param region PRINCE region index.
* param sr_enable Sub-Region Enable register pointer.
*
* return kStatus_Success upon success
* return kStatus_InvalidArgument
*/
status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable)
{
status_t status = kStatus_Success;
switch (region)
{
case kPRINCE_Region0:
*sr_enable = base->SR_ENABLE0;
break;
case kPRINCE_Region1:
*sr_enable = base->SR_ENABLE1;
break;
case kPRINCE_Region2:
*sr_enable = base->SR_ENABLE2;
break;
default:
status = kStatus_InvalidArgument;
break;
}
return status;
}
/*!
* brief Gets the PRINCE region base address register.
*
* This function gets PRINCE BASE_ADDR register.
*
* param base PRINCE peripheral address.
* param region PRINCE region index.
* param region_base_addr Region base address pointer.
*
* return kStatus_Success upon success
* return kStatus_InvalidArgument
*/
status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr)
{
status_t status = kStatus_Success;
switch (region)
{
case kPRINCE_Region0:
*region_base_addr = base->BASE_ADDR0;
break;
case kPRINCE_Region1:
*region_base_addr = base->BASE_ADDR1;
break;
case kPRINCE_Region2:
*region_base_addr = base->BASE_ADDR2;
break;
default:
status = kStatus_InvalidArgument;
break;
}
return status;
}
/*!
* @brief Sets the PRINCE region IV.
*
* This function sets specified AES IV for the given region.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param iv 64-bit AES IV in little-endian byte order.
*/
status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8])
{
status_t status = kStatus_Fail;
volatile uint32_t *IVMsb_reg = NULL;
volatile uint32_t *IVLsb_reg = NULL;
switch (region)
{
case kPRINCE_Region0:
IVLsb_reg = &base->IV_LSB0;
IVMsb_reg = &base->IV_MSB0;
break;
case kPRINCE_Region1:
IVLsb_reg = &base->IV_LSB1;
IVMsb_reg = &base->IV_MSB1;
break;
case kPRINCE_Region2:
IVLsb_reg = &base->IV_LSB2;
IVMsb_reg = &base->IV_MSB2;
break;
default:
status = kStatus_InvalidArgument;
break;
}
if (status != kStatus_InvalidArgument)
{
*IVLsb_reg = ((uint32_t *)(uintptr_t)iv)[0];
*IVMsb_reg = ((uint32_t *)(uintptr_t)iv)[1];
status = kStatus_Success;
}
return status;
}
/*!
* @brief Sets the PRINCE region base address.
*
* This function configures PRINCE region base address.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param region_base_addr Base Address for region.
*/
status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr)
{
status_t status = kStatus_Success;
switch (region)
{
case kPRINCE_Region0:
base->BASE_ADDR0 = region_base_addr;
break;
case kPRINCE_Region1:
base->BASE_ADDR1 = region_base_addr;
break;
case kPRINCE_Region2:
base->BASE_ADDR2 = region_base_addr;
break;
default:
status = kStatus_InvalidArgument;
break;
}
return status;
}
/*!
* @brief Sets the PRINCE Sub-Region Enable register.
*
* This function configures PRINCE SR_ENABLE register.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param sr_enable Sub-Region Enable register value.
*/
status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable)
{
status_t status = kStatus_Success;
switch (region)
{
case kPRINCE_Region0:
base->SR_ENABLE0 = sr_enable;
break;
case kPRINCE_Region1:
base->SR_ENABLE1 = sr_enable;
break;
case kPRINCE_Region2:
base->SR_ENABLE2 = sr_enable;
break;
default:
status = kStatus_InvalidArgument;
break;
}
return status;
}

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/*
* Copyright 2018 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_PRINCE_H_
#define _FSL_PRINCE_H_
#include "fsl_common.h"
#include "fsl_iap_ffr.h"
#include "fsl_puf.h"
/*!
* @addtogroup prince
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief PRINCE driver version 2.0.0.
*
* Current version: 2.0.0
*
* Change log:
* - Version 2.0.0
* - Initial version.
*/
#define FSL_PRINCE_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
#define FSL_PRINCE_DRIVER_SUBREGION_SIZE_IN_KB (8)
#if !defined(ALIGN_DOWN)
#define ALIGN_DOWN(x, a) ((x) & (uint32_t)(-((int32_t)(a))))
#endif
typedef enum _prince_region
{
kPRINCE_Region0 = 0U, /*!< PRINCE region 0 */
kPRINCE_Region1 = 1U, /*!< PRINCE region 1 */
kPRINCE_Region2 = 2U, /*!< PRINCE region 2 */
} prince_region_t;
typedef enum _prince_lock
{
kPRINCE_Region0Lock = 1U, /*!< PRINCE region 0 lock */
kPRINCE_Region1Lock = 2U, /*!< PRINCE region 1 lock */
kPRINCE_Region2Lock = 4U, /*!< PRINCE region 2 lock */
kPRINCE_MaskLock = 256U, /*!< PRINCE mask register lock */
} prince_lock_t;
/*******************************************************************************
* API
******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Enable data encryption.
*
* This function enables PRINCE on-the-fly data encryption.
*
* @param base PRINCE peripheral address.
*/
static inline void PRINCE_EncryptEnable(PRINCE_Type *base)
{
base->ENC_ENABLE = 1;
}
/*!
* @brief Disable data encryption.
*
* This function disables PRINCE on-the-fly data encryption.
*
* @param base PRINCE peripheral address.
*/
static inline void PRINCE_EncryptDisable(PRINCE_Type *base)
{
base->ENC_ENABLE = 0;
}
/*!
* @brief Sets PRINCE data mask.
*
* This function sets the PRINCE mask that is used to mask decrypted data.
*
* @param base PRINCE peripheral address.
* @param mask 64-bit data mask value.
*/
static inline void PRINCE_SetMask(PRINCE_Type *base, uint64_t mask)
{
base->MASK_LSB = mask & 0xffffffffu;
base->MASK_MSB = mask >> 32u;
}
/*!
* @brief Locks access for specified region registers or data mask register.
*
* This function sets lock on specified region registers or mask register.
*
* @param base PRINCE peripheral address.
* @param lock registers to lock. This is a logical OR of members of the
* enumeration ::prince_lock_t
*/
static inline void PRINCE_SetLock(PRINCE_Type *base, uint32_t lock)
{
base->LOCK = lock & 0x1ffu;
}
/*!
* @brief Generate new IV code.
*
* This function generates new IV code and stores it into the persistent memory.
* This function is implemented as a wrapper of the exported ROM bootloader API.
* Ensure about 800 bytes free space on the stack when calling this routine with the store parameter set to true!
*
* @param region PRINCE region index.
* @param iv_code IV code pointer used for storing the newly generated 52 bytes long IV code.
* @param store flag to allow storing the newly generated IV code into the persistent memory (FFR).
* param flash_context pointer to the flash driver context structure.
*
* @return kStatus_Success upon success
* @return kStatus_Fail otherwise, kStatus_Fail is also returned if the key code for the particular
* PRINCE region is not present in the keystore (though new IV code has been provided)
*/
status_t PRINCE_GenNewIV(prince_region_t region, uint8_t *iv_code, bool store, flash_config_t *flash_context);
/*!
* @brief Load IV code.
*
* This function enables IV code loading into the PRINCE bus encryption engine.
* This function is implemented as a wrapper of the exported ROM bootloader API.
*
* @param region PRINCE region index.
* @param iv_code IV code pointer used for passing the IV code.
*
* @return kStatus_Success upon success
* @return kStatus_Fail otherwise
*/
status_t PRINCE_LoadIV(prince_region_t region, uint8_t *iv_code);
/*!
* @brief Allow encryption/decryption for specified address range.
*
* This function sets the encryption/decryption for specified address range.
* This function is implemented as a wrapper of the exported ROM bootloader API.
* Ensure about 800 bytes free space on the stack when calling this routine!
*
* @param region PRINCE region index.
* @param start_address start address of the area to be encrypted/decrypted.
* @param length length of the area to be encrypted/decrypted.
* param flash_context pointer to the flash driver context structure.
*
* @return kStatus_Success upon success
* @return kStatus_Fail otherwise
*/
status_t PRINCE_SetEncryptForAddressRange(prince_region_t region,
uint32_t start_address,
uint32_t length,
flash_config_t *flash_context);
/*!
* @brief Gets the PRINCE Sub-Region Enable register.
*
* This function gets PRINCE SR_ENABLE register.
*
* @param base PRINCE peripheral address.
* @param region PRINCE region index.
* @param sr_enable Sub-Region Enable register pointer.
*
* @return kStatus_Success upon success
* @return kStatus_InvalidArgument
*/
status_t PRINCE_GetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t *sr_enable);
/*!
* @brief Gets the PRINCE region base address register.
*
* This function gets PRINCE BASE_ADDR register.
*
* @param base PRINCE peripheral address.
* @param region PRINCE region index.
* @param region_base_addr Region base address pointer.
*
* @return kStatus_Success upon success
* @return kStatus_InvalidArgument
*/
status_t PRINCE_GetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t *region_base_addr);
/*!
* @brief Sets the PRINCE region IV.
*
* This function sets specified AES IV for the given region.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param iv 64-bit AES IV in little-endian byte order.
*/
status_t PRINCE_SetRegionIV(PRINCE_Type *base, prince_region_t region, const uint8_t iv[8]);
/*!
* @brief Sets the PRINCE region base address.
*
* This function configures PRINCE region base address.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param region_base_addr Base Address for region.
*/
status_t PRINCE_SetRegionBaseAddress(PRINCE_Type *base, prince_region_t region, uint32_t region_base_addr);
/*!
* @brief Sets the PRINCE Sub-Region Enable register.
*
* This function configures PRINCE SR_ENABLE register.
*
* @param base PRINCE peripheral address.
* @param region Selection of the PRINCE region to be configured.
* @param sr_enable Sub-Region Enable register value.
*/
status_t PRINCE_SetRegionSREnable(PRINCE_Type *base, prince_region_t region, uint32_t sr_enable);
#if defined(__cplusplus)
}
#endif
/*!
*@}
*/
#endif /* _FSL_PRINCE_H_ */

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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_puf.h"
#include "fsl_clock.h"
#include "fsl_reset.h"
#include "fsl_common.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.puf"
#endif
static void puf_wait_usec(volatile uint32_t usec, uint32_t coreClockFrequencyMHz)
{
while (usec > 0)
{
usec--;
/* number of MHz is directly number of core clocks to wait 1 usec. */
/* the while loop below is actually 4 clocks so divide by 4 for ~1 usec */
register uint32_t ticksCount = coreClockFrequencyMHz / 4u + 1u;
while (ticksCount--)
{
}
}
}
static status_t puf_waitForInit(PUF_Type *base)
{
status_t status = kStatus_Fail;
/* wait until status register reads non-zero. All zero is not valid. It should be BUSY or OK or ERROR */
while (0 == base->STAT)
{
}
/* wait if busy */
while ((base->STAT & PUF_STAT_BUSY_MASK) != 0)
{
}
/* return status */
if (PUF_STAT_SUCCESS_MASK == (base->STAT & (PUF_STAT_SUCCESS_MASK | PUF_STAT_ERROR_MASK)))
{
status = kStatus_Success;
}
return status;
}
static void puf_powerOn(PUF_Type *base)
{
#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0)
/* RT6xxs */
base->PWRCTRL = 0x5u;
base->PWRCTRL = 0xDu;
base->PWRCTRL = 0x9u;
#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */
/* Niobe4 & Aruba FL */
base->PWRCTRL = PUF_PWRCTRL_RAMON_MASK;
while (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL))
{
}
#endif /* FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */
}
static status_t puf_powerCycle(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz)
{
#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0)
/* RT6xxs */
uint32_t coreClockFrequencyMHz = coreClockFrequencyHz / 1000000u;
/* exit ASPS mode */
/* write PWRCTRL=0x38. wait time > 1 us */
base->PWRCTRL = 0x38u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=1. */
puf_wait_usec(1, coreClockFrequencyMHz);
/* write PWRCTRL=0x8. wait time > 1 us */
base->PWRCTRL = 0x08u; /* SLEEP=1. PSWSMALL*=0. PSWLARGE*=0 */
puf_wait_usec(1, coreClockFrequencyMHz);
base->PWRCTRL = 0xCu;
base->PWRCTRL = 0xDu;
base->PWRCTRL = 0x9u;
/* Generate INITN low pulse */
base->PWRCTRL = 0xDu;
base->PWRCTRL = 0x5u;
base->PWRCTRL = 0x1u;
#else
/* Niobe4 & Aruba FL */
base->PWRCTRL = 0x0u;
while (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL)
{
}
#endif
/* Wait enough time to discharge fully */
puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u);
/* Reset PUF and reenable power to PUF SRAM */
RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn);
puf_powerOn(base);
return kStatus_Success;
}
/*!
* brief Initialize PUF
*
* This function enables power to PUF block and waits until the block initializes.
*
* param base PUF peripheral base address
* param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge
* param coreClockFrequencyHz core clock frequency in Hz
* return Status of the init operation
*/
status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz)
{
status_t status = kStatus_Fail;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Puf);
#endif
/* Reset PUF */
RESET_PeripheralReset(kPUF_RST_SHIFT_RSTn);
/* Enable power to PUF SRAM */
puf_powerOn(base);
/* Wait for peripheral to become ready */
status = puf_waitForInit(base);
/* In case of error or enroll & start not allowed, do power-cycle */
if ((status != kStatus_Success) || ((PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK) !=
(base->ALLOW & (PUF_ALLOW_ALLOWENROLL_MASK | PUF_ALLOW_ALLOWSTART_MASK))))
{
puf_powerCycle(base, dischargeTimeMsec, coreClockFrequencyHz);
status = puf_waitForInit(base);
}
return status;
}
/*!
* brief Denitialize PUF
*
* This function disables power to PUF SRAM and peripheral clock.
*
* param base PUF peripheral base address
*/
void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz)
{
#if defined(FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL) && (FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL > 0)
/* RT6xxs */
base->PWRCTRL = 0xDu; /* disable RAM CK */
/* enter ASPS mode */
base->PWRCTRL = 0xCu; /* SLEEP = 1 */
base->PWRCTRL = 0x8u; /* enable RAM CK */
base->PWRCTRL = 0xF8u; /* SLEEP=1, PSW*=1 */
#else /* !FSL_FEATURE_PUF_PWR_HAS_MANUAL_SLEEP_CONTROL */
/* Niobe4 & Aruba FL */
base->PWRCTRL = 0x00u;
#endif
/* Wait enough time to discharge fully */
puf_wait_usec(dischargeTimeMsec * 1000u, coreClockFrequencyHz / 1000000u);
RESET_SetPeripheralReset(kPUF_RST_SHIFT_RSTn);
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_Puf);
#endif
}
/*!
* brief Enroll PUF
*
* This function derives a digital fingerprint, generates the corresponding Activation Code (AC)
* and returns it to be stored in an NVM or a file. This step needs to be
* performed only once for each device. This function may be permanently disallowed by a fuse.
*
* param base PUF peripheral base address
* param[out] activationCode Word aligned address of the resulting activation code.
* param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes.
* return Status of enroll operation.
*/
status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize)
{
status_t status = kStatus_Fail;
uint32_t *activationCodeAligned = NULL;
register uint32_t temp32 = 0;
/* check that activation code buffer size is at least 1192 bytes */
if (activationCodeSize < PUF_ACTIVATION_CODE_SIZE)
{
return kStatus_InvalidArgument;
}
/* only work with aligned activationCode */
if (0x3u & (uintptr_t)activationCode)
{
return kStatus_InvalidArgument;
}
activationCodeAligned = (uint32_t *)(uintptr_t)activationCode;
/* check if ENROLL is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWENROLL_MASK))
{
return kStatus_Fail;
}
/* begin */
base->CTRL = PUF_CTRL_ENROLL_MASK;
/* check status */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* read out AC */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT))
{
temp32 = base->CODEOUTPUT;
if (activationCodeSize >= sizeof(uint32_t))
{
*activationCodeAligned = temp32;
activationCodeAligned++;
activationCodeSize -= sizeof(uint32_t);
}
}
}
if ((base->STAT & PUF_STAT_SUCCESS_MASK) && (activationCodeSize == 0))
{
status = kStatus_Success;
}
return status;
}
/*!
* brief Start PUF
*
* The Activation Code generated during the Enroll operation is used to
* reconstruct the digital fingerprint. This needs to be done after every power-up
* and reset.
*
* param base PUF peripheral base address
* param activationCode Word aligned address of the input activation code.
* param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes.
* return Status of start operation.
*/
status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize)
{
status_t status = kStatus_Fail;
const uint32_t *activationCodeAligned = NULL;
register uint32_t temp32 = 0;
/* check that activation code size is at least 1192 bytes */
if (activationCodeSize < 1192)
{
return kStatus_InvalidArgument;
}
/* only work with aligned activationCode */
if (0x3u & (uintptr_t)activationCode)
{
return kStatus_InvalidArgument;
}
activationCodeAligned = (const uint32_t *)(uintptr_t)activationCode;
/* check if START is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSTART_MASK))
{
return kStatus_Fail;
}
/* begin */
base->CTRL = PUF_CTRL_START_MASK;
/* check status */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* while busy send AC */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT))
{
if (activationCodeSize >= sizeof(uint32_t))
{
temp32 = *activationCodeAligned;
activationCodeAligned++;
activationCodeSize -= sizeof(uint32_t);
}
base->CODEINPUT = temp32;
}
}
/* get status */
if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))
{
status = kStatus_Success;
}
return status;
}
/*!
* brief Set intrinsic key
*
* The digital fingerprint generated during the Enroll/Start
* operations is used to generate a Key Code (KC) that defines a unique intrinsic
* key. This KC is returned to be stored in an NVM or a file. This operation
* needs to be done only once for each intrinsic key.
* Each time a Set Intrinsic Key operation is executed a new unique key is
* generated.
*
* param base PUF peripheral base address
* param keyIndex PUF key index register
* param keySize Size of the intrinsic key to generate in bytes.
* param[out] keyCode Word aligned address of the resulting key code.
* param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* return Status of set intrinsic key operation.
*/
status_t PUF_SetIntrinsicKey(
PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize)
{
status_t status = kStatus_Fail;
uint32_t *keyCodeAligned = NULL;
register uint32_t temp32 = 0;
/* check if SET KEY is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK))
{
return kStatus_Fail;
}
/* only work with aligned keyCode */
if (0x3u & (uintptr_t)keyCode)
{
return kStatus_InvalidArgument;
}
/* Check that keySize is in the correct range and that it is multiple of 8 */
if ((keySize < kPUF_KeySizeMin) || (keySize > kPUF_KeySizeMax) || (keySize & 0x7))
{
return kStatus_InvalidArgument;
}
/* check that keyCodeSize is correct for given keySize */
if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize))
{
return kStatus_InvalidArgument;
}
if ((uint32_t)keyIndex > kPUF_KeyIndexMax)
{
return kStatus_InvalidArgument;
}
keyCodeAligned = (uint32_t *)(uintptr_t)keyCode;
/* program the key size and index */
base->KEYSIZE = keySize >> 3;
base->KEYINDEX = (uint32_t)keyIndex;
/* begin */
base->CTRL = PUF_CTRL_GENERATEKEY_MASK;
/* wait till command is accepted */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* while busy read KC */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT))
{
temp32 = base->CODEOUTPUT;
if (keyCodeSize >= sizeof(uint32_t))
{
*keyCodeAligned = temp32;
keyCodeAligned++;
keyCodeSize -= sizeof(uint32_t);
}
}
}
/* get status */
if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))
{
status = kStatus_Success;
}
return status;
}
/*!
* brief Set user key
*
* The digital fingerprint generated during the Enroll/Start
* operations and a user key (UK) provided as input are used to
* generate a Key Code (KC). This KC is sent returned to be stored
* in an NVM or a file. This operation needs to be done only once for each user key.
*
* param base PUF peripheral base address
* param keyIndex PUF key index register
* param userKey Word aligned address of input user key.
* param userKeySize Size of the input user key in bytes.
* param[out] keyCode Word aligned address of the resulting key code.
* param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize).
* return Status of set user key operation.
*/
status_t PUF_SetUserKey(PUF_Type *base,
puf_key_index_register_t keyIndex,
const uint8_t *userKey,
size_t userKeySize,
uint8_t *keyCode,
size_t keyCodeSize)
{
status_t status = kStatus_Fail;
uint32_t *keyCodeAligned = NULL;
const uint32_t *userKeyAligned = NULL;
register uint32_t temp32 = 0;
/* check if SET KEY is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWSETKEY_MASK))
{
return kStatus_Fail;
}
/* only work with aligned keyCode */
if (0x3u & (uintptr_t)keyCode)
{
return kStatus_InvalidArgument;
}
/* Check that userKeySize is in the correct range and that it is multiple of 8 */
if ((userKeySize < kPUF_KeySizeMin) || (userKeySize > kPUF_KeySizeMax) || (userKeySize & 0x7))
{
return kStatus_InvalidArgument;
}
/* check that keyCodeSize is correct for given userKeySize */
if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize))
{
return kStatus_InvalidArgument;
}
if ((uint32_t)keyIndex > kPUF_KeyIndexMax)
{
return kStatus_InvalidArgument;
}
keyCodeAligned = (uint32_t *)(uintptr_t)keyCode;
userKeyAligned = (const uint32_t *)(uintptr_t)userKey;
/* program the key size and index */
base->KEYSIZE = userKeySize >> 3; /* convert to 64-bit blocks */
base->KEYINDEX = (uint32_t)keyIndex;
/* begin */
base->CTRL = PUF_CTRL_SETKEY_MASK;
/* wait till command is accepted */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* while busy write UK and read KC */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_KEYINREQ_MASK & base->STAT))
{
if (userKeySize >= sizeof(uint32_t))
{
temp32 = *userKeyAligned;
userKeyAligned++;
userKeySize -= sizeof(uint32_t);
}
base->KEYINPUT = temp32;
}
if (0 != (PUF_STAT_CODEOUTAVAIL_MASK & base->STAT))
{
temp32 = base->CODEOUTPUT;
if (keyCodeSize >= sizeof(uint32_t))
{
*keyCodeAligned = temp32;
keyCodeAligned++;
keyCodeSize -= sizeof(uint32_t);
}
}
}
/* get status */
if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))
{
status = kStatus_Success;
}
return status;
}
static status_t puf_getHwKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize)
{
status_t status = kStatus_Fail;
uint32_t *keyCodeAligned = NULL;
register uint32_t temp32 = 0;
keyCodeAligned = (uint32_t *)(uintptr_t)keyCode;
/* begin */
base->CTRL = PUF_CTRL_GETKEY_MASK;
/* wait till command is accepted */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* while busy send KC, key is reconstructed to HW bus */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT))
{
if (keyCodeSize >= sizeof(uint32_t))
{
temp32 = *keyCodeAligned;
keyCodeAligned++;
keyCodeSize -= sizeof(uint32_t);
}
base->CODEINPUT = temp32;
}
}
/* get status */
if (0 != (base->STAT & PUF_STAT_SUCCESS_MASK))
{
status = kStatus_Success;
}
return status;
}
/*!
* brief Reconstruct hw bus key from a key code
*
* The digital fingerprint generated during the Start operation and the KC
* generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This
* operation needs to be done every time a key is needed.
* This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00.
* Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory.
*
* param base PUF peripheral base address
* param keyCode Word aligned address of the input key code.
* param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots.
* param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly
* secure.
* return Status of get key operation.
*/
status_t PUF_GetHwKey(
PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask)
{
status_t status = kStatus_Fail;
uint32_t keyIndex;
/* check if GET KEY is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK))
{
return kStatus_Fail;
}
/* only work with aligned keyCode */
if (0x3u & (uintptr_t)keyCode)
{
return kStatus_Fail;
}
/* check that keyCodeSize is at least PUF_MIN_KEY_CODE_SIZE */
if (keyCodeSize < PUF_MIN_KEY_CODE_SIZE)
{
return kStatus_InvalidArgument;
}
keyIndex = 0x0Fu & keyCode[1];
/* check the Key Code header byte 1. index must be zero for the hw key. */
if (kPUF_KeyIndex_00 != (puf_key_index_register_t)keyIndex)
{
return kStatus_Fail;
}
#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0)
volatile uint32_t *keyMask_reg = NULL;
uint32_t regVal = (2 << (2 * keySlot));
switch (keySlot)
{
case kPUF_KeySlot0:
keyMask_reg = &base->KEYMASK[0];
break;
case kPUF_KeySlot1:
keyMask_reg = &base->KEYMASK[1];
break;
#if (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2)
case kPUF_KeySlot2:
keyMask_reg = &base->KEYMASK[2];
break;
case kPUF_KeySlot3:
keyMask_reg = &base->KEYMASK[3];
break;
#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS > 2 */
default:
status = kStatus_InvalidArgument;
break;
}
#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */
if (status != kStatus_InvalidArgument)
{
#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 0)
base->KEYRESET = regVal;
base->KEYENABLE = regVal;
*keyMask_reg = keyMask;
#endif /* FSL_FEATURE_PUF_HAS_KEYSLOTS */
status = puf_getHwKey(base, keyCode, keyCodeSize);
#if defined(FSL_FEATURE_PUF_HAS_SHIFT_STATUS) && (FSL_FEATURE_PUF_HAS_SHIFT_STATUS > 0)
size_t keyWords = 0;
if (status == kStatus_Success)
{
/* if the corresponding shift count does not match, return fail anyway */
keyWords = ((((size_t)keyCode[3]) * 2) - 1u) << (keySlot << 2);
if (keyWords != ((0x0Fu << (keySlot << 2)) & base->SHIFT_STATUS))
{
status = kStatus_Fail;
}
}
#endif /* FSL_FEATURE_PUF_HAS_SHIFT_STATUS */
}
return status;
}
/*!
* brief Checks if Get Key operation is allowed.
*
* This function returns true if get key operation is allowed.
*
* param base PUF peripheral base address
* return true if get key operation is allowed
*/
bool PUF_IsGetKeyAllowed(PUF_Type *base)
{
if (0 == (PUF_PWRCTRL_RAMSTAT_MASK & base->PWRCTRL))
{
return false;
}
/* check if GET KEY is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK))
{
return false;
}
return true;
}
/*!
* brief Reconstruct key from a key code
*
* The digital fingerprint generated during the Start operation and the KC
* generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This
* operation needs to be done every time a key is needed.
* This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15.
*
* param base PUF peripheral base address
* param keyCode Word aligned address of the input key code.
* param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* param[out] key Word aligned address of output key.
* param keySize Size of the output key in bytes.
* return Status of get key operation.
*/
status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize)
{
status_t status = kStatus_Fail;
uint32_t *keyCodeAligned = NULL;
uint32_t *keyAligned = NULL;
uint32_t keyIndex;
register uint32_t temp32 = 0;
/* check if GET KEY is allowed */
if (0x0u == (base->ALLOW & PUF_ALLOW_ALLOWGETKEY_MASK))
{
return kStatus_Fail;
}
/* only work with aligned keyCode */
if (0x3u & (uintptr_t)keyCode)
{
return kStatus_Fail;
}
/* only work with aligned key */
if (0x3u & (uintptr_t)key)
{
return kStatus_Fail;
}
/* check that keyCodeSize is correct for given keySize */
if (keyCodeSize < PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize))
{
return kStatus_InvalidArgument;
}
keyIndex = 0x0Fu & keyCode[1];
/* check the Key Code header byte 1. index must be non-zero for the register key. */
if (kPUF_KeyIndex_00 == (puf_key_index_register_t)keyIndex)
{
return kStatus_Fail;
}
keyCodeAligned = (uint32_t *)(uintptr_t)keyCode;
keyAligned = (uint32_t *)(uintptr_t)key;
/* begin */
base->CTRL = PUF_CTRL_GETKEY_MASK;
/* wait till command is accepted */
while (0 == (base->STAT & (PUF_STAT_BUSY_MASK | PUF_STAT_ERROR_MASK)))
{
}
/* while busy send KC, read key */
while (0 != (base->STAT & PUF_STAT_BUSY_MASK))
{
if (0 != (PUF_STAT_CODEINREQ_MASK & base->STAT))
{
temp32 = 0;
if (keyCodeSize >= sizeof(uint32_t))
{
temp32 = *keyCodeAligned;
keyCodeAligned++;
keyCodeSize -= sizeof(uint32_t);
}
base->CODEINPUT = temp32;
}
if (0 != (PUF_STAT_KEYOUTAVAIL_MASK & base->STAT))
{
keyIndex = base->KEYOUTINDEX;
temp32 = base->KEYOUTPUT;
if (keySize >= sizeof(uint32_t))
{
*keyAligned = temp32;
keyAligned++;
keySize -= sizeof(uint32_t);
}
}
}
/* get status */
if ((keyIndex) && (0 != (base->STAT & PUF_STAT_SUCCESS_MASK)))
{
status = kStatus_Success;
}
return status;
}
/*!
* brief Zeroize PUF
*
* This function clears all PUF internal logic and puts the PUF to error state.
*
* param base PUF peripheral base address
* return Status of the zeroize operation.
*/
status_t PUF_Zeroize(PUF_Type *base)
{
status_t status = kStatus_Fail;
/* zeroize command is always allowed */
base->CTRL = PUF_CTRL_ZEROIZE_MASK;
/* check that command is accepted */
if ((0 != (base->STAT & PUF_STAT_ERROR_MASK)) && (0 == base->ALLOW))
{
status = kStatus_Success;
}
return status;
}

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/*
* Copyright 2018 NXP
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _PUF_H_
#define _PUF_H_
#include <stddef.h>
#include <stdint.h>
#include "fsl_common.h"
typedef enum _puf_key_index_register
{
kPUF_KeyIndex_00 = 0x00U,
kPUF_KeyIndex_01 = 0x01U,
kPUF_KeyIndex_02 = 0x02U,
kPUF_KeyIndex_03 = 0x03U,
kPUF_KeyIndex_04 = 0x04U,
kPUF_KeyIndex_05 = 0x05U,
kPUF_KeyIndex_06 = 0x06U,
kPUF_KeyIndex_07 = 0x07U,
kPUF_KeyIndex_08 = 0x08U,
kPUF_KeyIndex_09 = 0x09U,
kPUF_KeyIndex_10 = 0x0AU,
kPUF_KeyIndex_11 = 0x0BU,
kPUF_KeyIndex_12 = 0x0CU,
kPUF_KeyIndex_13 = 0x0DU,
kPUF_KeyIndex_14 = 0x0EU,
kPUF_KeyIndex_15 = 0x0FU,
} puf_key_index_register_t;
typedef enum _puf_min_max
{
kPUF_KeySizeMin = 8u,
kPUF_KeySizeMax = 512u,
kPUF_KeyIndexMax = kPUF_KeyIndex_15,
} puf_min_max_t;
typedef enum _puf_key_slot
{
kPUF_KeySlot0 = 0U, /*!< PUF key slot 0 */
kPUF_KeySlot1 = 1U, /*!< PUF key slot 1 */
#if defined(FSL_FEATURE_PUF_HAS_KEYSLOTS) && (FSL_FEATURE_PUF_HAS_KEYSLOTS > 2)
kPUF_KeySlot2 = 2U, /*!< PUF key slot 2 */
kPUF_KeySlot3 = 3U, /*!< PUF key slot 3 */
#endif
} puf_key_slot_t;
/*! @brief Get Key Code size in bytes from key size in bytes at compile time. */
#define PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(x) ((160u + ((((x << 3) + 255u) >> 8) << 8)) >> 3)
#define PUF_MIN_KEY_CODE_SIZE PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(8)
#define PUF_ACTIVATION_CODE_SIZE 1192
/*******************************************************************************
* API
*******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif /* __cplusplus */
/*!
* @brief Initialize PUF
*
* This function enables power to PUF block and waits until the block initializes.
*
* @param base PUF peripheral base address
* @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge
* @param coreClockFrequencyHz core clock frequency in Hz
* @return Status of the init operation
*/
status_t PUF_Init(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz);
/*!
* @brief Denitialize PUF
*
* This function disables power to PUF SRAM and peripheral clock.
*
* @param base PUF peripheral base address
* @param dischargeTimeMsec time in ms to wait for PUF SRAM to fully discharge
* @param coreClockFrequencyHz core clock frequency in Hz
*/
void PUF_Deinit(PUF_Type *base, uint32_t dischargeTimeMsec, uint32_t coreClockFrequencyHz);
/*!
* @brief Enroll PUF
*
* This function derives a digital fingerprint, generates the corresponding Activation Code (AC)
* and returns it to be stored in an NVM or a file. This step needs to be
* performed only once for each device. This function may be permanently disallowed by a fuse.
*
* @param base PUF peripheral base address
* @param[out] activationCode Word aligned address of the resulting activation code.
* @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes.
* @return Status of enroll operation.
*/
status_t PUF_Enroll(PUF_Type *base, uint8_t *activationCode, size_t activationCodeSize);
/*!
* @brief Start PUF
*
* The Activation Code generated during the Enroll operation is used to
* reconstruct the digital fingerprint. This needs to be done after every power-up
* and reset.
*
* @param base PUF peripheral base address
* @param activationCode Word aligned address of the input activation code.
* @param activationCodeSize Size of the activationCode buffer in bytes. Shall be 1192 bytes.
* @return Status of start operation.
*/
status_t PUF_Start(PUF_Type *base, const uint8_t *activationCode, size_t activationCodeSize);
/*!
* @brief Set intrinsic key
*
* The digital fingerprint generated during the Enroll/Start
* operations is used to generate a Key Code (KC) that defines a unique intrinsic
* key. This KC is returned to be stored in an NVM or a file. This operation
* needs to be done only once for each intrinsic key.
* Each time a Set Intrinsic Key operation is executed a new unique key is
* generated.
*
* @param base PUF peripheral base address
* @param keyIndex PUF key index register
* @param keySize Size of the intrinsic key to generate in bytes.
* @param[out] keyCode Word aligned address of the resulting key code.
* @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* @return Status of set intrinsic key operation.
*/
status_t PUF_SetIntrinsicKey(
PUF_Type *base, puf_key_index_register_t keyIndex, size_t keySize, uint8_t *keyCode, size_t keyCodeSize);
/*!
* @brief Set user key
*
* The digital fingerprint generated during the Enroll/Start
* operations and a user key (UK) provided as input are used to
* generate a Key Code (KC). This KC is sent returned to be stored
* in an NVM or a file. This operation needs to be done only once for each user key.
*
* @param base PUF peripheral base address
* @param keyIndex PUF key index register
* @param userKey Word aligned address of input user key.
* @param userKeySize Size of the input user key in bytes.
* @param[out] keyCode Word aligned address of the resulting key code.
* @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(userKeySize).
* @return Status of set user key operation.
*/
status_t PUF_SetUserKey(PUF_Type *base,
puf_key_index_register_t keyIndex,
const uint8_t *userKey,
size_t userKeySize,
uint8_t *keyCode,
size_t keyCodeSize);
/*!
* @brief Reconstruct key from a key code
*
* The digital fingerprint generated during the Start operation and the KC
* generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This
* operation needs to be done every time a key is needed.
* This function accepts only Key Codes created for PUF index registers kPUF_KeyIndex_01 to kPUF_KeyIndex_15.
*
* @param base PUF peripheral base address
* @param keyCode Word aligned address of the input key code.
* @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* @param[out] key Word aligned address of output key.
* @param keySize Size of the output key in bytes.
* @return Status of get key operation.
*/
status_t PUF_GetKey(PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, uint8_t *key, size_t keySize);
/*!
* @brief Reconstruct hw bus key from a key code
*
* The digital fingerprint generated during the Start operation and the KC
* generated during a Set Key operation (Set intrinsic key or Set user key) are used to retrieve a stored key. This
* operation needs to be done every time a key is needed.
* This function accepts only Key Codes created for PUF index register kPUF_KeyIndex_00.
* Such a key is output directly to a dedicated hardware bus. The reconstructed key is not exposed to system memory.
*
* @param base PUF peripheral base address
* @param keyCode Word aligned address of the input key code.
* @param keyCodeSize Size of the keyCode buffer in bytes. Shall be PUF_GET_KEY_CODE_SIZE_FOR_KEY_SIZE(keySize).
* @param keySlot key slot to output on hw bus. Parameter is ignored on devices with less than two key slots.
* @param keyMask key masking value. Shall be random for each POR/reset. Value does not have to be cryptographicaly
* secure.
* @return Status of get key operation.
*/
status_t PUF_GetHwKey(
PUF_Type *base, const uint8_t *keyCode, size_t keyCodeSize, puf_key_slot_t keySlot, uint32_t keyMask);
/*!
* @brief Zeroize PUF
*
* This function clears all PUF internal logic and puts the PUF to error state.
*
* @param base PUF peripheral base address
* @return Status of the zeroize operation.
*/
status_t PUF_Zeroize(PUF_Type *base);
/*!
* @brief Checks if Get Key operation is allowed.
*
* This function returns true if get key operation is allowed.
*
* @param base PUF peripheral base address
* @return true if get key operation is allowed
*/
bool PUF_IsGetKeyAllowed(PUF_Type *base);
static inline void PUF_BlockSetKey(PUF_Type *base)
{
base->CFG |= PUF_CFG_BLOCKKEYOUTPUT_MASK; /* block set key */
}
static inline void PUF_BlockEnroll(PUF_Type *base)
{
base->CFG |= PUF_CFG_BLOCKENROLL_SETKEY_MASK; /* block enroll */
}
#if defined(__cplusplus)
}
#endif /* __cplusplus */
#endif /* _PUF_H_ */

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_rng.h"
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.rng_1"
#endif
/*******************************************************************************
* Definitions
*******************************************************************************/
/*******************************************************************************
* Prototypes
*******************************************************************************/
/*******************************************************************************
* Code
******************************************************************************/
void RNG_Init(RNG_Type *base)
{
/* Clear ring oscilator disable bit*/
PMC->PDRUNCFGCLR0 = PMC_PDRUNCFG0_PDEN_RNG_MASK;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_EnableClock(kCLOCK_Rng);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/* Clear POWERDOWN bit to enable RNG */
base->POWERDOWN &= ~RNG_POWERDOWN_POWERDOWN_MASK;
}
void RNG_Deinit(RNG_Type *base)
{
/* Set ring oscilator disable bit*/
PMC->PDRUNCFGSET0 = PMC_PDRUNCFG0_PDEN_RNG_MASK;
/* Set POWERDOWN bit to disable RNG */
base->POWERDOWN |= RNG_POWERDOWN_POWERDOWN_MASK;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
CLOCK_DisableClock(kCLOCK_Rng);
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
}
status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t dataSize)
{
status_t result = kStatus_Fail;
uint32_t random32;
uint32_t randomSize;
uint8_t *pRandom;
uint8_t *pData = (uint8_t *)data;
uint32_t i;
/* Check input parameters.*/
if (!(base && data && dataSize))
{
result = kStatus_InvalidArgument;
}
else
{
/* Check that ring oscilator is enabled */
if (!(PMC->PDRUNCFG0 & PMC_PDRUNCFG0_PDEN_RNG_MASK))
{
do
{
/* Read Entropy.*/
random32 = base->RANDOM_NUMBER;
pRandom = (uint8_t *)&random32;
if (dataSize < sizeof(random32))
{
randomSize = dataSize;
}
else
{
randomSize = sizeof(random32);
}
for (i = 0; i < randomSize; i++)
{
*pData++ = *pRandom++;
}
dataSize -= randomSize;
} while (dataSize > 0);
result = kStatus_Success;
}
}
return result;
}

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/*
* Copyright 2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_RNG_DRIVER_H_
#define _FSL_RNG_DRIVER_H_
#include "fsl_common.h"
/*!
* @addtogroup rng
* @{
*/
/*******************************************************************************
* Definitions
*******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief RNG driver version. Version 2.0.0.
*
* Current version: 2.0.0
*
* Change log:
* - Version 2.0.0
* - Initial version
*/
#define FSL_RNG_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
/*@}*/
/*******************************************************************************
* API
*******************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief Initializes the RNG.
*
* This function initializes the RNG.
* When called, the RNG module and ring oscillator is enabled.
*
* @param base RNG base address
* @param userConfig Pointer to the initialization configuration structure.
* @return If successful, returns the kStatus_RNG_Success. Otherwise, it returns an error.
*/
void RNG_Init(RNG_Type *base);
/*!
* @brief Shuts down the RNG.
*
* This function shuts down the RNG.
*
* @param base RNG base address.
*/
void RNG_Deinit(RNG_Type *base);
/*!
* @brief Gets random data.
*
* This function gets random data from the RNG.
*
* @param base RNG base address.
* @param data Pointer address used to store random data.
* @param dataSize Size of the buffer pointed by the data parameter.
* @return random data
*/
status_t RNG_GetRandomData(RNG_Type *base, void *data, size_t data_size);
/*!
* @brief Returns random 32-bit number.
*
* This function gets random number from the RNG.
*
* @param base RNG base address.
* @return random number
*/
static inline uint32_t RNG_GetRandomWord(RNG_Type *base)
{
return base->RANDOM_NUMBER;
}
#if defined(__cplusplus)
}
#endif
/*! @}*/
#endif /*_FSL_RNG_H_*/

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/*
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SDIF_H_
#define _FSL_SDIF_H_
#include "fsl_common.h"
/*!
* @addtogroup sdif
* @{
*/
/**********************************
* Definitions.
*****************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Driver version 2.0.10. */
#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 10U))
/*@}*/
/*! @brief SDIOCLKCTRL setting
* Below clock delay setting should depend on specific platform, so
* it can be redefined when timing mismatch issue occur.
* Such as: response error/CRC error and so on
*/
/*! @brief clock range value which need to add delay to avoid timing issue */
#ifndef SDIF_CLOCK_RANGE_NEED_DELAY
#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U)
#endif
/*
* Fixed delay configuration
* min hold time:2ns
* min setup time: 6ns
* delay = (x+1)*250ps
*/
/*! @brief High speed mode clk_sample fixed delay*/
#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY
#define SDIF_HIGHSPEED_SAMPLE_DELAY (0U)
#endif
/*! @brief High speed mode clk_drv fixed delay */
#ifndef SDIF_HIGHSPEED_DRV_DELAY
#define SDIF_HIGHSPEED_DRV_DELAY (0x1FU)
#endif
/*
* Phase shift delay configuration
* 0 degree: no delay
* 90 degree: 0.25/source clk value
* 180 degree: 0.50/source clk value
* 270 degree: 0.75/source clk value
*/
/*! @brief High speed mode clk_sample phase shift */
#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT
#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U)
#endif
/*! @brief High speed mode clk_drv phase shift */
#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT
#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv phase delay */
#endif
/*! @brief SDIF internal DMA descriptor address and the data buffer address align */
#define SDIF_INTERNAL_DMA_ADDR_ALIGN (4U)
/*! @brief SDIF status */
enum _sdif_status
{
kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */
kStatus_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */
kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */
kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /*!< send command to card fail */
kStatus_SDIF_SendCmdErrorBufferFull =
MAKE_STATUS(kStatusGroup_SDIF, 4U), /*!< send command to card fail, due to command buffer full
user need to resend this command */
kStatus_SDIF_DMATransferFailWithFBE =
MAKE_STATUS(kStatusGroup_SDIF, 5U), /*!< DMA transfer data fail with fatal bus error ,
to do with this error :issue a hard reset/controller reset*/
kStatus_SDIF_DMATransferDescriptorUnavailable =
MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< DMA descriptor unavailable */
kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /*!< transfer data fail */
kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), /*!< response error */
kStatus_SDIF_DMAAddrNotAlign = MAKE_STATUS(kStatusGroup_SDIF, 8U), /*!< DMA address not align */
};
/*! @brief Host controller capabilities flag mask */
enum _sdif_capability_flag
{
kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */
kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */
kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */
kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */
kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */
kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */
};
/*! @brief define the reset type */
enum _sdif_reset_type
{
kSDIF_ResetController =
SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface
CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE
and READ_WAIT bits of control register,START_CMD bit of the
command register*/
kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/
kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */
kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/
kSDIF_ResetDMAInterface,
};
/*! @brief define the card bus width type */
typedef enum _sdif_bus_width
{
kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode
share one register bit */
kSDIF_Bus4BitWidth = 1U, /*!< 4bit mode mask */
kSDIF_Bus8BitWidth = 2U, /*!< support 8 bit mode */
} sdif_bus_width_t;
/*! @brief define the command flags */
enum _sdif_command_flags
{
kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/
kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */
kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/
kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,either read/write*/
kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */
kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */
kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */
kSDIF_WaitPreTransferComplete =
SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */
kSDIF_TransferStopAbort =
SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer
,this bit should set so that cmd/data state-machines of CIU can return
to idle correctly*/
kSDIF_SendInitialization =
SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initialization 80 clocks for SD card after power on */
kSDIF_CmdUpdateClockRegisterOnly =
SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */
kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */
kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */
kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */
kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */
kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU
terminates the boot operation*/
kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/
kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */
kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/
};
/*! @brief The command type */
enum _sdif_command_type
{
kCARD_CommandTypeNormal = 0U, /*!< Normal command */
kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */
kCARD_CommandTypeResume = 2U, /*!< Resume command */
kCARD_CommandTypeAbort = 3U, /*!< Abort command */
};
/*!
* @brief The command response type.
*
* Define the command response type from card to host controller.
*/
enum _sdif_response_type
{
kCARD_ResponseTypeNone = 0U, /*!< Response type: none */
kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */
kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */
kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */
kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */
kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */
kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */
kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */
kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */
kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */
};
/*! @brief define the interrupt mask flags */
enum _sdif_interrupt_mask
{
kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */
kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */
kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/
kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/
kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */
kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */
kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< response CRC error */
kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */
kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */
kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */
kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */
kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO under run or overrun error */
kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */
kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */
kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */
kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */
kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */
kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError |
kSDIF_ResponseTimeout |
kSDIF_HardwareLockError, /*!< command transfer status collection*/
kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest |
kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout |
kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError |
kSDIF_AutoCmdDone, /*!< data transfer status collection */
kSDIF_DataTransferError =
kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout,
kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */
};
/*! @brief define the internal DMA status flags */
enum _sdif_dma_status
{
kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */
kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA receive finished for one DMA descriptor */
kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */
kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */
kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */
kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */
kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/
kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError |
kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary |
kSDIF_AbnormalInterruptSummary,
};
/*! @brief define the internal DMA descriptor flag */
enum _sdif_dma_descriptor_flag
{
kSDIF_DisableCompleteInterrupt = 1, /*!< disable the complete interrupt flag for the ends
in the buffer pointed to by this descriptor*/
kSDIF_DMADescriptorDataBufferEnd = 2, /*!< indicate this descriptor contain the last data buffer of data */
kSDIF_DMADescriptorDataBufferStart = 3, /*!< indicate this descriptor contain the first data buffer
of data,if first buffer size is 0,next descriptor contain
the begin of the data*/
kSDIF_DMASecondAddrChained = 4, /*!< indicate that the second addr in the descriptor is the
next descriptor addr not the data buffer */
kSDIF_DMADescriptorEnd = 5, /*!< indicate that the descriptor list reached its final descriptor*/
kSDIF_DMADescriptorOwnByDMA = 31, /*!< indicate the descriptor is own by SD/MMC DMA */
};
/*! @brief define the internal DMA mode */
typedef enum _sdif_dma_mode
{
kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */
kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */
} sdif_dma_mode_t;
/*! @brief define the internal DMA descriptor */
typedef struct _sdif_dma_descriptor
{
uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */
uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */
const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */
const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */
} sdif_dma_descriptor_t;
/*! @brief Defines the internal DMA configure structure. */
typedef struct _sdif_dma_config
{
bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will
use only SINGLE, INCR4, INCR8 or INCR16 during start of
normal burst transfers. When reset, the AHB will use SINGLE
and INCR burst transfer operations */
sdif_dma_mode_t mode; /*!< define the DMA mode */
uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor
this field is special for dual DMA mode */
uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/
uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the
dma descriptor buffer length if it is bigger enough for your transfer */
} sdif_dma_config_t;
/*!
* @brief Card data descriptor
*/
typedef struct _sdif_data
{
bool streamTransfer; /*!< indicate this is a stream data transfer command */
bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */
bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */
size_t blockSize; /*!< Block size, take care when configure this parameter */
uint32_t blockCount; /*!< Block count */
uint32_t *rxData; /*!< data buffer to receive */
const uint32_t *txData; /*!< data buffer to transfer */
} sdif_data_t;
/*!
* @brief Card command descriptor
*
* Define card command-related attribute.
*/
typedef struct _sdif_command
{
uint32_t index; /*!< Command index */
uint32_t argument; /*!< Command argument */
uint32_t response[4U]; /*!< Response for this command */
uint32_t type; /*!< define the command type */
uint32_t responseType; /*!< Command response type */
uint32_t flags; /*!< Cmd flags */
uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when
receive the cmd response */
} sdif_command_t;
/*! @brief Transfer state */
typedef struct _sdif_transfer
{
sdif_data_t *data; /*!< Data to transfer */
sdif_command_t *command; /*!< Command to send */
} sdif_transfer_t;
/*! @brief Data structure to initialize the sdif */
typedef struct _sdif_config
{
uint8_t responseTimeout; /*!< command response timeout value */
uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in
card detect logic,typical value is 5-25ms */
uint32_t endianMode; /*!< define endian mode ,this field is not used in this
module actually, keep for compatible with middleware*/
uint32_t dataTimeout; /*!< data timeout value */
} sdif_config_t;
/*!
* @brief SDIF capability information.
* Defines a structure to get the capability information of SDIF.
*/
typedef struct _sdif_capability
{
uint32_t sdVersion; /*!< support SD card/sdio version */
uint32_t mmcVersion; /*!< support emmc card version */
uint32_t maxBlockLength; /*!< Maximum block length united as byte */
uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */
uint32_t flags; /*!< Capability flags to indicate the support information */
} sdif_capability_t;
/*! @brief sdif callback functions. */
typedef struct _sdif_transfer_callback
{
void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */
void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */
void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */
void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */
void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */
void (*TransferComplete)(SDIF_Type *base,
void *handle,
status_t status,
void *userData); /*!< Transfer complete callback */
} sdif_transfer_callback_t;
/*!
* @brief sdif handle
*
* Defines the structure to save the sdif state information and callback function. The detail interrupt status when
* send command or transfer data can be obtained from interruptFlags field by using mask defined in
* sdif_interrupt_flag_t;
* @note All the fields except interruptFlags and transferredWords must be allocated by the user.
*/
typedef struct _sdif_handle
{
/* Transfer parameter */
sdif_data_t *volatile data; /*!< Data to transfer */
sdif_command_t *volatile command; /*!< Command to send */
/* Transfer status */
volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */
volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/
volatile uint32_t transferredWords; /*!< Words transferred by polling way */
/* Callback functions */
sdif_transfer_callback_t callback; /*!< Callback function */
void *userData; /*!< Parameter for transfer complete callback */
} sdif_handle_t;
/*! @brief sdif transfer function. */
typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content);
/*! @brief sdif host descriptor */
typedef struct _sdif_host
{
SDIF_Type *base; /*!< sdif peripheral base address */
uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */
sdif_config_t config; /*!< sdif configuration */
sdif_transfer_function_t transfer; /*!< sdif transfer function */
sdif_capability_t capability; /*!< sdif capability information */
} sdif_host_t;
/*************************************************************************************************
* API
************************************************************************************************/
#if defined(__cplusplus)
extern "C" {
#endif
/*!
* @brief SDIF module initialization function.
*
* Configures the SDIF according to the user configuration.
* @param base SDIF peripheral base address.
* @param config SDIF configuration information.
*/
void SDIF_Init(SDIF_Type *base, sdif_config_t *config);
/*!
* @brief SDIF module deinit function.
* user should call this function follow with IP reset
* @param base SDIF peripheral base address.
*/
void SDIF_Deinit(SDIF_Type *base);
/*!
* @brief SDIF send initialize 80 clocks for SD card after initial
* @param base SDIF peripheral base address.
* @param timeout value
*/
bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout);
#if defined(FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD) && FSL_FEATURE_SDIF_ONE_INSTANCE_SUPPORT_TWO_CARD
/*!
* @brief SDIF module enable/disable card0 clock.
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK0_ENABLE_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK0_ENABLE_MASK;
}
}
/*!
* @brief SDIF module enable/disable card1 clock.
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableCard1Clock(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK1_ENABLE_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK1_ENABLE_MASK;
}
}
/*!
* @brief SDIF module enable/disable module disable the card clock
* to enter low power mode when card is idle,for SDIF cards, if
* interrupts must be detected, clock should not be stopped
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK0_LOW_POWER_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK0_LOW_POWER_MASK;
}
}
/*!
* @brief SDIF module enable/disable module disable the card clock
* to enter low power mode when card is idle,for SDIF cards, if
* interrupts must be detected, clock should not be stopped
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableCard1LowPowerMode(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK1_LOW_POWER_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK1_LOW_POWER_MASK;
}
}
/*!
* @brief enable/disable the card0 power.
* once turn power on, software should wait for regulator/switch
* ramp-up time before trying to initialize card.
* @param base SDIF peripheral base address.
* @param enable/disable flag.
*/
static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable)
{
if (enable)
{
base->PWREN |= SDIF_PWREN_POWER_ENABLE0_MASK;
}
else
{
base->PWREN &= ~SDIF_PWREN_POWER_ENABLE0_MASK;
}
}
/*!
* @brief enable/disable the card1 power.
* once turn power on, software should wait for regulator/switch
* ramp-up time before trying to initialize card.
* @param base SDIF peripheral base address.
* @param enable/disable flag.
*/
static inline void SDIF_EnableCard1Power(SDIF_Type *base, bool enable)
{
if (enable)
{
base->PWREN |= SDIF_PWREN_POWER_ENABLE1_MASK;
}
else
{
base->PWREN &= ~SDIF_PWREN_POWER_ENABLE1_MASK;
}
}
/*!
* @brief set card0 data bus width
* @param base SDIF peripheral base address.
* @param data bus width type
*/
void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type);
/*!
* @brief set card1 data bus width
* @param base SDIF peripheral base address.
* @param data bus width type
*/
void SDIF_SetCard1BusWidth(SDIF_Type *base, sdif_bus_width_t type);
/*!
* @brief SDIF module detect card0 insert status function.
* @param base SDIF peripheral base address.
* @param data3 indicate use data3 as card insert detect pin
* @retval 1 card is inserted
* 0 card is removed
*/
static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
{
if (data3)
{
return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U;
}
else
{
return (base->CDETECT & SDIF_CDETECT_CARD0_DETECT_MASK) == 0U ? 1U : 0U;
}
}
/*!
* @brief SDIF module detect card1 insert status function.
* @param base SDIF peripheral base address.
* @param data3 indicate use data3 as card insert detect pin
* @retval 1 card is inserted
* 0 card is removed
*/
static inline uint32_t SDIF_DetectCard1Insert(SDIF_Type *base, bool data3)
{
if (data3)
{
return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U;
}
else
{
return (base->CDETECT & SDIF_CDETECT_CARD1_DETECT_MASK) == 0U ? 1U : 0U;
}
}
#else
/*!
* @brief SDIF module enable/disable card clock.
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK;
}
}
/*!
* @brief SDIF module enable/disable module disable the card clock
* to enter low power mode when card is idle,for SDIF cards, if
* interrupts must be detected, clock should not be stopped
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK;
}
else
{
base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK;
}
}
/*!
* @brief enable/disable the card power.
* once turn power on, software should wait for regulator/switch
* ramp-up time before trying to initialize card.
* @param base SDIF peripheral base address.
* @param enable/disable flag.
*/
static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable)
{
if (enable)
{
base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK;
}
else
{
base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK;
}
}
/*!
* @brief set card data bus width
* @param base SDIF peripheral base address.
* @param data bus width type
*/
void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type);
/*!
* @brief SDIF module detect card insert status function.
* @param base SDIF peripheral base address.
* @param data3 indicate use data3 as card insert detect pin
* @retval 1 card is inserted
* 0 card is removed
*/
static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
{
if (data3)
{
return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U;
}
else
{
return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U;
}
}
#endif
/*!
* @brief Sets the card bus clock frequency.
*
* @param base SDIF peripheral base address.
* @param srcClock_Hz SDIF source clock frequency united in Hz.
* @param target_HZ card bus clock frequency united in Hz.
* @return The nearest frequency of busClock_Hz configured to SD bus.
*/
uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ);
/*!
* @brief reset the different block of the interface.
* @param base SDIF peripheral base address.
* @param mask indicate which block to reset.
* @param timeout value,set to wait the bit self clear
* @return reset result.
*/
bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout);
/*!
* @brief get the card write protect status
* @param base SDIF peripheral base address.
*/
static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base)
{
return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK;
}
/*!
* @brief toggle state on hardware reset PIN
* This is used which card has a reset PIN typically.
* @param base SDIF peripheral base address.
*/
static inline void SDIF_AssertHardwareReset(SDIF_Type *base)
{
base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK;
}
/*!
* @brief send command to the card
* @param base SDIF peripheral base address.
* @param command configuration collection
* @param timeout value
* @return command excute status
*/
status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout);
/*!
* @brief SDIF enable/disable global interrupt
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK;
}
else
{
base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK;
}
}
/*!
* @brief SDIF enable interrupt
* @param base SDIF peripheral base address.
* @param interrupt mask
*/
static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask)
{
base->INTMASK |= mask;
}
/*!
* @brief SDIF disable interrupt
* @param base SDIF peripheral base address.
* @param interrupt mask
*/
static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask)
{
base->INTMASK &= ~mask;
}
/*!
* @brief SDIF get interrupt status
* @param base SDIF peripheral base address.
*/
static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base)
{
return base->MINTSTS;
}
/*!
* @brief SDIF clear interrupt status
* @param base SDIF peripheral base address.
* @param status mask to clear
*/
static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask)
{
base->RINTSTS &= mask;
}
/*!
* @brief Creates the SDIF handle.
* register call back function for interrupt and enable the interrupt
* @param base SDIF peripheral base address.
* @param handle SDIF handle pointer.
* @param callback Structure pointer to contain all callback functions.
* @param userData Callback function parameter.
*/
void SDIF_TransferCreateHandle(SDIF_Type *base,
sdif_handle_t *handle,
sdif_transfer_callback_t *callback,
void *userData);
/*!
* @brief SDIF enable DMA interrupt
* @param base SDIF peripheral base address.
* @param interrupt mask to set
*/
static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask)
{
base->IDINTEN |= mask;
}
/*!
* @brief SDIF disable DMA interrupt
* @param base SDIF peripheral base address.
* @param interrupt mask to clear
*/
static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask)
{
base->IDINTEN &= ~mask;
}
/*!
* @brief SDIF get internal DMA status
* @param base SDIF peripheral base address.
* @return the internal DMA status register
*/
static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base)
{
return base->IDSTS;
}
/*!
* @brief SDIF clear internal DMA status
* @param base SDIF peripheral base address.
* @param status mask to clear
*/
static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask)
{
base->IDSTS &= mask;
}
/*!
* @brief SDIF internal DMA config function
* @param base SDIF peripheral base address.
* @param internal DMA configuration collection
* @param data buffer pointer
* @param data buffer size
*/
status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize);
/*!
* @brief SDIF internal DMA enable
* @param base SDIF peripheral base address.
* @param enable internal DMA enable or disable flag.
*/
static inline void SDIF_EnableInternalDMA(SDIF_Type *base, bool enable)
{
if (enable)
{
/* use internal DMA interface */
base->CTRL |= SDIF_CTRL_USE_INTERNAL_DMAC_MASK;
/* enable the internal SD/MMC DMA */
base->BMOD |= SDIF_BMOD_DE_MASK;
}
else
{
/* use internal DMA interface */
base->CTRL &= ~SDIF_CTRL_USE_INTERNAL_DMAC_MASK;
/* enable the internal SD/MMC DMA */
base->BMOD &= ~SDIF_BMOD_DE_MASK;
}
}
/*!
* @brief SDIF send read wait to SDIF card function
* @param base SDIF peripheral base address.
*/
static inline void SDIF_SendReadWait(SDIF_Type *base)
{
base->CTRL |= SDIF_CTRL_READ_WAIT_MASK;
}
/*!
* @brief SDIF abort the read data when SDIF card is in suspend state
* Once assert this bit,data state machine will be reset which is waiting for the
* next blocking data,used in SDIO card suspend sequence,should call after suspend
* cmd send
* @param base SDIF peripheral base address.
* @param timeout value to wait this bit self clear which indicate the data machine
* reset to idle
*/
bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout);
/*!
* @brief SDIF enable/disable CE-ATA card interrupt
* this bit should set together with the card register
* @param base SDIF peripheral base address.
* @param enable/disable flag
*/
static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable)
{
if (enable)
{
base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
}
else
{
base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK;
}
}
/*!
* @brief SDIF transfer function data/cmd in a non-blocking way
* this API should be use in interrupt mode, when use this API user
* must call SDIF_TransferCreateHandle first, all status check through
* interrupt
* @param base SDIF peripheral base address.
* @param sdif handle
* @param DMA config structure
* This parameter can be config as:
* 1. NULL
In this condition, polling transfer mode is selected
2. avaliable DMA config
In this condition, DMA transfer mode is selected
* @param sdif transfer configuration collection
*/
status_t SDIF_TransferNonBlocking(SDIF_Type *base,
sdif_handle_t *handle,
sdif_dma_config_t *dmaConfig,
sdif_transfer_t *transfer);
/*!
* @brief SDIF transfer function data/cmd in a blocking way
* @param base SDIF peripheral base address.
* @param DMA config structure
* 1. NULL
* In this condition, polling transfer mode is selected
* 2. avaliable DMA config
* In this condition, DMA transfer mode is selected
* @param sdif transfer configuration collection
*/
status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer);
/*!
* @brief SDIF release the DMA descriptor to DMA engine
* this function should be called when DMA descriptor unavailable status occurs
* @param base SDIF peripheral base address.
* @param sdif DMA config pointer
*/
status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig);
/*!
* @brief SDIF return the controller capability
* @param base SDIF peripheral base address.
* @param sdif capability pointer
*/
void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability);
/*!
* @brief SDIF return the controller status
* @param base SDIF peripheral base address.
*/
static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base)
{
return base->STATUS;
}
/*!
* @brief SDIF send command complete signal disable to CE-ATA card
* @param base SDIF peripheral base address.
* @param send auto stop flag
*/
static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop)
{
if (withAutoStop)
{
base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK;
}
else
{
base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK;
}
}
/*!
* @brief SDIF config the clock delay
* This function is used to config the cclk_in delay to
* sample and driver the data ,should meet the min setup
* time and hold time, and user need to config this parameter
* according to your board setting
* @param target freq work mode
* @param clock divider which is used to decide if use phase shift for delay
*/
void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider);
/* @} */
#if defined(__cplusplus)
}
#endif
/*! @} */
#endif /* _FSL_sdif_H_*/

9
ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.c
View file

@ -268,13 +268,12 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_tra
/* transmit */ /* transmit */
SPI_EnableTxDMA(base, true); SPI_EnableTxDMA(base, true);
if (xfer->configFlags & kSPI_FrameAssert)
{
PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p);
}
if (xfer->txData) if (xfer->txData)
{ {
if (xfer->configFlags & kSPI_FrameAssert)
{
PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p);
}
/* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma
* descriptor to send the last data. * descriptor to send the last data.
*/ */

4
ext/hal/nxp/mcux/drivers/lpc/fsl_spi_dma.h
View file

@ -24,8 +24,8 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief SPI DMA driver version 2.0.3. */ /*! @brief SPI DMA driver version 2.0.2. */
#define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 3)) #define FSL_SPI_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/ /*@}*/
typedef struct _spi_dma_handle spi_dma_handle_t; typedef struct _spi_dma_handle spi_dma_handle_t;

206
ext/hal/nxp/mcux/drivers/lpc/fsl_sysctl.c Normal file
View file

@ -0,0 +1,206 @@
/*
* Copyright (c) 2018, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include "fsl_sysctl.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/* Component ID definition, used by tools. */
#ifndef FSL_COMPONENT_ID
#define FSL_COMPONENT_ID "platform.drivers.sysctl"
#endif
/*******************************************************************************
* Prototypes
******************************************************************************/
/*!
* @brief Get the instance.
*
* @param base SYSCTL peripheral base address.
* @return Instance number.
*/
static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base);
/*!
* @brief Enable SYSCTL write protect
*
* @param base SYSCTL peripheral base address.
* @param regAddr register address
* @param value value to write.
*/
static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value);
/*******************************************************************************
* Variables
******************************************************************************/
/*! @brief SYSCTL base address array name */
static SYSCTL_Type *const s_sysctlBase[] = SYSCTL_BASE_PTRS;
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/*! @brief SYSCTL clock array name */
static const clock_ip_name_t s_sysctlClock[] = SYSCTL_CLOCKS;
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Code
******************************************************************************/
static void SYSCTL_UpdateRegister(SYSCTL_Type *base, volatile uint32_t *regAddr, uint32_t value)
{
base->UPDATELCKOUT &= ~SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK;
*regAddr = value;
base->UPDATELCKOUT |= SYSCTL_UPDATELCKOUT_UPDATELCKOUT_MASK;
}
static uint32_t SYSCTL_GetInstance(SYSCTL_Type *base)
{
uint8_t instance = 0;
while ((instance < ARRAY_SIZE(s_sysctlBase)) && (s_sysctlBase[instance] != base))
{
instance++;
}
assert(instance < ARRAY_SIZE(s_sysctlBase));
return instance;
}
/*!
* @brief SYSCTL initial
*
* @param base Base address of the SYSCTL peripheral.
*/
void SYSCTL_Init(SYSCTL_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Enable SYSCTL clock. */
CLOCK_EnableClock(s_sysctlClock[SYSCTL_GetInstance(base)]);
#endif
}
/*!
* @brief SYSCTL deinit
*
* @param base Base address of the SYSCTL peripheral.
*/
void SYSCTL_Deinit(SYSCTL_Type *base)
{
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
/* Disable SYSCTL clock. */
CLOCK_DisableClock(s_sysctlClock[SYSCTL_GetInstance(base)]);
#endif
}
/*!
* @brief SYSCTL share set configure for separate signal
*
* @param base Base address of the SYSCTL peripheral
* @param flexCommIndex index of flexcomm,reference _sysctl_share_src
* @param setIndex share set for sck, reference _sysctl_share_set_index
*
*/
void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set)
{
uint32_t tempReg = base->FCCTRLSEL[flexCommIndex];
tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK << signal);
tempReg |= (set + 1U) << signal;
SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg);
}
/*!
* @brief SYSCTL share set configure for flexcomm
*
* @param base Base address of the SYSCTL peripheral.
* @param flexCommIndex index of flexcomm, reference _sysctl_share_src
* @param sckSet share set for sck,reference _sysctl_share_set_index
* @param wsSet share set for ws, reference _sysctl_share_set_index
* @param dataInSet share set for data in, reference _sysctl_share_set_index
* @param dataOutSet share set for data out, reference _sysctl_share_set_index
*
*/
void SYSCTL_SetFlexcommShareSet(
SYSCTL_Type *base, uint32_t flexCommIndex, uint32_t sckSet, uint32_t wsSet, uint32_t dataInSet, uint32_t dataOutSet)
{
uint32_t tempReg = base->FCCTRLSEL[flexCommIndex];
tempReg &= ~(SYSCTL_FCCTRLSEL_SCKINSEL_MASK | SYSCTL_FCCTRLSEL_WSINSEL_MASK | SYSCTL_FCCTRLSEL_DATAINSEL_MASK |
SYSCTL_FCCTRLSEL_DATAOUTSEL_MASK);
tempReg |= SYSCTL_FCCTRLSEL_SCKINSEL(sckSet + 1U) | SYSCTL_FCCTRLSEL_WSINSEL(wsSet + 1U) |
SYSCTL_FCCTRLSEL_DATAINSEL(dataInSet + 1U) | SYSCTL_FCCTRLSEL_DATAOUTSEL(dataOutSet + 1U);
SYSCTL_UpdateRegister(base, &base->FCCTRLSEL[flexCommIndex], tempReg);
}
/*!
* @brief SYSCTL share set source configure
*
* @param base Base address of the SYSCTL peripheral
* @param setIndex index of share set, reference _sysctl_share_set_index
* @param sckShareSrc sck source for this share set,reference _sysctl_share_src
* @param wsShareSrc ws source for this share set,reference _sysctl_share_src
* @param dataInShareSrc data in source for this share set,reference _sysctl_share_src
* @param dataOutShareSrc data out source for this share set,reference _sysctl_dataout_mask
*
*/
void SYSCTL_SetShareSetSrc(SYSCTL_Type *base,
uint32_t setIndex,
uint32_t sckShareSrc,
uint32_t wsShareSrc,
uint32_t dataInShareSrc,
uint32_t dataOutMask)
{
uint32_t tempReg = base->SHAREDCTRLSET[setIndex];
/* WS,SCK,DATA IN */
tempReg &=
~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_MASK |
SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_MASK);
tempReg |= SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL(sckShareSrc) |
SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL(wsShareSrc) |
SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL(dataInShareSrc);
/* data out */
tempReg &=
~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK |
SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK | SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK |
SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK);
tempReg |= dataOutMask;
SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg);
}
/*!
* @brief SYSCTL sck source configure
*
* @param base Base address of the SYSCTL peripheral
* @param setIndex index of share set, reference _sysctl_share_set_index
* @param sckShareSrc sck source fro this share set,reference _sysctl_share_src
*
*/
void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base,
uint32_t setIndex,
sysctl_sharedctrlset_signal_t signal,
uint32_t shareSrc)
{
uint32_t tempReg = base->SHAREDCTRLSET[setIndex];
if (signal == kSYSCTL_SharedCtrlSignalDataOut)
{
tempReg |= 1 << (signal + shareSrc);
}
else
{
tempReg &= ~(SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_MASK << signal);
tempReg |= shareSrc << signal;
}
SYSCTL_UpdateRegister(base, &base->SHAREDCTRLSET[setIndex], tempReg);
}

186
ext/hal/nxp/mcux/drivers/lpc/fsl_sysctl.h Normal file
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@ -0,0 +1,186 @@
/*
* Copyright (c) 2018, NXP Semiconductors, Inc.
* All rights reserved.
*
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _FSL_SYSCTL_H_
#define _FSL_SYSCTL_H_
#include "fsl_common.h"
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @addtogroup sysctl
* @{
*/
/*! @file */
/*! @file fsl_sysctl.h */
/*******************************************************************************
* Definitions
******************************************************************************/
/*! @name Driver version */
/*@{*/
/*! @brief Group sysctl driver version for SDK */
#define FSL_SYSCTL_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1. */
/*@}*/
/*! @brief SYSCTL share set*/
enum _sysctl_share_set_index
{
kSYSCTL_ShareSet0 = 0, /*!< share set 0 */
kSYSCTL_ShareSet1 = 1, /*!< share set 1 */
};
/*! @brief SYSCTL flexcomm signal */
typedef enum _sysctl_fcctrlsel_signal
{
kSYSCTL_FlexcommSignalSCK = SYSCTL_FCCTRLSEL_SCKINSEL_SHIFT, /*!< SCK signal */
kSYSCTL_FlexcommSignalWS = SYSCTL_FCCTRLSEL_WSINSEL_SHIFT, /*!< WS signal */
kSYSCTL_FlexcommSignalDataIn = SYSCTL_FCCTRLSEL_DATAINSEL_SHIFT, /*!< Data in signal */
kSYSCTL_FlexcommSignalDataOut = SYSCTL_FCCTRLSEL_DATAOUTSEL_SHIFT, /*!< Data out signal */
} sysctl_fcctrlsel_signal_t;
/*! @brief SYSCTL flexcomm index*/
enum _sysctl_share_src
{
kSYSCTL_Flexcomm0 = 0, /*!< share set 0 */
kSYSCTL_Flexcomm1 = 1, /*!< share set 1 */
kSYSCTL_Flexcomm2 = 2, /*!< share set 2 */
kSYSCTL_Flexcomm4 = 4, /*!< share set 4 */
kSYSCTL_Flexcomm5 = 5, /*!< share set 5 */
kSYSCTL_Flexcomm6 = 6, /*!< share set 6 */
kSYSCTL_Flexcomm7 = 7, /*!< share set 7 */
};
/*! @brief SYSCTL shared data out mask */
enum _sysctl_dataout_mask
{
kSYSCTL_Flexcomm0DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_MASK, /*!< share set 0 */
kSYSCTL_Flexcomm1DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC1DATAOUTEN_MASK, /*!< share set 1 */
kSYSCTL_Flexcomm2DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_F20DATAOUTEN_MASK, /*!< share set 2 */
kSYSCTL_Flexcomm3DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC3DATAOUTEN_MASK, /*!< share set 3 */
kSYSCTL_Flexcomm4DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC4DATAOUTEN_MASK, /*!< share set 4 */
kSYSCTL_Flexcomm5DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC5DATAOUTEN_MASK, /*!< share set 5 */
kSYSCTL_Flexcomm6DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC6DATAOUTEN_MASK, /*!< share set 6 */
kSYSCTL_Flexcomm7DataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC7DATAOUTEN_MASK, /*!< share set 7 */
};
/*! @brief SYSCTL flexcomm signal */
typedef enum _sysctl_sharedctrlset_signal
{
kSYSCTL_SharedCtrlSignalSCK = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDSCKSEL_SHIFT, /*!< SCK signal */
kSYSCTL_SharedCtrlSignalWS = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDWSSEL_SHIFT, /*!< WS signal */
kSYSCTL_SharedCtrlSignalDataIn = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_SHAREDDATASEL_SHIFT, /*!< Data in signal */
kSYSCTL_SharedCtrlSignalDataOut = SYSCTL_SHARECTRLSET_SHAREDCTRLSET_FC0DATAOUTEN_SHIFT, /*!< Data out signal */
} sysctl_sharedctrlset_signal_t;
/*******************************************************************************
* API
******************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
/*!
* @name Initialization and deinitialization
* @{
*/
/*!
* @brief SYSCTL initial
*
* @param base Base address of the SYSCTL peripheral.
*/
void SYSCTL_Init(SYSCTL_Type *base);
/*!
* @brief SYSCTL deinit
*
* @param base Base address of the SYSCTL peripheral.
*/
void SYSCTL_Deinit(SYSCTL_Type *base);
/* @} */
/*!
* @name SYSCTL share signal configure
* @{
*/
/*!
* @brief SYSCTL share set configure for flexcomm
*
* @param base Base address of the SYSCTL peripheral.
* @param flexCommIndex index of flexcomm, reference _sysctl_share_src
* @param sckSet share set for sck,reference _sysctl_share_set_index
* @param wsSet share set for ws, reference _sysctl_share_set_index
* @param dataInSet share set for data in, reference _sysctl_share_set_index
* @param dataOutSet share set for data out, reference _sysctl_share_set_index
*
*/
void SYSCTL_SetFlexcommShareSet(SYSCTL_Type *base,
uint32_t flexCommIndex,
uint32_t sckSet,
uint32_t wsSet,
uint32_t dataInSet,
uint32_t dataOutSet);
/*!
* @brief SYSCTL share set configure for separate signal
*
* @param base Base address of the SYSCTL peripheral
* @param flexCommIndex index of flexcomm,reference _sysctl_share_src
* @param signal FCCTRLSEL signal shift
* @param setIndex share set for sck, reference _sysctl_share_set_index
*
*/
void SYSCTL_SetShareSet(SYSCTL_Type *base, uint32_t flexCommIndex, sysctl_fcctrlsel_signal_t signal, uint32_t set);
/*!
* @brief SYSCTL share set source configure
*
* @param base Base address of the SYSCTL peripheral
* @param setIndex index of share set, reference _sysctl_share_set_index
* @param sckShareSrc sck source fro this share set,reference _sysctl_share_src
* @param wsShareSrc ws source fro this share set,reference _sysctl_share_src
* @param dataInShareSrc data in source fro this share set,reference _sysctl_share_src
* @param dataOutShareSrc data out source fro this share set,reference _sysctl_share_src
*
*/
void SYSCTL_SetShareSetSrc(SYSCTL_Type *base,
uint32_t setIndex,
uint32_t sckShareSrc,
uint32_t wsShareSrc,
uint32_t dataInShareSrc,
uint32_t dataOutShareSrc);
/*!
* @brief SYSCTL sck source configure
*
* @param base Base address of the SYSCTL peripheral
* @param setIndex index of share set, reference _sysctl_share_set_index
* @param sckShareSrc sck source fro this share set,reference _sysctl_share_src
*
*/
void SYSCTL_SetShareSignalSrc(SYSCTL_Type *base,
uint32_t setIndex,
sysctl_sharedctrlset_signal_t signal,
uint32_t shareSrc);
/* @} */
#ifdef __cplusplus
}
#endif
/*@}*/
#endif /* _FSL_SYSCTL_H_ */

5
ext/hal/nxp/mcux/drivers/lpc/fsl_utick.c
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@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -114,8 +114,11 @@ void UTICK_Init(UTICK_Type *base)
RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]); RESET_PeripheralReset(s_utickResets[UTICK_GetInstance(base)]);
#endif #endif
#if !(defined(FSL_FEATURE_UTICK_HAS_NO_PDCFG) && FSL_FEATURE_UTICK_HAS_NO_PDCFG)
/* Power up Watchdog oscillator*/ /* Power up Watchdog oscillator*/
POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC); POWER_DisablePD(kPDRUNCFG_PD_WDT_OSC);
#endif
s_utickIsr = UTICK_HandleIRQ; s_utickIsr = UTICK_HandleIRQ;
} }

6
ext/hal/nxp/mcux/drivers/lpc/fsl_utick.h
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -22,8 +22,8 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief UTICK driver version 2.0.1. */ /*! @brief UTICK driver version 2.0.2. */
#define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) #define FSL_UTICK_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
/*@}*/ /*@}*/
/*! @brief UTICK timer operational mode. */ /*! @brief UTICK timer operational mode. */

12
ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.c
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -71,7 +71,7 @@ static uint32_t WWDT_GetInstance(WWDT_Type *base)
******************************************************************************/ ******************************************************************************/
/*! /*!
* brief Initializes WWDT configure sturcture. * brief Initializes WWDT configure structure.
* *
* This function initializes the WWDT configure structure to default value. The default * This function initializes the WWDT configure structure to default value. The default
* value are: * value are:
@ -101,8 +101,10 @@ void WWDT_GetDefaultConfig(wwdt_config_t *config)
config->enableWatchdogReset = false; config->enableWatchdogReset = false;
/* Disable the watchdog protection for updating the timeout value */ /* Disable the watchdog protection for updating the timeout value */
config->enableWatchdogProtect = false; config->enableWatchdogProtect = false;
#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK)
/* Do not lock the watchdog oscillator */ /* Do not lock the watchdog oscillator */
config->enableLockOscillator = false; config->enableLockOscillator = false;
#endif
/* Windowing is not in effect */ /* Windowing is not in effect */
config->windowValue = 0xFFFFFFU; config->windowValue = 0xFFFFFFU;
/* Set the timeout value to the max */ /* Set the timeout value to the max */
@ -152,9 +154,13 @@ void WWDT_Init(WWDT_Type *base, const wwdt_config_t *config)
#endif #endif
#endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */ #endif /* FSL_SDK_DISABLE_DRIVER_RESET_CONTROL */
#if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK)
value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) | value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset) |
WWDT_MOD_LOCK(config->enableLockOscillator); WWDT_MOD_LOCK(config->enableLockOscillator);
/* Set configruation */ #else
value = WWDT_MOD_WDEN(config->enableWwdt) | WWDT_MOD_WDRESET(config->enableWatchdogReset);
#endif
/* Set configuration */
base->TC = WWDT_TC_COUNT(config->timeoutValue); base->TC = WWDT_TC_COUNT(config->timeoutValue);
base->MOD |= value; base->MOD |= value;
base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue); base->WINDOW = WWDT_WINDOW_WINDOW(config->windowValue);

24
ext/hal/nxp/mcux/drivers/lpc/fsl_wwdt.h
View file

@ -1,6 +1,6 @@
/* /*
* Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP * Copyright 2016-2018 NXP
* All rights reserved. * All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
@ -23,8 +23,8 @@
/*! @name Driver version */ /*! @name Driver version */
/*@{*/ /*@{*/
/*! @brief Defines WWDT driver version 2.1.0. */ /*! @brief Defines WWDT driver version 2.1.1. */
#define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) #define FSL_WWDT_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/ /*@}*/
/*! @name Refresh sequence */ /*! @name Refresh sequence */
@ -43,14 +43,16 @@ typedef struct _wwdt_config
changed after counter is below warning & window values changed after counter is below warning & window values
false: Disable watchdog protect; timeout value can be changed false: Disable watchdog protect; timeout value can be changed
at any time */ at any time */
bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented #if !(defined(FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK) && FSL_FEATURE_WWDT_HAS_NO_OSCILLATOR_LOCK)
Once set, this bit can only be cleared by a reset bool enableLockOscillator; /*!< true: Disabling or powering down the watchdog oscillator is prevented
false: Do not lock oscillator */ Once set, this bit can only be cleared by a reset
uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */ false: Do not lock oscillator */
uint32_t timeoutValue; /*!< Timeout value */ #endif
uint32_t warningValue; /*!< Watchdog time counter value that will generate a uint32_t windowValue; /*!< Window value, set this to 0xFFFFFF if windowing is not in effect */
warning interrupt. Set this to 0 for no warning */ uint32_t timeoutValue; /*!< Timeout value */
uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */ uint32_t warningValue; /*!< Watchdog time counter value that will generate a
warning interrupt. Set this to 0 for no warning */
uint32_t clockFreq_Hz; /*!< Watchdog clock source frequency. */
} wwdt_config_t; } wwdt_config_t;
/*! /*!