soc: arm: Add support for Ambiq Apollo4 Blue Plus.

Added devicetree and Kconfig for Apollo4 Blue Plus SoC.
They are needed for the apollo4p_blue_kxr_evb board.

Signed-off-by: Aaron Ye <aye@ambiq.com>

dts/arm/ambiq/ambiq_apollo4p_blue.dtsi

@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+#include <arm/armv7-m.dtsi>
+#include <mem.h>
+
+/ {
+	clocks {
+		uartclk: apb-pclk {
+			compatible = "fixed-clock";
+			clock-frequency = <24000000>;
+			#clock-cells = <0>;
+		};
+	};
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+		};
+	};
+
+	/* MRAM region */
+	flash0: flash@18000 {
+		compatible = "soc-nv-flash";
+		reg = <0x00018000 0x1e8000>;
+	};
+
+	/* TCM */
+	tcm: tcm@10000000 {
+		compatible = "zephyr,memory-region";
+		reg = <0x10000000 0x10000>;
+		zephyr,memory-region = "ITCM";
+	};
+
+	/* SRAM */
+	sram0: memory@10010000 {
+		compatible = "mmio-sram";
+		reg = <0x10010000 0x2B0000>;
+	};
+
+	soc {
+		pwrcfg: pwrcfg@40021000 {
+			compatible = "ambiq,pwrctrl";
+			reg = <0x40021000 0x400>;
+			#pwrcfg-cells = <2>;
+		};
+
+		stimer0: stimer@40008800 {
+			compatible = "ambiq,stimer";
+			reg = <0x40008800 0x80>;
+			interrupts = <32 0>;
+			status = "okay";
+		};
+
+		counter0: counter@40008000 {
+			compatible = "ambiq,counter";
+			reg = <0x40008000 0x80>;
+			interrupts = <67 0>;
+			status = "disabled";
+		};
+
+		uart0: uart@4001c000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001c000 0x1000>;
+			interrupts = <15 0>;
+			interrupt-names = "UART0";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
+		};
+		uart1: uart@4001d000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001d000 0x1000>;
+			interrupts = <16 0>;
+			interrupt-names = "UART1";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
+		};
+
+		uart2: uart@4001e000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001e000 0x1000>;
+			interrupts = <17 0>;
+			interrupt-names = "UART2";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
+		};
+
+		uart3: uart@4001f000 {
+			compatible = "ambiq,uart", "arm,pl011";
+			reg = <0x4001f000 0x1000>;
+			interrupts = <18 0>;
+			interrupt-names = "UART3";
+			status = "disabled";
+			clocks = <&uartclk>;
+			ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
+		};
+
+		pinctrl: pin-controller@40010000 {
+			compatible = "ambiq,apollo4-pinctrl";
+			reg = <0x40010000 0x800>;
+		};
+
+		wdt0: watchdog@40024000 {
+			compatible = "ambiq,watchdog";
+			reg = <0x40024000 0x400>;
+			interrupts = <1 0>;
+			clock-frequency = <16>;
+			status = "disabled";
+		};
+
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <3>;
+};

soc/arm/ambiq/apollo4x/Kconfig.defconfig.apollo4p_blue

@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: Apache-2.0
+#
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
+
+if SOC_APOLLO4P_BLUE
+
+config NUM_IRQS
+	default 83
+
+DT_NODE_SRAM := /memory@0
+
+config SRAM_NC_SIZE
+	default $(dt_node_reg_size_int,$(DT_NODE_SRAM),1,K)
+
+config SRAM_NC_BASE_ADDRESS
+	default $(dt_node_reg_addr_hex,$(DT_NODE_SRAM),1)
+
+endif # SOC_APOLLO4P_BLUE

soc/arm/ambiq/apollo4x/Kconfig.soc

@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 # Copyright (c) 2023 Antmicro <www.antmicro.com>
+# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
 
 choice
 	prompt "Ambiq Apollo4X Selection"
@@ -9,4 +10,7 @@ choice
 config SOC_APOLLO4P
 	bool "Apollo4P"
 
+config SOC_APOLLO4P_BLUE
+	bool "Apollo4 Blue Plus"
+
 endchoice