From 09b64467a9a1c7a839249bbf89474cfc8f64873f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Piotr=20Zi=C4=99cik?= Date: Thu, 11 Apr 2019 14:28:52 +0200 Subject: [PATCH] logging: log_backend_swo: Get clock frequency from DTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The log_backend_swo used system clock frequency as a base for SWO clock calculation. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik --- soc/arm/silabs_exx32/efm32hg/dts_fixup.h | 1 + soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h | 1 + soc/arm/silabs_exx32/efm32wg/dts_fixup.h | 1 + soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h | 1 + soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h | 1 + subsys/logging/log_backend_swo.c | 9 ++++----- 6 files changed, 9 insertions(+), 5 deletions(-) diff --git a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h index c527e9e60bb..e77f57d837e 100644 --- a/soc/arm/silabs_exx32/efm32hg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32hg/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL diff --git a/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h b/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h index 7e54a999752..7fea7bed0eb 100644 --- a/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32pg12b/dts_fixup.h @@ -7,6 +7,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h index 83bb2a211ab..724803b696a 100644 --- a/soc/arm/silabs_exx32/efm32wg/dts_fixup.h +++ b/soc/arm/silabs_exx32/efm32wg/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400C0000_LABEL diff --git a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h index b3e22ec1b6f..553808e2a96 100644 --- a/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32fg1p/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h index e14dfb877c7..8ff92e04378 100644 --- a/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h +++ b/soc/arm/silabs_exx32/efr32mg12p/dts_fixup.h @@ -9,6 +9,7 @@ /* SoC level DTS fixup file */ #define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS +#define DT_CPU_CLOCK_FREQUENCY DT_ARM_CORTEX_M4F_0_CLOCK_FREQUENCY #define DT_FLASH_DEV_BASE_ADDRESS DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_BASE_ADDRESS #define DT_FLASH_DEV_NAME DT_SILABS_GECKO_FLASH_CONTROLLER_400E0000_LABEL diff --git a/subsys/logging/log_backend_swo.c b/subsys/logging/log_backend_swo.c index bd2e7f4eaaa..acb1af61375 100644 --- a/subsys/logging/log_backend_swo.c +++ b/subsys/logging/log_backend_swo.c @@ -18,8 +18,8 @@ * this frequency should much the one set by the SWO viewer program. * * The initialization code assumes that SWO core frequency is equal to HCLK - * as defined by SYS_CLOCK_HW_CYCLES_PER_SEC Kconfig option. This may require - * additional, vendor specific configuration. + * as defined by DT_CPU_CLOCK_FREQUENCY. This may require additional, + * vendor specific configuration. */ #include @@ -36,13 +36,12 @@ #if CONFIG_LOG_BACKEND_SWO_FREQ_HZ == 0 #define SWO_FREQ_DIV 1 #else -#define SWO_FREQ (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC \ - + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2)) +#define SWO_FREQ (DT_CPU_CLOCK_FREQUENCY + (CONFIG_LOG_BACKEND_SWO_FREQ_HZ / 2)) #define SWO_FREQ_DIV (SWO_FREQ / CONFIG_LOG_BACKEND_SWO_FREQ_HZ) #if SWO_FREQ_DIV > 0xFFFF #error CONFIG_LOG_BACKEND_SWO_FREQ_HZ is too low. SWO clock divider is 16-bit. \ Minimum supported SWO clock frequency is \ - CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC/2^16. + [CPU Clock Frequency]/2^16. #endif #endif