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dt-bindings: clock: Add MCO register definition for STM32WBA

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Added MCO register definition to support MCO functionality in the STM32WBA
series. This update also includes the addition of MCO_PRE_DIV and MCO_SEL
defines.

Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
This commit is contained in:
Lubos Koudelka 2025-02-05 10:30:57 +01:00 • committed by Benjamin Cabé
commit 099970e130
1 changed files with 24 additions and 0 deletions
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24
include/zephyr/dt-bindings/clock/stm32wba_clock.h
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@ -100,5 +100,29 @@
#define ADC_SEL(val) STM32_DOMAIN_CLOCK(val, 7, 12, CCIPR3_REG)
/** BCDR1 devices */
#define RTC_SEL(val) STM32_DOMAIN_CLOCK(val, 3, 8, BCDR1_REG)
/** @brief RCC_CFGRx register offset */
#define CFGR1_REG 0x1C
/** CFGR1 devices */
#define MCO1_SEL(val) STM32_MCO_CFGR(val, 0xF, 24, CFGR1_REG)
#define MCO1_PRE(val) STM32_MCO_CFGR(val, 0x7, 28, CFGR1_REG)
/* MCO prescaler : division factor */
#define MCO_PRE_DIV_1 0
#define MCO_PRE_DIV_2 1
#define MCO_PRE_DIV_4 2
#define MCO_PRE_DIV_8 3
#define MCO_PRE_DIV_16 4
/* MCO clock output */
#define MCO_SEL_SYSCLKPRE 1
#define MCO_SEL_HSI16 3
#define MCO_SEL_HSE32 4
#define MCO_SEL_PLL1RCLK 5
#define MCO_SEL_LSI 6
#define MCO_SEL_LSE 7
#define MCO_SEL_PLL1PCLK 8
#define MCO_SEL_PLL1QCLK 9
#define MCO_SEL_HCLK5 10
#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_STM32WBA_CLOCK_H_ */