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drivers: pinmux: lpc11u6x: drop driver

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Drop LPC11U6X pinmux driver in favor of pinctrl.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas 2023-02-21 10:54:52 +01:00 • committed by Anas Nashif
commit 099012a59f
7 changed files with 0 additions and 181 deletions
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1
drivers/pinmux/CMakeLists.txt
View file

@ -1,6 +1,5 @@
# SPDX-License-Identifier: Apache-2.0
# Board initialization
zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X pinmux_lpc11u6x.c)
zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)

2
drivers/pinmux/Kconfig
View file

@ -24,8 +24,6 @@ config PINMUX_INIT_PRIORITY
rule for particular boards. Don't change this value unless you
know what you are doing.
source "drivers/pinmux/Kconfig.lpc11u6x"
source "drivers/pinmux/Kconfig.mcux"
source "drivers/pinmux/Kconfig.xec"

9
drivers/pinmux/Kconfig.lpc11u6x
View file

@ -1,9 +0,0 @@
# Copyright (c) 2020 2020 Seagate Technology LLC
# SPDX-License-Identifier: Apache-2.0
config PINMUX_LPC11U6X
bool "Pinmux driver for NXP LPC11U6X MCUs"
depends on SOC_SERIES_LPC11U6X
default y
help
Enable pinmux driver for NXP LPC11U6X MCUs.

114
drivers/pinmux/pinmux_lpc11u6x.c
View file

@ -1,114 +0,0 @@
/*
* Copyright (c) 2020 Seagate Technology LLC
*
* SPDX-License-Identifier: Apache-2.0
*/
#define DT_DRV_COMPAT nxp_lpc11u6x_pinmux
/**
* @file
* @brief pinmux driver for NXP LPC11U6X SoCs
*
* This driver allows to configure the IOCON (I/O control) registers found
* on the LPC11U6x MCUs.
*
* The IOCON registers are divided into three ports. The number of pins
* available on each port depends on the package type (48, 64 or 100 pins).
* Each port is handled as a distinct device and is defined by a dedicated
* device tree node. This node provides the port's base address and number
* of pins information.
*/
#include <errno.h>
#include <zephyr/drivers/pinmux.h>
struct pinmux_lpc11u6x_config {
uint8_t port;
volatile uint32_t *base;
uint8_t npins;
};
static int pinmux_lpc11u6x_set(const struct device *dev, uint32_t pin,
uint32_t func)
{
const struct pinmux_lpc11u6x_config *config = dev->config;
volatile uint32_t *base;
if (pin >= config->npins) {
return -EINVAL;
}
/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
if (config->port == 2 && pin > 1) {
base = config->base + 1;
} else {
base = config->base;
}
base[pin] = func;
return 0;
}
static int
pinmux_lpc11u6x_get(const struct device *dev, uint32_t pin, uint32_t *func)
{
const struct pinmux_lpc11u6x_config *config = dev->config;
volatile uint32_t *base;
if (pin >= config->npins) {
return -EINVAL;
}
/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
if (config->port == 2 && pin > 1) {
base = config->base + 1;
} else {
base = config->base;
}
*func = base[pin];
return 0;
}
static int
pinmux_lpc11u6x_pullup(const struct device *dev, uint32_t pin, uint8_t func)
{
return -ENOTSUP;
}
static int
pinmux_lpc11u6x_input(const struct device *dev, uint32_t pin, uint8_t func)
{
return -ENOTSUP;
}
static int pinmux_lpc11u6x_init(const struct device *dev)
{
return 0;
}
static const struct pinmux_driver_api pinmux_lpc11u6x_driver_api = {
.set = pinmux_lpc11u6x_set,
.get = pinmux_lpc11u6x_get,
.pullup = pinmux_lpc11u6x_pullup,
.input = pinmux_lpc11u6x_input,
};
#define PINMUX_LPC11U6X_INIT(id) \
static const struct pinmux_lpc11u6x_config \
pinmux_lpc11u6x_config_##id = { \
.port = id, \
.base = (volatile uint32_t *) DT_INST_REG_ADDR(id), \
.npins = DT_INST_REG_SIZE(id) / 4, \
}; \
\
DEVICE_DT_INST_DEFINE(id, &pinmux_lpc11u6x_init, \
NULL, NULL, &pinmux_lpc11u6x_config_##id, \
PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, \
&pinmux_lpc11u6x_driver_api);
DT_INST_FOREACH_STATUS_OKAY(PINMUX_LPC11U6X_INIT)

23
dts/arm/nxp/nxp_lpc11u6x.dtsi
View file

@ -76,29 +76,6 @@
reg = <0xf0 0x60>;
};
};
/* PIO0_0 to PIO0_23. */
pinmux0: pinmux@40044000 {
compatible = "nxp,lpc11u6x-pinmux";
#pinmux-cells = <2>;
reg = <0x40044000 0x60>;
status = "okay";
};
/* PIO1_0 to PIO1_31. */
pinmux1: pinmux@40044060 {
compatible = "nxp,lpc11u6x-pinmux";
#pinmux-cells = <2>;
reg = <0x40044060 0x80>;
status = "okay";
};
/* PIO2_0 to PIO2_23. */
pinmux2: pinmux@400440f0 {
compatible = "nxp,lpc11u6x-pinmux";
#pinmux-cells = <2>;
reg = <0x400440f0 0x64>;
status = "okay";
};
/* GPIO0_0 to GPIO0_23 */
gpio0: gpio@0 {

22
dts/bindings/pinctrl/nxp,lpc11u6x-pinmux.yaml
View file

@ -1,22 +0,0 @@
# Copyright (c) 2020 Seagate Technology LLC
# SPDX-License-Identifier: Apache-2.0
description: NXP LPC11U6X pinmux (aka IOCON) node
compatible: "nxp,lpc11u6x-pinmux"
include: base.yaml
properties:
reg:
required: true
"#pinmux-cells":
type: int
required: true
const: 2
description: number of items in a pinmux specifier
pinmux-cells:
- pin
- function

10
soc/arm/nxp_lpc/lpc11u6x/Kconfig.defconfig.series
View file

@ -14,14 +14,4 @@ config NUM_IRQS
# must be >= the highest interrupt number used
default 40
if PINMUX
# The pinmux device must be initialized before all the other devices, including
# the clock control device which uses it.
config PINMUX_INIT_PRIORITY
default 1
endif # PINMUX
endif # SOC_SERIES_LPC11U6X