drivers: pinmux: lpc11u6x: drop driver
Drop LPC11U6X pinmux driver in favor of pinctrl. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This commit is contained in:
Gerard Marull-Paretas
Anas Nashif
parent
33372b9e48
commit
099012a59f
7 changed files with 0 additions and 181 deletions
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@ -1,6 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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# Board initialization
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# Board initialization
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zephyr_sources_ifdef(CONFIG_PINMUX_LPC11U6X pinmux_lpc11u6x.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_MCUX pinmux_mcux.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
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zephyr_sources_ifdef(CONFIG_PINMUX_XEC pinmux_mchp_xec.c)
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@ -24,8 +24,6 @@ config PINMUX_INIT_PRIORITY
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rule for particular boards. Don't change this value unless you
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rule for particular boards. Don't change this value unless you
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know what you are doing.
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know what you are doing.
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source "drivers/pinmux/Kconfig.lpc11u6x"
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source "drivers/pinmux/Kconfig.mcux"
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source "drivers/pinmux/Kconfig.mcux"
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source "drivers/pinmux/Kconfig.xec"
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source "drivers/pinmux/Kconfig.xec"
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@ -1,9 +0,0 @@
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# Copyright (c) 2020 2020 Seagate Technology LLC
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# SPDX-License-Identifier: Apache-2.0
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config PINMUX_LPC11U6X
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bool "Pinmux driver for NXP LPC11U6X MCUs"
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depends on SOC_SERIES_LPC11U6X
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default y
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help
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Enable pinmux driver for NXP LPC11U6X MCUs.
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@ -1,114 +0,0 @@
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/*
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* Copyright (c) 2020 Seagate Technology LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_lpc11u6x_pinmux
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/**
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* @file
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* @brief pinmux driver for NXP LPC11U6X SoCs
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*
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* This driver allows to configure the IOCON (I/O control) registers found
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* on the LPC11U6x MCUs.
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*
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* The IOCON registers are divided into three ports. The number of pins
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* available on each port depends on the package type (48, 64 or 100 pins).
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* Each port is handled as a distinct device and is defined by a dedicated
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* device tree node. This node provides the port's base address and number
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* of pins information.
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*/
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#include <errno.h>
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#include <zephyr/drivers/pinmux.h>
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struct pinmux_lpc11u6x_config {
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uint8_t port;
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volatile uint32_t *base;
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uint8_t npins;
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};
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static int pinmux_lpc11u6x_set(const struct device *dev, uint32_t pin,
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uint32_t func)
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{
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const struct pinmux_lpc11u6x_config *config = dev->config;
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volatile uint32_t *base;
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if (pin >= config->npins) {
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return -EINVAL;
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}
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/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
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if (config->port == 2 && pin > 1) {
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base = config->base + 1;
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} else {
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base = config->base;
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}
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base[pin] = func;
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return 0;
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}
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static int
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pinmux_lpc11u6x_get(const struct device *dev, uint32_t pin, uint32_t *func)
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{
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const struct pinmux_lpc11u6x_config *config = dev->config;
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volatile uint32_t *base;
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if (pin >= config->npins) {
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return -EINVAL;
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}
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/* Handle 4 bytes hole between PIO2_1 and PIO2_2. */
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if (config->port == 2 && pin > 1) {
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base = config->base + 1;
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} else {
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base = config->base;
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}
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*func = base[pin];
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return 0;
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}
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static int
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pinmux_lpc11u6x_pullup(const struct device *dev, uint32_t pin, uint8_t func)
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{
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return -ENOTSUP;
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}
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static int
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pinmux_lpc11u6x_input(const struct device *dev, uint32_t pin, uint8_t func)
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{
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return -ENOTSUP;
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}
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static int pinmux_lpc11u6x_init(const struct device *dev)
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{
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return 0;
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}
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static const struct pinmux_driver_api pinmux_lpc11u6x_driver_api = {
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.set = pinmux_lpc11u6x_set,
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.get = pinmux_lpc11u6x_get,
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.pullup = pinmux_lpc11u6x_pullup,
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.input = pinmux_lpc11u6x_input,
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};
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#define PINMUX_LPC11U6X_INIT(id) \
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static const struct pinmux_lpc11u6x_config \
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pinmux_lpc11u6x_config_##id = { \
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.port = id, \
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.base = (volatile uint32_t *) DT_INST_REG_ADDR(id), \
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.npins = DT_INST_REG_SIZE(id) / 4, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(id, &pinmux_lpc11u6x_init, \
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NULL, NULL, &pinmux_lpc11u6x_config_##id, \
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PRE_KERNEL_1, CONFIG_PINMUX_INIT_PRIORITY, \
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&pinmux_lpc11u6x_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(PINMUX_LPC11U6X_INIT)
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@ -76,29 +76,6 @@
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reg = <0xf0 0x60>;
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reg = <0xf0 0x60>;
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};
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};
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};
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};
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/* PIO0_0 to PIO0_23. */
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pinmux0: pinmux@40044000 {
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compatible = "nxp,lpc11u6x-pinmux";
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#pinmux-cells = <2>;
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reg = <0x40044000 0x60>;
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status = "okay";
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};
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/* PIO1_0 to PIO1_31. */
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pinmux1: pinmux@40044060 {
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compatible = "nxp,lpc11u6x-pinmux";
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#pinmux-cells = <2>;
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reg = <0x40044060 0x80>;
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status = "okay";
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};
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/* PIO2_0 to PIO2_23. */
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pinmux2: pinmux@400440f0 {
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compatible = "nxp,lpc11u6x-pinmux";
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#pinmux-cells = <2>;
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reg = <0x400440f0 0x64>;
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status = "okay";
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};
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/* GPIO0_0 to GPIO0_23 */
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/* GPIO0_0 to GPIO0_23 */
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gpio0: gpio@0 {
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gpio0: gpio@0 {
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@ -1,22 +0,0 @@
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# Copyright (c) 2020 Seagate Technology LLC
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# SPDX-License-Identifier: Apache-2.0
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description: NXP LPC11U6X pinmux (aka IOCON) node
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compatible: "nxp,lpc11u6x-pinmux"
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include: base.yaml
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properties:
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reg:
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required: true
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"#pinmux-cells":
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type: int
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required: true
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const: 2
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description: number of items in a pinmux specifier
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pinmux-cells:
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- pin
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- function
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@ -14,14 +14,4 @@ config NUM_IRQS
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# must be >= the highest interrupt number used
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# must be >= the highest interrupt number used
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default 40
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default 40
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if PINMUX
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# The pinmux device must be initialized before all the other devices, including
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# the clock control device which uses it.
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config PINMUX_INIT_PRIORITY
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default 1
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endif # PINMUX
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endif # SOC_SERIES_LPC11U6X
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endif # SOC_SERIES_LPC11U6X
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