diff --git a/drivers/gpio/gpio_mcux_rgpio.c b/drivers/gpio/gpio_mcux_rgpio.c
index 9da25d48ae3..c8aea3794fe 100644
--- a/drivers/gpio/gpio_mcux_rgpio.c
+++ b/drivers/gpio/gpio_mcux_rgpio.c
@@ -1,5 +1,5 @@
 /*
- * Copyright 2023-2024, NXP
+ * Copyright 2023-2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -21,6 +21,12 @@
 	((const struct mcux_rgpio_config *)(_dev)->config)
 #define DEV_DATA(_dev) ((struct mcux_rgpio_data *)(_dev)->data)
 
+/*
+ * Default PAD config value for SCMI pinctrl:
+ * Pull down, Slight Fast Slew Rate, X4 driver strength.
+ */
+#define GPIO_PIN_DEFAUT_PAD_VAL 0x0000051e
+
 struct mcux_rgpio_config {
 	/* gpio_driver_config needs to be first */
 	struct gpio_driver_config common;
@@ -68,10 +74,15 @@ static int mcux_rgpio_configure(const struct device *dev,
 		return -ENOTSUP;
 	}
 
+#if defined(CONFIG_PINCTRL_IMX_SCMI)
+	/* For SCMI Pinctrl platform, set default PAD config value for SCMI pinctrl. */
+	uint32_t reg = GPIO_PIN_DEFAUT_PAD_VAL;
+#else
 	/* Set appropriate bits in pin configuration register */
 	volatile uint32_t *gpio_cfg_reg = (volatile uint32_t *)
 			((size_t)config->pin_muxes[cfg_idx].config_register);
 	uint32_t reg = *gpio_cfg_reg;
+#endif
 
 #if defined(CONFIG_SOC_SERIES_IMXRT118X)
 	/* PUE/PDRV types have the same ODE bit */