arch: arm64: Enable shared IRQ line for UART

Enable the shared IRQ for the UART line and enable the remaining tasks
that depends on a separated declaration of the TX/RX/Err/... IRQs.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>

arch/arm/core/aarch64/Kconfig

@@ -61,6 +61,9 @@ config CMSIS_V2_THREAD_MAX_STACK_SIZE
 config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
 	default 4096
 
+config IPM_CONSOLE_STACK_SIZE
+	default 2048
+
 if CPU_CORTEX_A
 
 config ARMV8_A

boards/arm/qemu_cortex_a53/qemu_cortex_a53.yaml

@@ -9,9 +9,4 @@ toolchain:
 ram: 128
 testing:
   ignore_tags:
-    - console
-    - drivers
     - interrupt
-    - net
-    - nfc
-    - shell

boards/arm/qemu_cortex_a53/qemu_cortex_a53_defconfig

@@ -10,6 +10,7 @@ CONFIG_SRAM_SIZE=131072
 
 # Enable UART driver
 CONFIG_SERIAL=y
+CONFIG_SHARED_IRQ=y
 
 # Enable console
 CONFIG_CONSOLE=y
@@ -18,3 +19,6 @@ CONFIG_UART_CONSOLE=y
 # Enable serial port
 CONFIG_UART_PL011=y
 CONFIG_UART_PL011_PORT0=y
+CONFIG_UART_INTERRUPT_DRIVEN=y
+CONFIG_SHARED_IRQ_0=y
+CONFIG_UART_PL011_PORT0_SHARED_IRQ=y

dts/arm/qemu-virt/qemu-virt-a53.dtsi

@@ -51,6 +51,15 @@
 			label = "UART_0";
 		};
 
+		sharedirq0: sharedirq0 {
+			compatible = "shared-irq";
+			label = "SHARED_IRQ";
+			interrupts = <GIC_SPI 1 0 IRQ_TYPE_LEVEL>;
+			interrupt-controller;
+			#interrupt-cells = <0>;
+			status = "okay";
+		};
+
 		flash0: flash@0 {
 			compatible = "soc-nv-flash";
 			reg = <0x0 DT_SIZE_K(64)>;

soc/arm/qemu_cortex_a53/dts_fixup.h

@@ -8,3 +8,8 @@
 #define DT_PL011_PORT0_NAME		DT_ARM_PL011_9000000_LABEL
 #define DT_PL011_PORT0_CLOCK_FREQUENCY	DT_ARM_PL011_9000000_CLOCK_FREQUENCY
 #define DT_PL011_PORT0_BAUD_RATE	DT_ARM_PL011_9000000_CURRENT_SPEED
+
+#define DT_INST_0_SHARED_IRQ_IRQ_0_SENSE	DT_INST_0_SHARED_IRQ_IRQ_0_FLAGS
+
+#undef DT_INST_0_SHARED_IRQ_IRQ_0
+#define DT_INST_0_SHARED_IRQ_IRQ_0	((DT_SHARED_IRQ_SHAREDIRQ0_IRQ_0 + 1) << 8)