diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx
new file mode 100644
index 00000000000..1210383f34e
--- /dev/null
+++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.defconfig.stm32l432xx
@@ -0,0 +1,20 @@
+# Kconfig - ST Microelectronics STM32L432KC MCU
+#
+# Copyright (c) 2016 Open-RnD Sp. z o.o.
+# Copyright (c) 2016 BayLibre, SAS
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_STM32L432XX
+
+config SOC
+	string
+	default stm32l432xx
+
+config NUM_IRQS
+	int
+	default 82
+
+endif # SOC_STM32L432XX
+
diff --git a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
index 69f80ebc27e..e636253663d 100644
--- a/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
+++ b/arch/arm/soc/st_stm32/stm32l4/Kconfig.soc
@@ -14,6 +14,10 @@ config SOC_STM32L476XX
 	bool "STM32L476XX"
 	select HAS_STM32CUBE
 
+config SOC_STM32L432XX
+	bool "STM32L432XX"
+	select HAS_STM32CUBE
+
 config SOC_STM32L475XG
 	bool "STM32L475XG"
 	select HAS_STM32CUBE
diff --git a/dts/arm/st/mem.h b/dts/arm/st/mem.h
index b9628bafebf..98e8713ce0d 100644
--- a/dts/arm/st/mem.h
+++ b/dts/arm/st/mem.h
@@ -39,6 +39,9 @@
 #elif defined(CONFIG_SOC_STM32L476XX)
 #define DT_FLASH_SIZE		__SIZE_K(1024)
 #define DT_SRAM_SIZE		__SIZE_K(96)
+#elif defined(CONFIG_SOC_STM32L432XX)
+#define DT_FLASH_SIZE		__SIZE_K(256)
+#define DT_SRAM_SIZE		__SIZE_K(64)
 #else
 #error "Flash and RAM sizes not defined for this chip"
 #endif
diff --git a/dts/arm/st/stm32l432.dtsi b/dts/arm/st/stm32l432.dtsi
new file mode 100644
index 00000000000..1b3c7bee59f
--- /dev/null
+++ b/dts/arm/st/stm32l432.dtsi
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2017 Linaro Limited
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+#include <st/mem.h>
+
+/ {
+	flash0: flash {
+		reg = <0x08000000 DT_FLASH_SIZE>;
+	};
+
+	sram0: memory {
+		reg = <0x20000000 DT_SRAM_SIZE>;
+	};
+
+	soc {
+		usart1: uart@40013800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40013800 0x400>;
+			interrupts = <37 0>;
+			status = "disabled";
+		};
+
+		usart2: uart@40004400 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38 0>;
+			status = "disabled";
+		};
+
+		usart3: uart@40004800 {
+			compatible = "st,stm32-usart", "st,stm32-uart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39 0>;
+			status = "disabled";
+		};
+
+		uart4: uart@40004c00 {
+			compatible = "st,stm32-uart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52 0>;
+			status = "disabled";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};