michaelh/zephyr
1
0
Fork 0
Code Releases Activity

soc: renesas: ra: Add RA2A1 SoC support

Browse source 
Add Support for Renesas RA2A1 SoC.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2024-06-01 13:16:33 +09:00 • committed by Henrik Brix Andersen
commit 0877b3a354
15 changed files with 638 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

15
soc/renesas/ra/ra2a1/CMakeLists.txt Normal file
View file

@ -0,0 +1,15 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
zephyr_include_directories(.)
zephyr_sources(
soc.c
)
zephyr_linker_sources(SECTIONS sections.ld)
zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
zephyr_linker_sources(ROM_START rom_start.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

12
soc/renesas/ra/ra2a1/Kconfig Normal file
View file

@ -0,0 +1,12 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2A1
select ARM
select CPU_CORTEX_M23
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_VTOR
select CPU_CORTEX_M_HAS_SYSTICK
select HAS_SWO
select XIP
select HAS_RENESAS_RA_FSP

12
soc/renesas/ra/ra2a1/Kconfig.defconfig Normal file
View file

@ -0,0 +1,12 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
if SOC_SERIES_RA2A1
config NUM_IRQS
default 32
config PINCTRL
default y
endif # SOC_SERIES_RA2A1

20
soc/renesas/ra/ra2a1/Kconfig.soc Normal file
View file

@ -0,0 +1,20 @@
# Copyright (c) 2024 TOKITA Hiroshi
# SPDX-License-Identifier: Apache-2.0
config SOC_SERIES_RA2A1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA2A1 series
config SOC_R7FA2A1AB3CFM
bool
select SOC_SERIES_RA2A1
help
R7FA2A1AB3CFM
config SOC_SERIES
default "ra2a1" if SOC_SERIES_RA2A1
config SOC
default "r7fa2a1ab3cfm" if SOC_R7FA2A1AB3CFM

13
soc/renesas/ra/ra2a1/data_sections.ld Normal file
View file

@ -0,0 +1,13 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION

12
soc/renesas/ra/ra2a1/ram_sections.ld Normal file
View file

@ -0,0 +1,12 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

11
soc/renesas/ra/ra2a1/rom_start.ld Normal file
View file

@ -0,0 +1,11 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;

116
soc/renesas/ra/ra2a1/sections.ld Normal file
View file

@ -0,0 +1,116 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
SECTION_PROLOGUE(.id_code,,)
{
KEEP(*(.id_code*))
} GROUP_LINK_IN(ID_CODE)
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = __OPTION_SETTING_OFS_Start + 0x04;
KEEP(*(.option_setting_ofs2))
. = __OPTION_SETTING_OFS_Start + 0x10;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
SECTION_PROLOGUE(.option_setting_sas,,)
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
SECTION_PROLOGUE(.option_setting_ns,,)
{
__OPTION_SETTING_NS_Start = .;
KEEP(*(.option_setting_ofs1))
. = __OPTION_SETTING_NS_Start + 0x04;
KEEP(*(.option_setting_ofs3))
. = __OPTION_SETTING_NS_Start + 0x10;
KEEP(*(.option_setting_banksel))
. = __OPTION_SETTING_NS_Start + 0x40;
KEEP(*(.option_setting_bps0))
. = __OPTION_SETTING_NS_Start + 0x44;
KEEP(*(.option_setting_bps1))
. = __OPTION_SETTING_NS_Start + 0x48;
KEEP(*(.option_setting_bps2))
. = __OPTION_SETTING_NS_Start + 0x4C;
KEEP(*(.option_setting_bps3))
. = __OPTION_SETTING_NS_Start + 0x60;
KEEP(*(.option_setting_pbps0))
. = __OPTION_SETTING_NS_Start + 0x64;
KEEP(*(.option_setting_pbps1))
. = __OPTION_SETTING_NS_Start + 0x68;
KEEP(*(.option_setting_pbps2))
. = __OPTION_SETTING_NS_Start + 0x6C;
KEEP(*(.option_setting_pbps3))
__OPTION_SETTING_NS_End = .;
} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
SECTION_PROLOGUE(.option_setting_s,,)
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = __OPTION_SETTING_S_Start + 0x04;
KEEP(*(.option_setting_ofs3_sec))
. = __OPTION_SETTING_S_Start + 0x10;
KEEP(*(.option_setting_banksel_sec))
. = __OPTION_SETTING_S_Start + 0x40;
KEEP(*(.option_setting_bps_sec0))
. = __OPTION_SETTING_S_Start + 0x44;
KEEP(*(.option_setting_bps_sec1))
. = __OPTION_SETTING_S_Start + 0x48;
KEEP(*(.option_setting_bps_sec2))
. = __OPTION_SETTING_S_Start + 0x4C;
KEEP(*(.option_setting_bps_sec3))
. = __OPTION_SETTING_S_Start + 0x60;
KEEP(*(.option_setting_pbps_sec0))
. = __OPTION_SETTING_S_Start + 0x64;
KEEP(*(.option_setting_pbps_sec1))
. = __OPTION_SETTING_S_Start + 0x68;
KEEP(*(.option_setting_pbps_sec2))
. = __OPTION_SETTING_S_Start + 0x6C;
KEEP(*(.option_setting_pbps_sec3))
. = __OPTION_SETTING_S_Start + 0x80;
KEEP(*(.option_setting_ofs1_sel))
. = __OPTION_SETTING_S_Start + 0x84;
KEEP(*(.option_setting_ofs3_sel))
. = __OPTION_SETTING_S_Start + 0x90;
KEEP(*(.option_setting_banksel_sel))
. = __OPTION_SETTING_S_Start + 0xC0;
KEEP(*(.option_setting_bps_sel0))
. = __OPTION_SETTING_S_Start + 0xC4;
KEEP(*(.option_setting_bps_sel1))
. = __OPTION_SETTING_S_Start + 0xC8;
KEEP(*(.option_setting_bps_sel2))
. = __OPTION_SETTING_S_Start + 0xCC;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
#endif

45
soc/renesas/ra/ra2a1/soc.c Normal file
View file

@ -0,0 +1,45 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RA2A1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include <bsp_api.h>
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
* So the init priority has to be 0 (zero).
*
* @return 0
*/
static int renesas_ra2a1_init(void)
{
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
bsp_clock_init();
return 0;
}
SYS_INIT(renesas_ra2a1_init, PRE_KERNEL_1, 0);

16
soc/renesas/ra/ra2a1/soc.h Normal file
View file

@ -0,0 +1,16 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file SoC configuration macros for the Renesas RA2A1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA2A1_SOC_H_ */

3
soc/renesas/ra/soc.yml
View file

@ -1,6 +1,9 @@
family:
- name: renesas_ra
series:
- name: ra2a1
socs:
- name: r7fa2a1ab3cfm
- name: ra4m1
socs:
- name: r7fa4m1ab3cfm