From 081c9c3becc8b99f295ed015c4fc8c1f718bb515 Mon Sep 17 00:00:00 2001 From: Erwan Gouriou Date: Fri, 4 May 2018 13:34:39 +0200 Subject: [PATCH] scripts: extract_dts_includes: Generate'_0' defines only when needed Indexed defines were systematically generated even when there was only one element to generate. So we ended up generated a lot of _0 defines. Then we needed to generate aliases to these _0 indexed defines, in order to get useful defines. For instance: #define GPIO_LEDS_0_GPIO_FLAGS_0 4 #define GPIO_LEDS_0_GPIO_PIN_0 5 #define GPIO_LEDS_0_GPIO_FLAGS GPIO_LEDS_0_GPIO_FLAGS_0 #define GPIO_LEDS_0_GPIO_PIN GPIO_LEDS_0_GPIO_PIN_0 This commit allows to generate _0 indexed define only if a property has more than one elements to define. Aliases generation to _0 indexed defines are also removed. Note: IRQ are left untouched since this is frequent to handle multiple IRQs in a driver Signed-off-by: Erwan Gouriou --- arch/arm/soc/arm/beetle/dts.fixup | 20 +++---- arch/arm/soc/atmel_sam/same70/dts.fixup | 4 +- arch/arm/soc/atmel_sam0/samd21/dts.fixup | 2 +- arch/arm/soc/nordic_nrf/nrf51/dts.fixup | 4 +- arch/arm/soc/nordic_nrf/nrf52/dts.fixup | 4 +- arch/arm/soc/nxp_imx/rt/dts.fixup | 10 ++-- arch/arm/soc/nxp_kinetis/k6x/dts.fixup | 26 ++++----- arch/arm/soc/nxp_kinetis/kl2x/dts.fixup | 10 ++-- arch/arm/soc/nxp_kinetis/kwx/dts.fixup | 24 ++++---- arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup | 2 +- arch/arm/soc/st_stm32/stm32f0/dts.fixup | 2 +- arch/arm/soc/st_stm32/stm32f3/dts.fixup | 2 +- arch/arm/soc/st_stm32/stm32f4/dts.fixup | 2 +- arch/arm/soc/st_stm32/stm32l4/dts.fixup | 2 +- arch/arm/soc/ti_simplelink/cc32xx/dts.fixup | 2 +- boards/arm/mps2_an385/dts.fixup | 34 +++++------ boards/arm/nrf52_pca20020/dts.fixup | 6 +- scripts/dts/extract_dts_includes.py | 65 ++++++++++++--------- 18 files changed, 114 insertions(+), 107 deletions(-) diff --git a/arch/arm/soc/arm/beetle/dts.fixup b/arch/arm/soc/arm/beetle/dts.fixup index c342179560e..0e0cfe04bed 100644 --- a/arch/arm/soc/arm/beetle/dts.fixup +++ b/arch/arm/soc/arm/beetle/dts.fixup @@ -3,39 +3,39 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* CMSDK APB Timers */ -#define CMSDK_APB_TIMER0 ARM_CMSDK_TIMER_40000000_BASE_ADDRESS_0 +#define CMSDK_APB_TIMER0 ARM_CMSDK_TIMER_40000000_BASE_ADDRESS #define CMSDK_APB_TIMER_0_IRQ ARM_CMSDK_TIMER_40000000_IRQ_0 -#define CMSDK_APB_TIMER1 ARM_CMSDK_TIMER_40001000_BASE_ADDRESS_0 +#define CMSDK_APB_TIMER1 ARM_CMSDK_TIMER_40001000_BASE_ADDRESS #define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 ARM_CMSDK_TIMER_40001000_IRQ_0 /* CMSDK APB Dual Timer */ -#define CMSDK_APB_DTIMER ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS_0 +#define CMSDK_APB_DTIMER ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS #define CMSDK_APB_DUALTIMER_IRQ ARM_CMSDK_DTIMER_40002000_IRQ_0 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ -#define CMSDK_APB_UART0 ARM_CMSDK_UART_40004000_BASE_ADDRESS_0 +#define CMSDK_APB_UART0 ARM_CMSDK_UART_40004000_BASE_ADDRESS #define CMSDK_APB_UART_0_IRQ ARM_CMSDK_UART_40004000_IRQ_0 #define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT0_NAME ARM_CMSDK_UART_40004000_LABEL -#define CMSDK_APB_UART1 ARM_CMSDK_UART_40005000_BASE_ADDRESS_0 +#define CMSDK_APB_UART1 ARM_CMSDK_UART_40005000_BASE_ADDRESS #define CMSDK_APB_UART_1_IRQ ARM_CMSDK_UART_40005000_IRQ_0 #define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT1_NAME ARM_CMSDK_UART_40005000_LABEL /* CMSDK APB Watchdog */ -#define CMSDK_APB_WDOG ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS_0 +#define CMSDK_APB_WDOG ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS /* CMSDK AHB General Purpose Input/Output (GPIO) */ -#define CMSDK_AHB_GPIO0 ARM_CMSDK_GPIO_40010000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO0 ARM_CMSDK_GPIO_40010000_BASE_ADDRESS -#define CMSDK_AHB_GPIO1 ARM_CMSDK_GPIO_40011000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO1 ARM_CMSDK_GPIO_40011000_BASE_ADDRESS -#define CMSDK_AHB_GPIO2 ARM_CMSDK_GPIO_40012000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO2 ARM_CMSDK_GPIO_40012000_BASE_ADDRESS -#define CMSDK_AHB_GPIO3 ARM_CMSDK_GPIO_40013000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO3 ARM_CMSDK_GPIO_40013000_BASE_ADDRESS /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/atmel_sam/same70/dts.fixup b/arch/arm/soc/atmel_sam/same70/dts.fixup index 67fd61f937a..b8f25469ea1 100644 --- a/arch/arm/soc/atmel_sam/same70/dts.fixup +++ b/arch/arm/soc/atmel_sam/same70/dts.fixup @@ -91,12 +91,12 @@ #define CONFIG_USART_SAM_PORT_2_IRQ_PRIO ATMEL_SAM_USART_4002C000_IRQ_0_PRIORITY #define CONFIG_USART_SAM_PORT_2_PERIPHERAL_ID ATMEL_SAM_USART_4002C000_PERIPHERAL_ID -#define CONFIG_ADC_0_BASE_ADDRESS ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS_0 +#define CONFIG_ADC_0_BASE_ADDRESS ATMEL_SAM_AFEC_4003C000_BASE_ADDRESS #define CONFIG_ADC_0_IRQ ATMEL_SAM_AFEC_4003C000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI ATMEL_SAM_AFEC_4003C000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME ATMEL_SAM_AFEC_4003C000_LABEL -#define CONFIG_ADC_1_BASE_ADDRESS ATMEL_SAM_AFEC_40064000_BASE_ADDRESS_0 +#define CONFIG_ADC_1_BASE_ADDRESS ATMEL_SAM_AFEC_40064000_BASE_ADDRESS #define CONFIG_ADC_1_IRQ ATMEL_SAM_AFEC_40064000_IRQ_0 #define CONFIG_ADC_1_IRQ_PRI ATMEL_SAM_AFEC_40064000_IRQ_0_PRIORITY #define CONFIG_ADC_1_NAME ATMEL_SAM_AFEC_40064000_LABEL diff --git a/arch/arm/soc/atmel_sam0/samd21/dts.fixup b/arch/arm/soc/atmel_sam0/samd21/dts.fixup index 932cb7aa1a2..a2cef0ae226 100644 --- a/arch/arm/soc/atmel_sam0/samd21/dts.fixup +++ b/arch/arm/soc/atmel_sam0/samd21/dts.fixup @@ -1,6 +1,6 @@ /* SoC level DTS fixup file */ -#define FLASH_DEV_BASE_ADDRESS ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS ATMEL_SAM0_NVMCTRL_41004000_BASE_ADDRESS #define FLASH_DEV_NAME ATMEL_SAM0_NVMCTRL_41004000_LABEL #define CONFIG_GPIO_SAM0_PORTA_LABEL ATMEL_SAM0_GPIO_41004400_LABEL diff --git a/arch/arm/soc/nordic_nrf/nrf51/dts.fixup b/arch/arm/soc/nordic_nrf/nrf51/dts.fixup index 15d381d815f..5de06876ff8 100644 --- a/arch/arm/soc/nordic_nrf/nrf51/dts.fixup +++ b/arch/arm/soc/nordic_nrf/nrf51/dts.fixup @@ -7,13 +7,13 @@ #define FLASH_DEV_NAME NRF_NRF51_FLASH_CONTROLLER_4001E000_LABEL -#define CONFIG_I2C_0_BASE_ADDR NORDIC_NRF5_I2C_40003000_BASE_ADDRESS_0 +#define CONFIG_I2C_0_BASE_ADDR NORDIC_NRF5_I2C_40003000_BASE_ADDRESS #define CONFIG_I2C_0_NAME NORDIC_NRF5_I2C_40003000_LABEL #define CONFIG_I2C_0_BITRATE NORDIC_NRF5_I2C_40003000_CLOCK_FREQUENCY #define CONFIG_I2C_0_IRQ_PRI NORDIC_NRF5_I2C_40003000_IRQ_0_PRIORITY #define CONFIG_I2C_0_IRQ NORDIC_NRF5_I2C_40003000_IRQ_0 -#define CONFIG_I2C_1_BASE_ADDR NORDIC_NRF5_I2C_40004000_BASE_ADDRESS_0 +#define CONFIG_I2C_1_BASE_ADDR NORDIC_NRF5_I2C_40004000_BASE_ADDRESS #define CONFIG_I2C_1_NAME NORDIC_NRF5_I2C_40004000_LABEL #define CONFIG_I2C_1_BITRATE NORDIC_NRF5_I2C_40004000_CLOCK_FREQUENCY #define CONFIG_I2C_1_IRQ_PRI NORDIC_NRF5_I2C_40004000_IRQ_0_PRIORITY diff --git a/arch/arm/soc/nordic_nrf/nrf52/dts.fixup b/arch/arm/soc/nordic_nrf/nrf52/dts.fixup index 1cee1160291..8a594b604fc 100644 --- a/arch/arm/soc/nordic_nrf/nrf52/dts.fixup +++ b/arch/arm/soc/nordic_nrf/nrf52/dts.fixup @@ -7,13 +7,13 @@ #define FLASH_DEV_NAME NRF_NRF52_FLASH_CONTROLLER_4001E000_LABEL -#define CONFIG_I2C_0_BASE_ADDR NORDIC_NRF5_I2C_40003000_BASE_ADDRESS_0 +#define CONFIG_I2C_0_BASE_ADDR NORDIC_NRF5_I2C_40003000_BASE_ADDRESS #define CONFIG_I2C_0_NAME NORDIC_NRF5_I2C_40003000_LABEL #define CONFIG_I2C_0_BITRATE NORDIC_NRF5_I2C_40003000_CLOCK_FREQUENCY #define CONFIG_I2C_0_IRQ_PRI NORDIC_NRF5_I2C_40003000_IRQ_0_PRIORITY #define CONFIG_I2C_0_IRQ NORDIC_NRF5_I2C_40003000_IRQ_0 -#define CONFIG_I2C_1_BASE_ADDR NORDIC_NRF5_I2C_40004000_BASE_ADDRESS_0 +#define CONFIG_I2C_1_BASE_ADDR NORDIC_NRF5_I2C_40004000_BASE_ADDRESS #define CONFIG_I2C_1_NAME NORDIC_NRF5_I2C_40004000_LABEL #define CONFIG_I2C_1_BITRATE NORDIC_NRF5_I2C_40004000_CLOCK_FREQUENCY #define CONFIG_I2C_1_IRQ_PRI NORDIC_NRF5_I2C_40004000_IRQ_0_PRIORITY diff --git a/arch/arm/soc/nxp_imx/rt/dts.fixup b/arch/arm/soc/nxp_imx/rt/dts.fixup index f820db466fc..9c4b6add3a6 100644 --- a/arch/arm/soc/nxp_imx/rt/dts.fixup +++ b/arch/arm/soc/nxp_imx/rt/dts.fixup @@ -8,29 +8,29 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_MCUX_CCM_BASE_ADDRESS NXP_IMX_CCM_400FC000_BASE_ADDRESS_0 +#define CONFIG_MCUX_CCM_BASE_ADDRESS NXP_IMX_CCM_400FC000_BASE_ADDRESS #define CONFIG_MCUX_CCM_NAME NXP_IMX_CCM_400FC000_LABEL -#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS NXP_IMX_GPIO_401B8000_BASE_ADDRESS_0 +#define CONFIG_MCUX_IGPIO_1_BASE_ADDRESS NXP_IMX_GPIO_401B8000_BASE_ADDRESS #define CONFIG_MCUX_IGPIO_1_NAME NXP_IMX_GPIO_401B8000_LABEL #define CONFIG_MCUX_IGPIO_1_IRQ_0 NXP_IMX_GPIO_401B8000_IRQ_0 #define CONFIG_MCUX_IGPIO_1_IRQ_0_PRI NXP_IMX_GPIO_401B8000_IRQ_0_PRIORITY #define CONFIG_MCUX_IGPIO_1_IRQ_1 NXP_IMX_GPIO_401B8000_IRQ_1 #define CONFIG_MCUX_IGPIO_1_IRQ_1_PRI NXP_IMX_GPIO_401B8000_IRQ_1_PRIORITY -#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS NXP_IMX_GPIO_400C0000_BASE_ADDRESS_0 +#define CONFIG_MCUX_IGPIO_5_BASE_ADDRESS NXP_IMX_GPIO_400C0000_BASE_ADDRESS #define CONFIG_MCUX_IGPIO_5_NAME NXP_IMX_GPIO_400C0000_LABEL #define CONFIG_MCUX_IGPIO_5_IRQ_0 NXP_IMX_GPIO_400C0000_IRQ_0 #define CONFIG_MCUX_IGPIO_5_IRQ_0_PRI NXP_IMX_GPIO_400C0000_IRQ_0_PRIORITY #define CONFIG_MCUX_IGPIO_5_IRQ_1 NXP_IMX_GPIO_400C0000_IRQ_1 #define CONFIG_MCUX_IGPIO_5_IRQ_1_PRI NXP_IMX_GPIO_400C0000_IRQ_1_PRIORITY -#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS NXP_KINETIS_LPUART_40184000_BASE_ADDRESS_0 +#define CONFIG_UART_MCUX_LPUART_1_BASE_ADDRESS NXP_KINETIS_LPUART_40184000_BASE_ADDRESS #define CONFIG_UART_MCUX_LPUART_1_NAME NXP_KINETIS_LPUART_40184000_LABEL #define CONFIG_UART_MCUX_LPUART_1_IRQ NXP_KINETIS_LPUART_40184000_IRQ_0 #define CONFIG_UART_MCUX_LPUART_1_IRQ_PRI NXP_KINETIS_LPUART_40184000_IRQ_0_PRIORITY #define CONFIG_UART_MCUX_LPUART_1_BAUD_RATE NXP_KINETIS_LPUART_40184000_CURRENT_SPEED #define CONFIG_UART_MCUX_LPUART_1_CLOCK_NAME NXP_IMX_CCM_400FC000_LABEL -#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CCM_CLK_NAME_0 +#define CONFIG_UART_MCUX_LPUART_1_CLOCK_SUBSYS NXP_KINETIS_LPUART_40184000_CCM_CLK_NAME /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/nxp_kinetis/k6x/dts.fixup b/arch/arm/soc/nxp_kinetis/k6x/dts.fixup index 27be9cd1f90..ba6447e40f4 100644 --- a/arch/arm/soc/nxp_kinetis/k6x/dts.fixup +++ b/arch/arm/soc/nxp_kinetis/k6x/dts.fixup @@ -8,7 +8,7 @@ #define CONFIG_UART_MCUX_0_IRQ_STATUS NXP_KINETIS_UART_4006A000_IRQ_STATUS #define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME #define CONFIG_UART_MCUX_1_BAUD_RATE NXP_KINETIS_UART_4006B000_CURRENT_SPEED #define CONFIG_UART_MCUX_1_NAME NXP_KINETIS_UART_4006B000_LABEL @@ -17,7 +17,7 @@ #define CONFIG_UART_MCUX_1_IRQ_STATUS NXP_KINETIS_UART_4006B000_IRQ_STATUS #define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_1_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME #define CONFIG_UART_MCUX_2_BAUD_RATE NXP_KINETIS_UART_4006C000_CURRENT_SPEED #define CONFIG_UART_MCUX_2_NAME NXP_KINETIS_UART_4006C000_LABEL @@ -26,7 +26,7 @@ #define CONFIG_UART_MCUX_2_IRQ_STATUS NXP_KINETIS_UART_4006C000_IRQ_STATUS #define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_2_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME #define CONFIG_UART_MCUX_3_BAUD_RATE NXP_KINETIS_UART_4006D000_CURRENT_SPEED #define CONFIG_UART_MCUX_3_NAME NXP_KINETIS_UART_4006D000_LABEL @@ -35,7 +35,7 @@ #define CONFIG_UART_MCUX_3_IRQ_STATUS NXP_KINETIS_UART_4006D000_IRQ_STATUS #define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_3_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME #define CONFIG_UART_MCUX_4_BAUD_RATE NXP_KINETIS_UART_400EA000_CURRENT_SPEED #define CONFIG_UART_MCUX_4_NAME NXP_KINETIS_UART_400EA000_LABEL @@ -44,7 +44,7 @@ #define CONFIG_UART_MCUX_4_IRQ_STATUS NXP_KINETIS_UART_400EA000_IRQ_STATUS #define CONFIG_UART_MCUX_4_IRQ_STATUS_PRI NXP_KINETIS_UART_400EA000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_4_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_4_CLOCK_SUBSYS NXP_KINETIS_UART_400EA000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_4_CLOCK_SUBSYS NXP_KINETIS_UART_400EA000_SIM_CLK_NAME #define CONFIG_UART_MCUX_5_BAUD_RATE NXP_KINETIS_UART_400EB000_CURRENT_SPEED #define CONFIG_UART_MCUX_5_NAME NXP_KINETIS_UART_400EB000_LABEL @@ -53,39 +53,39 @@ #define CONFIG_UART_MCUX_5_IRQ_STATUS NXP_KINETIS_UART_400EB000_IRQ_STATUS #define CONFIG_UART_MCUX_5_IRQ_STATUS_PRI NXP_KINETIS_UART_400EB000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_5_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_5_CLOCK_SUBSYS NXP_KINETIS_UART_400EB000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_5_CLOCK_SUBSYS NXP_KINETIS_UART_400EB000_SIM_CLK_NAME -#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0 +#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS #define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL -#define CONFIG_ADC_1_BASE_ADDRESS NXP_KINETIS_ADC16_400BB000_BASE_ADDRESS_0 +#define CONFIG_ADC_1_BASE_ADDRESS NXP_KINETIS_ADC16_400BB000_BASE_ADDRESS #define CONFIG_ADC_1_IRQ NXP_KINETIS_ADC16_400BB000_IRQ_0 #define CONFIG_ADC_1_IRQ_PRI NXP_KINETIS_ADC16_400BB000_IRQ_0_PRIORITY #define CONFIG_ADC_1_NAME NXP_KINETIS_ADC16_400BB000_LABEL -#define CONFIG_FTM_3_BASE_ADDRESS NXP_KINETIS_FTM_400B9000_BASE_ADDRESS_0 +#define CONFIG_FTM_3_BASE_ADDRESS NXP_KINETIS_FTM_400B9000_BASE_ADDRESS #define CONFIG_FTM_3_IRQ NXP_KINETIS_FTM_400B9000_IRQ_0 #define CONFIG_FTM_3_IRQ_PRI NXP_KINETIS_FTM_400B9000_IRQ_0_PRIORITY #define CONFIG_FTM_3_NAME NXP_KINETIS_FTM_400B9000_LABEL -#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0 +#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS #define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL #define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0 +#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS #define CONFIG_I2C_MCUX_0_IRQ NXP_KINETIS_I2C_40066000_IRQ_0 #define CONFIG_I2C_MCUX_0_IRQ_PRI NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY #define CONFIG_I2C_MCUX_0_BITRATE NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY #define CONFIG_I2C_1_NAME NXP_KINETIS_I2C_40067000_LABEL -#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS_0 +#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS #define CONFIG_I2C_MCUX_1_IRQ NXP_KINETIS_I2C_40067000_IRQ_0 #define CONFIG_I2C_MCUX_1_IRQ_PRI NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY #define CONFIG_I2C_MCUX_1_BITRATE NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY -#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFE_40020000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFE_40020000_BASE_ADDRESS #define FLASH_DEV_NAME NXP_KINETIS_FTFE_40020000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/nxp_kinetis/kl2x/dts.fixup b/arch/arm/soc/nxp_kinetis/kl2x/dts.fixup index 80b412e0088..40566301a3b 100644 --- a/arch/arm/soc/nxp_kinetis/kl2x/dts.fixup +++ b/arch/arm/soc/nxp_kinetis/kl2x/dts.fixup @@ -2,23 +2,23 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V6M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS #define CONFIG_UART_MCUX_LPSCI_0_NAME NXP_KINETIS_LPSCI_4006A000_LABEL #define CONFIG_UART_MCUX_LPSCI_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_SUBSYS NXP_KINETIS_LPSCI_4006A000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_LPSCI_0_CLOCK_SUBSYS NXP_KINETIS_LPSCI_4006A000_SIM_CLK_NAME -#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0 +#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS #define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL -#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0 +#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS #define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL #define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0 +#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS #define CONFIG_I2C_MCUX_0_IRQ NXP_KINETIS_I2C_40066000_IRQ_0 #define CONFIG_I2C_MCUX_0_IRQ_PRI NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY #define CONFIG_I2C_MCUX_0_BITRATE NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY -#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFA_40020000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFA_40020000_BASE_ADDRESS #define FLASH_DEV_NAME NXP_KINETIS_FTFA_40020000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/nxp_kinetis/kwx/dts.fixup b/arch/arm/soc/nxp_kinetis/kwx/dts.fixup index cf488e78427..b85a471a8bd 100644 --- a/arch/arm/soc/nxp_kinetis/kwx/dts.fixup +++ b/arch/arm/soc/nxp_kinetis/kwx/dts.fixup @@ -1,28 +1,28 @@ /* SoC level DTS fixup file */ -#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS_0 +#define CONFIG_ADC_0_BASE_ADDRESS NXP_KINETIS_ADC16_4003B000_BASE_ADDRESS #define CONFIG_ADC_0_IRQ NXP_KINETIS_ADC16_4003B000_IRQ_0 #define CONFIG_ADC_0_IRQ_PRI NXP_KINETIS_ADC16_4003B000_IRQ_0_PRIORITY #define CONFIG_ADC_0_NAME NXP_KINETIS_ADC16_4003B000_LABEL #define CONFIG_I2C_0_NAME NXP_KINETIS_I2C_40066000_LABEL -#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS_0 +#define CONFIG_I2C_MCUX_0_BASE_ADDRESS NXP_KINETIS_I2C_40066000_BASE_ADDRESS #define CONFIG_I2C_MCUX_0_IRQ NXP_KINETIS_I2C_40066000_IRQ_0 #define CONFIG_I2C_MCUX_0_IRQ_PRI NXP_KINETIS_I2C_40066000_IRQ_0_PRIORITY #define CONFIG_I2C_MCUX_0_BITRATE NXP_KINETIS_I2C_40066000_CLOCK_FREQUENCY #define CONFIG_I2C_1_NAME NXP_KINETIS_I2C_40067000_LABEL -#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS_0 +#define CONFIG_I2C_MCUX_1_BASE_ADDRESS NXP_KINETIS_I2C_40067000_BASE_ADDRESS #define CONFIG_I2C_MCUX_1_IRQ NXP_KINETIS_I2C_40067000_IRQ_0 #define CONFIG_I2C_MCUX_1_IRQ_PRI NXP_KINETIS_I2C_40067000_IRQ_0_PRIORITY #define CONFIG_I2C_MCUX_1_BITRATE NXP_KINETIS_I2C_40067000_CLOCK_FREQUENCY -#define CONFIG_FTM_1_BASE_ADDRESS NXP_KINETIS_FTM_40039000_BASE_ADDRESS_0 +#define CONFIG_FTM_1_BASE_ADDRESS NXP_KINETIS_FTM_40039000_BASE_ADDRESS #define CONFIG_FTM_1_IRQ NXP_KINETIS_FTM_40039000_IRQ_0 #define CONFIG_FTM_1_IRQ_PRI NXP_KINETIS_FTM_40039000_IRQ_0_PRIORITY #define CONFIG_FTM_1_NAME NXP_KINETIS_FTM_40039000_LABEL -#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS_0 +#define CONFIG_SIM_BASE_ADDRESS NXP_KINETIS_SIM_40047000_BASE_ADDRESS #define CONFIG_SIM_NAME NXP_KINETIS_SIM_40047000_LABEL #if defined(CONFIG_SOC_MKW22D5) || defined(CONFIG_SOC_MKW24D5) @@ -35,7 +35,7 @@ #define CONFIG_UART_MCUX_0_IRQ_STATUS NXP_KINETIS_UART_4006A000_IRQ_STATUS #define CONFIG_UART_MCUX_0_IRQ_STATUS_PRI NXP_KINETIS_UART_4006A000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_0_CLOCK_SUBSYS NXP_KINETIS_UART_4006A000_SIM_CLK_NAME #define CONFIG_UART_MCUX_1_BAUD_RATE NXP_KINETIS_UART_4006B000_CURRENT_SPEED #define CONFIG_UART_MCUX_1_NAME NXP_KINETIS_UART_4006B000_LABEL @@ -44,7 +44,7 @@ #define CONFIG_UART_MCUX_1_IRQ_STATUS NXP_KINETIS_UART_4006B000_IRQ_STATUS #define CONFIG_UART_MCUX_1_IRQ_STATUS_PRI NXP_KINETIS_UART_4006B000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_1_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_1_CLOCK_SUBSYS NXP_KINETIS_UART_4006B000_SIM_CLK_NAME #define CONFIG_UART_MCUX_2_BAUD_RATE NXP_KINETIS_UART_4006C000_CURRENT_SPEED #define CONFIG_UART_MCUX_2_NAME NXP_KINETIS_UART_4006C000_LABEL @@ -53,7 +53,7 @@ #define CONFIG_UART_MCUX_2_IRQ_STATUS NXP_KINETIS_UART_4006C000_IRQ_STATUS #define CONFIG_UART_MCUX_2_IRQ_STATUS_PRI NXP_KINETIS_UART_4006C000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_2_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_2_CLOCK_SUBSYS NXP_KINETIS_UART_4006C000_SIM_CLK_NAME #define CONFIG_UART_MCUX_3_BAUD_RATE NXP_KINETIS_UART_4006D000_CURRENT_SPEED #define CONFIG_UART_MCUX_3_NAME NXP_KINETIS_UART_4006D000_LABEL @@ -62,9 +62,9 @@ #define CONFIG_UART_MCUX_3_IRQ_STATUS NXP_KINETIS_UART_4006D000_IRQ_STATUS #define CONFIG_UART_MCUX_3_IRQ_STATUS_PRI NXP_KINETIS_UART_4006D000_IRQ_STATUS_PRIORITY #define CONFIG_UART_MCUX_3_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_3_CLOCK_SUBSYS NXP_KINETIS_UART_4006D000_SIM_CLK_NAME -#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFL_40020000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFL_40020000_BASE_ADDRESS #define FLASH_DEV_NAME NXP_KINETIS_FTFL_40020000_LABEL #endif /* CONFIG_SOC_MKW22D5 || CONFIG_SOC_MKW24D5 */ @@ -76,9 +76,9 @@ #define CONFIG_UART_MCUX_LPUART_0_IRQ_PRI NXP_KINETIS_LPUART_40054000_IRQ_0_PRIORITY #define CONFIG_UART_MCUX_LPUART_0_NAME NXP_KINETIS_LPUART_40054000_LABEL #define CONFIG_UART_MCUX_LPUART_0_CLOCK_NAME NXP_KINETIS_SIM_40047000_LABEL -#define CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS NXP_KINETIS_LPUART_40054000_SIM_CLK_NAME_0 +#define CONFIG_UART_MCUX_LPUART_0_CLOCK_SUBSYS NXP_KINETIS_LPUART_40054000_SIM_CLK_NAME -#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFA_40020000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS NXP_KINETIS_FTFA_40020000_BASE_ADDRESS #define FLASH_DEV_NAME NXP_KINETIS_FTFA_40020000_LABEL #endif /* CONFIG_SOC_MKW40Z4 || CONFIG_SOC_MKW41Z4 */ /* End of SoC Level DTS fixup file */ diff --git a/arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup b/arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup index 02c0fe1008d..a108cd4b48d 100644 --- a/arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup +++ b/arch/arm/soc/nxp_lpc/lpc54xxx/dts.fixup @@ -8,7 +8,7 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS -#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS NXP_LPC_USART_40086000_BASE_ADDRESS_0 +#define CONFIG_USART_MCUX_LPC_0_BASE_ADDRESS NXP_LPC_USART_40086000_BASE_ADDRESS #define CONFIG_USART_MCUX_LPC_0_BAUD_RATE NXP_LPC_USART_40086000_CURRENT_SPEED #define CONFIG_USART_MCUX_LPC_0_IRQ_PRI NXP_LPC_USART_40086000_IRQ_0_PRIORITY #define CONFIG_USART_MCUX_LPC_0_NAME NXP_LPC_USART_40086000_LABEL diff --git a/arch/arm/soc/st_stm32/stm32f0/dts.fixup b/arch/arm/soc/st_stm32/stm32f0/dts.fixup index 1842b14e12b..1cc751c34f8 100644 --- a/arch/arm/soc/st_stm32/stm32f0/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f0/dts.fixup @@ -36,7 +36,7 @@ #define CONFIG_SPI_2_NAME ST_STM32_SPI_FIFO_40003800_LABEL #define CONFIG_SPI_2_IRQ ST_STM32_SPI_FIFO_40003800_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS ST_STM32F0_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define FLASH_DEV_NAME ST_STM32F0_FLASH_CONTROLLER_40022000_LABEL #define CONFIG_USB_BASE_ADDRESS ST_STM32_USB_40005C00_BASE_ADDRESS diff --git a/arch/arm/soc/st_stm32/stm32f3/dts.fixup b/arch/arm/soc/st_stm32/stm32f3/dts.fixup index 5141ace7538..06ca340ae83 100644 --- a/arch/arm/soc/st_stm32/stm32f3/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f3/dts.fixup @@ -50,7 +50,7 @@ #define CONFIG_SPI_4_NAME ST_STM32_SPI_FIFO_40013C00_LABEL #define CONFIG_SPI_4_IRQ ST_STM32_SPI_FIFO_40013C00_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS ST_STM32F3_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define FLASH_DEV_NAME ST_STM32F3_FLASH_CONTROLLER_40022000_LABEL #define CONFIG_USB_BASE_ADDRESS ST_STM32_USB_40005C00_BASE_ADDRESS diff --git a/arch/arm/soc/st_stm32/stm32f4/dts.fixup b/arch/arm/soc/st_stm32/stm32f4/dts.fixup index e64a12cf3cf..ec97522d5ec 100644 --- a/arch/arm/soc/st_stm32/stm32f4/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32f4/dts.fixup @@ -80,7 +80,7 @@ #define CONFIG_SPI_6_NAME ST_STM32_SPI_40015400_LABEL #define CONFIG_SPI_6_IRQ ST_STM32_SPI_40015400_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS ST_STM32F4_FLASH_CONTROLLER_40023C00_BASE_ADDRESS #define FLASH_DEV_NAME ST_STM32F4_FLASH_CONTROLLER_40023C00_LABEL #define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS diff --git a/arch/arm/soc/st_stm32/stm32l4/dts.fixup b/arch/arm/soc/st_stm32/stm32l4/dts.fixup index a46fd707580..0b3e986c400 100644 --- a/arch/arm/soc/st_stm32/stm32l4/dts.fixup +++ b/arch/arm/soc/st_stm32/stm32l4/dts.fixup @@ -63,7 +63,7 @@ #define CONFIG_SPI_3_NAME ST_STM32_SPI_FIFO_40003C00_LABEL #define CONFIG_SPI_3_IRQ ST_STM32_SPI_FIFO_40003C00_IRQ_0 -#define FLASH_DEV_BASE_ADDRESS ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS_0 +#define FLASH_DEV_BASE_ADDRESS ST_STM32L4_FLASH_CONTROLLER_40022000_BASE_ADDRESS #define FLASH_DEV_NAME ST_STM32L4_FLASH_CONTROLLER_40022000_LABEL #define CONFIG_USB_BASE_ADDRESS ST_STM32_OTGFS_50000000_BASE_ADDRESS diff --git a/arch/arm/soc/ti_simplelink/cc32xx/dts.fixup b/arch/arm/soc/ti_simplelink/cc32xx/dts.fixup index 452d6267f16..2922127e2a0 100644 --- a/arch/arm/soc/ti_simplelink/cc32xx/dts.fixup +++ b/arch/arm/soc/ti_simplelink/cc32xx/dts.fixup @@ -4,7 +4,7 @@ #define CONFIG_UART_CC32XX_NAME TI_CC32XX_UART_4000C000_LABEL #define CONFIG_I2C_0_LABEL TI_CC32XX_I2C_40020000_LABEL -#define CONFIG_I2C_0_BASE_ADDRESS TI_CC32XX_I2C_40020000_BASE_ADDRESS_0 +#define CONFIG_I2C_0_BASE_ADDRESS TI_CC32XX_I2C_40020000_BASE_ADDRESS #define CONFIG_I2C_0_BITRATE TI_CC32XX_I2C_40020000_CLOCK_FREQUENCY #define CONFIG_I2C_0_IRQ TI_CC32XX_I2C_40020000_IRQ_0 #define CONFIG_I2C_0_IRQ_PRIORITY TI_CC32XX_I2C_40020000_IRQ_0_PRIORITY diff --git a/boards/arm/mps2_an385/dts.fixup b/boards/arm/mps2_an385/dts.fixup index c8aa805dfab..e4a9b16ed0c 100644 --- a/boards/arm/mps2_an385/dts.fixup +++ b/boards/arm/mps2_an385/dts.fixup @@ -3,46 +3,46 @@ #define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS /* CMSDK APB Timers */ -#define CMSDK_APB_TIMER0 ARM_CMSDK_TIMER_40000000_BASE_ADDRESS_0 +#define CMSDK_APB_TIMER0 ARM_CMSDK_TIMER_40000000_BASE_ADDRESS #define CMSDK_APB_TIMER_0_IRQ ARM_CMSDK_TIMER_40000000_IRQ_0 -#define CMSDK_APB_TIMER1 ARM_CMSDK_TIMER_40001000_BASE_ADDRESS_0 +#define CMSDK_APB_TIMER1 ARM_CMSDK_TIMER_40001000_BASE_ADDRESS #define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 ARM_CMSDK_TIMER_40001000_IRQ_0 /* CMSDK APB Dual Timer */ -#define CMSDK_APB_DTIMER ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS_0 +#define CMSDK_APB_DTIMER ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS #define CMSDK_APB_DUALTIMER_IRQ ARM_CMSDK_DTIMER_40002000_IRQ_0 /* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */ -#define CMSDK_APB_UART0 ARM_CMSDK_UART_40004000_BASE_ADDRESS_0 +#define CMSDK_APB_UART0 ARM_CMSDK_UART_40004000_BASE_ADDRESS #define CMSDK_APB_UART_0_IRQ_TX ARM_CMSDK_UART_40004000_IRQ_0 #define CMSDK_APB_UART_0_IRQ_RX ARM_CMSDK_UART_40004000_IRQ_1 #define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT0_NAME ARM_CMSDK_UART_40004000_LABEL -#define CMSDK_APB_UART1 ARM_CMSDK_UART_40005000_BASE_ADDRESS_0 +#define CMSDK_APB_UART1 ARM_CMSDK_UART_40005000_BASE_ADDRESS #define CMSDK_APB_UART_1_IRQ_TX ARM_CMSDK_UART_40005000_IRQ_0 #define CMSDK_APB_UART_1_IRQ_RX ARM_CMSDK_UART_40005000_IRQ_1 #define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT1_NAME ARM_CMSDK_UART_40005000_LABEL -#define CMSDK_APB_UART2 ARM_CMSDK_UART_40006000_BASE_ADDRESS_0 +#define CMSDK_APB_UART2 ARM_CMSDK_UART_40006000_BASE_ADDRESS #define CMSDK_APB_UART_2_IRQ_TX ARM_CMSDK_UART_40006000_IRQ_0 #define CMSDK_APB_UART_2_IRQ_RX ARM_CMSDK_UART_40006000_IRQ_1 #define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE ARM_CMSDK_UART_40006000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT2_NAME ARM_CMSDK_UART_40006000_LABEL -#define CMSDK_APB_UART3 ARM_CMSDK_UART_40007000_BASE_ADDRESS_0 +#define CMSDK_APB_UART3 ARM_CMSDK_UART_40007000_BASE_ADDRESS #define CMSDK_APB_UART_3_IRQ_TX ARM_CMSDK_UART_40007000_IRQ_0 #define CMSDK_APB_UART_3_IRQ_RX ARM_CMSDK_UART_40007000_IRQ_1 #define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY #define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE ARM_CMSDK_UART_40007000_CURRENT_SPEED #define CONFIG_UART_CMSDK_APB_PORT3_NAME ARM_CMSDK_UART_40007000_LABEL -#define CMSDK_APB_UART4 ARM_CMSDK_UART_40009000_BASE_ADDRESS_0 +#define CMSDK_APB_UART4 ARM_CMSDK_UART_40009000_BASE_ADDRESS #define CMSDK_APB_UART_4_IRQ_TX ARM_CMSDK_UART_40009000_IRQ_0 #define CMSDK_APB_UART_4_IRQ_RX ARM_CMSDK_UART_40009000_IRQ_1 #define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY @@ -50,32 +50,32 @@ #define CONFIG_UART_CMSDK_APB_PORT4_NAME ARM_CMSDK_UART_40009000_LABEL /* CMSDK APB Watchdog */ -#define CMSDK_APB_WDOG ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS_0 +#define CMSDK_APB_WDOG ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS /* CMSDK AHB General Purpose Input/Output (GPIO) */ -#define CMSDK_AHB_GPIO0 ARM_CMSDK_GPIO_40010000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO0 ARM_CMSDK_GPIO_40010000_BASE_ADDRESS #define IRQ_PORT0_ALL ARM_CMSDK_GPIO_40010000_IRQ_0 -#define CMSDK_AHB_GPIO1 ARM_CMSDK_GPIO_40011000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO1 ARM_CMSDK_GPIO_40011000_BASE_ADDRESS #define IRQ_PORT1_ALL ARM_CMSDK_GPIO_40011000_IRQ_0 -#define CMSDK_AHB_GPIO2 ARM_CMSDK_GPIO_40012000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO2 ARM_CMSDK_GPIO_40012000_BASE_ADDRESS #define IRQ_PORT2_ALL ARM_CMSDK_GPIO_40012000_IRQ_0 -#define CMSDK_AHB_GPIO3 ARM_CMSDK_GPIO_40013000_BASE_ADDRESS_0 +#define CMSDK_AHB_GPIO3 ARM_CMSDK_GPIO_40013000_BASE_ADDRESS #define IRQ_PORT3_ALL ARM_CMSDK_GPIO_40013000_IRQ_0 /* I2C SBCon */ -#define I2C_SBCON_0_BASE_ADDR ARM_VERSATILE_I2C_40022000_BASE_ADDRESS_0 +#define I2C_SBCON_0_BASE_ADDR ARM_VERSATILE_I2C_40022000_BASE_ADDRESS #define I2C_SBCON_0_NAME ARM_VERSATILE_I2C_40022000_LABEL -#define I2C_SBCON_1_BASE_ADDR ARM_VERSATILE_I2C_40023000_BASE_ADDRESS_0 +#define I2C_SBCON_1_BASE_ADDR ARM_VERSATILE_I2C_40023000_BASE_ADDRESS #define I2C_SBCON_1_NAME ARM_VERSATILE_I2C_40023000_LABEL -#define I2C_SBCON_2_BASE_ADDR ARM_VERSATILE_I2C_40029000_BASE_ADDRESS_0 +#define I2C_SBCON_2_BASE_ADDR ARM_VERSATILE_I2C_40029000_BASE_ADDRESS #define I2C_SBCON_2_NAME ARM_VERSATILE_I2C_40029000_LABEL -#define I2C_SBCON_3_BASE_ADDR ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS_0 +#define I2C_SBCON_3_BASE_ADDR ARM_VERSATILE_I2C_4002A000_BASE_ADDRESS #define I2C_SBCON_3_NAME ARM_VERSATILE_I2C_4002A000_LABEL /* End of SoC Level DTS fixup file */ diff --git a/boards/arm/nrf52_pca20020/dts.fixup b/boards/arm/nrf52_pca20020/dts.fixup index 1e19b85dd86..2c413052650 100644 --- a/boards/arm/nrf52_pca20020/dts.fixup +++ b/boards/arm/nrf52_pca20020/dts.fixup @@ -4,12 +4,12 @@ #define CONFIG_HTS221_NAME NORDIC_NRF5_I2C_40003000_ST_HTS221_5F_LABEL #define CONFIG_HTS221_I2C_MASTER_DEV_NAME NORDIC_NRF5_I2C_40003000_ST_HTS221_5F_BUS_NAME -#define CONFIG_HTS221_I2C_ADDR NORDIC_NRF5_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS_0 +#define CONFIG_HTS221_I2C_ADDR NORDIC_NRF5_I2C_40003000_ST_HTS221_5F_BASE_ADDRESS #define CONFIG_CCS811_NAME NORDIC_NRF5_I2C_40003000_AMS_CCS811_5A_LABEL #define CONFIG_CCS811_I2C_MASTER_DEV_NAME NORDIC_NRF5_I2C_40003000_AMS_CCS811_5A_BUS_NAME -#define CONFIG_CCS811_I2C_ADDR NORDIC_NRF5_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS_0 +#define CONFIG_CCS811_I2C_ADDR NORDIC_NRF5_I2C_40003000_AMS_CCS811_5A_BASE_ADDRESS #define CONFIG_LPS22HB_DEV_NAME NORDIC_NRF5_I2C_40003000_ST_LPS22HB_PRESS_5C_LABEL #define CONFIG_LPS22HB_I2C_MASTER_DEV_NAME NORDIC_NRF5_I2C_40003000_ST_LPS22HB_PRESS_5C_BUS_NAME -#define CONFIG_LPS22HB_I2C_ADDR NORDIC_NRF5_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS_0 +#define CONFIG_LPS22HB_I2C_ADDR NORDIC_NRF5_I2C_40003000_ST_LPS22HB_PRESS_5C_BASE_ADDRESS diff --git a/scripts/dts/extract_dts_includes.py b/scripts/dts/extract_dts_includes.py index 37a47f140bf..f5f2015fc72 100755 --- a/scripts/dts/extract_dts_includes.py +++ b/scripts/dts/extract_dts_includes.py @@ -144,7 +144,12 @@ def extract_reg_prop(node_address, names, defs, def_label, div, post_label): prop_alias = {} addr = 0 size = 0 - l_idx = [str(index)] + # Check is defined should be indexed (_0, _1) + if index == 0 and len(props) < 3: + # 1 element (len 2) or no element (len 0) in props + l_idx = [] + else: + l_idx = [str(index)] try: name = [names.pop(0).upper()] @@ -168,12 +173,6 @@ def extract_reg_prop(node_address, names, defs, def_label, div, post_label): if size_cells: prop_alias['_'.join(l_base + name + l_size)] = l_size_fqn - if index == 0: - if address_cells: - prop_alias['_'.join(l_base + l_addr)] = l_addr_fqn - if size_cells: - prop_alias['_'.join(l_base + l_size)] = l_size_fqn - # generate defs for node aliases if node_address in aliases: for i in aliases[node_address]: @@ -250,36 +249,44 @@ def extract_cells(node_address, yaml, prop, names, index, prefix, defs, except: name = [] + # Get number of cells per element of current property + for k in reduced[cell_parent]['props'].keys(): + if k[0] == '#' and '-cells' in k: + num_cells = reduced[cell_parent]['props'].get(k) + + # Generate label for each field of the property element l_cell = [str(cell_yaml.get('cell_string', ''))] l_base = def_label.split('/') l_base += prefix - l_idx = [str(index)] + # Check if #define should be indexed (_0, _1, ...) + if index == 0 and len(props) < (num_cells + 2): + # Less than 2 elements in prop_values (ie len < num_cells + phandle + 1) + # Indexing is not needed + l_idx = [] + else: + l_idx = [str(index)] prop_def = {} prop_alias = {} - for k in reduced[cell_parent]['props'].keys(): - if k[0] == '#' and '-cells' in k: - for i in range(reduced[cell_parent]['props'].get(k)): - l_cellname = [str(cell_yaml['#cells'][i]).upper()] - if l_cell == l_cellname: - label = l_base + l_cell + l_idx - else: - label = l_base + l_cell + l_cellname + l_idx - label_name = l_base + name + l_cellname - prop_def['_'.join(label)] = props.pop(0) - if len(name): - prop_alias['_'.join(label_name)] = '_'.join(label) + # Generate label for each field of the property element + for i in range(num_cells): + l_cellname = [str(cell_yaml['#cells'][i]).upper()] + if l_cell == l_cellname: + label = l_base + l_cell + l_idx + else: + label = l_base + l_cell + l_cellname + l_idx + label_name = l_base + name + l_cellname + prop_def['_'.join(label)] = props.pop(0) + if len(name): + prop_alias['_'.join(label_name)] = '_'.join(label) - if index == 0: - prop_alias['_'.join(label[:-1])] = '_'.join(label) - - # generate defs for node aliases - if node_address in aliases: - for i in aliases[node_address]: - alias_label = convert_string_to_label(i) - alias = [alias_label] + label[1:-1] - prop_alias['_'.join(alias)] = '_'.join(label[:-1]) + # generate defs for node aliases + if node_address in aliases: + for i in aliases[node_address]: + alias_label = convert_string_to_label(i) + alias = [alias_label] + label[1:-1] + prop_alias['_'.join(alias)] = '_'.join(label[:-1]) insert_defs(node_address, defs, prop_def, prop_alias)