diff --git a/drivers/dai/intel/ssp/ssp.c b/drivers/dai/intel/ssp/ssp.c
index 215f9912d57..a7e83f7a07f 100644
--- a/drivers/dai/intel/ssp/ssp.c
+++ b/drivers/dai/intel/ssp/ssp.c
@@ -74,11 +74,11 @@ static struct dai_intel_ssp_mn ssp_mn_divider = {
 		.irq = DT_NUM_IRQS(node_id),				\
 		.irq_name = irq_name_level5_z,				\
 		.fifo[DAI_DIR_PLAYBACK].offset =			\
-			DT_REG_ADDR_BY_IDX(node_id, 0) + SSDR,		\
+			DT_REG_ADDR_BY_IDX(node_id, 0) + OUT_FIFO,		\
 		.fifo[DAI_DIR_PLAYBACK].handshake =			\
 			DT_DMAS_CELL_BY_NAME(node_id, tx, channel),	\
 		.fifo[DAI_DIR_CAPTURE].offset =				\
-			DT_REG_ADDR_BY_IDX(node_id, 0) + SSDR,		\
+			DT_REG_ADDR_BY_IDX(node_id, 0) + IN_FIFO,		\
 		.fifo[DAI_DIR_CAPTURE].handshake =			\
 			DT_DMAS_CELL_BY_NAME(node_id, rx, channel),	\
 		.mn_inst = &ssp_mn_divider,				\
@@ -817,7 +817,7 @@ static void dai_ssp_pm_runtime_en_ssp_power(struct dai_intel_ssp *dp, uint32_t s
 	ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
 					      I2SLCTL_CPA(ssp_index), I2SLCTL_CPA(ssp_index),
 					      DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
-#elif CONFIG_SOC_INTEL_ACE20_LNL
+#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
 	sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) |
 			       I2SLCTL_SPA(ssp_index),
 			       dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
@@ -851,7 +851,8 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
 	ret = dai_ssp_poll_for_register_delay(dai_ip_base(dp) + I2SLCTL_OFFSET,
 					      I2SLCTL_CPA(ssp_index), 0,
 					      DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
-#elif CONFIG_SOC_INTEL_ACE20_LNL
+
+#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
 	sys_write32(sys_read32(dai_hdamlssp_base(dp) + I2SLCTL_OFFSET) & (~I2SLCTL_SPA(ssp_index)),
 			dai_hdamlssp_base(dp) + I2SLCTL_OFFSET);
 
@@ -874,7 +875,7 @@ static void dai_ssp_pm_runtime_dis_ssp_power(struct dai_intel_ssp *dp, uint32_t
 static void dai_ssp_program_channel_map(struct dai_intel_ssp *dp,
 		const struct dai_config *cfg, uint32_t ssp_index)
 {
-#ifdef CONFIG_SOC_INTEL_ACE20_LNL
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
 	uint16_t pcmsycm = cfg->link_config;
 	 /* Set upper slot number from configuration */
 	pcmsycm = pcmsycm | (dp->ssp_plat_data->params.tdm_slots - 1) << 4;
@@ -905,11 +906,21 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
 	 * SSSR_TNF is cleared when TX FIFO is empty or full,
 	 * so wait for set TNF then for TFL zero - order matter.
 	 */
+#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+	ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(0),
+							SSMODyCS_TNF, SSMODyCS_TNF,
+							DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
+
+	ret |= dai_ssp_poll_for_register_delay(dai_base(dp) + SSMODyCS(0), SSMODyCS_TFL, 0,
+					       DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE *
+					       (DAI_INTEL_SSP_FIFO_DEPTH - 1) / 2);
+#else
 	ret = dai_ssp_poll_for_register_delay(dai_base(dp) + SSSR, SSSR_TNF, SSSR_TNF,
 					      DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE);
 	ret |= dai_ssp_poll_for_register_delay(dai_base(dp) + SSCR3, SSCR3_TFL_MASK, 0,
 					       DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE *
 					       (DAI_INTEL_SSP_FIFO_DEPTH - 1) / 2);
+#endif
 
 	if (ret) {
 		LOG_WRN("timeout");
@@ -923,6 +934,81 @@ static void dai_ssp_empty_tx_fifo(struct dai_intel_ssp *dp)
 	}
 }
 
+#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
+{
+	uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
+	uint32_t i, sssr;
+
+	sssr = sys_read32(dai_base(dp) + SSSR);
+
+	if (sssr & SSSR_ROR) {
+		/* The RX FIFO is in overflow condition, empty it */
+		for (i = 0; i < DAI_INTEL_SSP_FIFO_DEPTH; i++)
+			sys_read32(dai_base(dp) + SSMIDyD(0));
+
+		/* Clear the overflow status */
+		dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
+		/* Re-read the SSSR register */
+		sssr = sys_read32(dai_base(dp) + SSSR);
+	}
+
+	while ((sys_read32(dai_base(dp) + SSMIDyCS(0)) & SSMIDyCS_RNE) && retry--) {
+		uint32_t entries = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) + SSMIDyCS(0)));
+
+		/* Empty the RX FIFO (the DMA is not running at this point) */
+		for (i = 0; i < entries + 1; i++)
+			sys_read32(dai_base(dp) + SSMIDyD(0));
+
+		sssr = sys_read32(dai_base(dp) + SSSR);
+	}
+}
+
+static void ssp_empty_rx_fifo_on_stop(struct dai_intel_ssp *dp)
+{
+	struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
+	uint64_t sample_ticks = ssp_plat_data->params.fsync_rate ?
+		1000000 / ssp_plat_data->params.fsync_rate : 0;
+
+	uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
+	uint32_t i, sssr, ssmidycs;
+	uint32_t entries[2];
+
+	sssr = sys_read32(dai_base(dp) + SSSR);
+	entries[0] = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) + SSMIDyCS(0)));
+
+	while ((sys_read32(dai_base(dp) + SSMIDyCS(0)) & SSMIDyCS_RNE) && retry--) {
+		/* Wait one sample time */
+		k_busy_wait(sample_ticks);
+
+		entries[1] = SSMIDyCS_RFL_VAL(sys_read32(dai_base(dp) + SSMIDyCS(0)));
+		sssr = sys_read32(dai_base(dp) + SSSR);
+		ssmidycs = sys_read32(dai_base(dp) + SSMIDyCS(0));
+
+		if (entries[0] > entries[1]) {
+			/*
+			 * The DMA is reading the FIFO, check the status in the
+			 * next loop
+			 */
+			entries[0] = entries[1];
+		} else if (!(ssmidycs & SSMIDyCS_RFS)) {
+			/*
+			 * The DMA request is not asserted, read the FIFO
+			 * directly, otherwise let the next loop iteration to
+			 * check the status
+			 */
+			for (i = 0; i < entries[1] + 1; i++)
+				sys_read32(dai_base(dp) + SSMIDyD(0));
+		}
+
+		sssr = sys_read32(dai_base(dp) + SSSR);
+	}
+
+	/* Just in case clear the overflow status */
+	dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
+}
+
+#else
 static void ssp_empty_rx_fifo_on_start(struct dai_intel_ssp *dp)
 {
 	uint32_t retry = DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX;
@@ -994,21 +1080,20 @@ static void ssp_empty_rx_fifo_on_stop(struct dai_intel_ssp *dp)
 	dai_ssp_update_bits(dp, SSSR, SSSR_ROR, SSSR_ROR);
 }
 
+#endif
+
 static int dai_ssp_mclk_prepare_enable(struct dai_intel_ssp *dp)
 {
 	struct dai_intel_ssp_plat_data *ssp_plat_data = dai_get_plat_data(dp);
-	int ret = 0;
+	int ret;
 
 	if (ssp_plat_data->clk_active & SSP_CLK_MCLK_ACTIVE) {
 		return 0;
 	}
 
 	/* MCLK config */
-	if (ssp_plat_data->clk_active & SSP_CLK_MCLK_IS_NEEDED) {
-		ret = dai_ssp_mn_set_mclk(dp, ssp_plat_data->params.mclk_id,
-					  ssp_plat_data->params.mclk_rate);
-	}
-
+	ret = dai_ssp_mn_set_mclk(dp, ssp_plat_data->params.mclk_id,
+					ssp_plat_data->params.mclk_rate);
 	if (ret < 0) {
 		LOG_ERR("invalid mclk_rate = %d for mclk_id = %d", ssp_plat_data->params.mclk_rate,
 			ssp_plat_data->params.mclk_id);
@@ -1027,9 +1112,7 @@ static void dai_ssp_mclk_disable_unprepare(struct dai_intel_ssp *dp)
 		return;
 	}
 
-	if (ssp_plat_data->clk_active & SSP_CLK_MCLK_IS_NEEDED) {
-		dai_ssp_mn_release_mclk(dp, ssp_plat_data->params.mclk_id);
-	}
+	dai_ssp_mn_release_mclk(dp, ssp_plat_data->params.mclk_id);
 
 	ssp_plat_data->clk_active &= ~SSP_CLK_MCLK_ACTIVE;
 }
@@ -1049,10 +1132,6 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
 		return 0;
 	}
 
-	if (!(ssp_plat_data->clk_active & SSP_CLK_BCLK_IS_NEEDED)) {
-		goto out;
-	}
-
 	sscr0 = sys_read32(dai_base(dp) + SSCR0);
 
 #if CONFIG_INTEL_MN
@@ -1075,9 +1154,11 @@ static int dai_ssp_bclk_prepare_enable(struct dai_intel_ssp *dp)
 	mdiv = ft[DAI_INTEL_SSP_DEFAULT_IDX].freq / ssp_plat_data->params.bclk_rate;
 #endif
 
+#ifndef CONFIG_SOC_INTEL_ACE30_PTL
 	if (need_ecs) {
 		sscr0 |= SSCR0_ECS;
 	}
+#endif
 
 	/* clock divisor is SCR + 1 */
 	mdiv -= 1;
@@ -1112,9 +1193,7 @@ static void dai_ssp_bclk_disable_unprepare(struct dai_intel_ssp *dp)
 		return;
 	}
 #if CONFIG_INTEL_MN
-	if (ssp_plat_data->clk_active & SSP_CLK_BCLK_IS_NEEDED) {
-		dai_ssp_mn_release_bclk(dp, ssp_plat_data->ssp_index);
-	}
+	dai_ssp_mn_release_bclk(dp, ssp_plat_data->ssp_index);
 #endif
 	ssp_plat_data->clk_active &= ~SSP_CLK_BCLK_ACTIVE;
 }
@@ -1237,19 +1316,16 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
 		sscr1 |= SSCR1_SCLKDIR | SSCR1_SFRMDIR;
 		break;
 	case DAI_INTEL_IPC3_SSP_FMT_CBC_CFC:
-		ssp_plat_data->clk_active |= SSP_CLK_MCLK_IS_NEEDED | SSP_CLK_BCLK_IS_NEEDED;
 		sscr1 |= SSCR1_SCFR;
 		cfs = true;
 		break;
 	case DAI_INTEL_IPC3_SSP_FMT_CBP_CFC:
-		ssp_plat_data->clk_active |= SSP_CLK_MCLK_IS_NEEDED;
 		sscr1 |= SSCR1_SCLKDIR;
 		/* FIXME: this mode has not been tested */
 
 		cfs = true;
 		break;
 	case DAI_INTEL_IPC3_SSP_FMT_CBC_CFP:
-		ssp_plat_data->clk_active |= SSP_CLK_MCLK_IS_NEEDED | SSP_CLK_BCLK_IS_NEEDED;
 		sscr1 |= SSCR1_SCFR | SSCR1_SFRMDIR;
 		/* FIXME: this mode has not been tested */
 		break;
@@ -1611,8 +1687,13 @@ static int dai_ssp_set_config_tplg(struct dai_intel_ssp *dp, const struct dai_co
 	sys_write32(sspsp2, dai_base(dp) + SSPSP2);
 	sys_write32(ssioc, dai_base(dp) + SSIOC);
 	sys_write32(ssto, dai_base(dp) + SSTO);
+#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+	sys_write64((uint64_t)sstsa, dai_base(dp) + SSMODyTSA(0));
+	sys_write64((uint64_t)ssrsa, dai_base(dp) + SSMIDyTSA(0));
+#else
 	sys_write32(sstsa, dai_base(dp) + SSTSA);
 	sys_write32(ssrsa, dai_base(dp) + SSRSA);
+#endif
 
 	LOG_INF("sscr0 = 0x%08x, sscr1 = 0x%08x, ssto = 0x%08x, sspsp = 0x%0x",
 		sscr0, sscr1, ssto, sspsp);
@@ -1825,7 +1906,7 @@ static int dai_ssp_parse_aux_data(struct dai_intel_ssp *dp, const void *spec_con
 			sys_write32(sys_read32(dai_ip_base(dp) + I2SLCTL_OFFSET) |
 				    I2CLCTL_MLCS(link->clock_source), dai_ip_base(dp) +
 				    I2SLCTL_OFFSET);
-#elif CONFIG_SOC_INTEL_ACE20_LNL
+#elif CONFIG_SOC_INTEL_ACE20_LNL || CONFIG_SOC_INTEL_ACE30_PTL
 			sys_write32(sys_read32(dai_i2svss_base(dp) + I2SLCTL_OFFSET) |
 				    I2CLCTL_MLCS(link->clock_source), dai_i2svss_base(dp) +
 				    I2SLCTL_OFFSET);
@@ -1876,14 +1957,20 @@ static int dai_ssp_set_clock_control_ver_1(struct dai_intel_ssp *dp,
 static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_config *cfg,
 				   const struct dai_intel_ipc4_ssp_config *regs)
 {
-	uint32_t ssc0, sstsa, ssrsa, sscr1;
+	uint32_t ssc0, sstsa, ssrsa;
+	uint32_t sscr1 = regs->ssc1;
+#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+	sscr1 = regs->ssc1 & ~(SSCR1_RSVD21);
+#else
+	sscr1 = regs->ssc1 & ~(SSCR1_RSRE | SSCR1_TSRE);
+#endif
 
 	ssc0 = regs->ssc0;
 	sstsa = SSTSA_GET(regs->sstsa);
 	ssrsa = SSRSA_GET(regs->ssrsa);
-	sscr1 = regs->ssc1 & ~(SSCR1_RSRE | SSCR1_TSRE);
 
 	LOG_INF("SSP%d configuration:", dp->dai_index);
+#ifndef CONFIG_SOC_INTEL_ACE30_PTL
 	if (regs->sstsa & SSTSA_TXEN || regs->ssrsa & SSRSA_RXEN ||
 	    regs->ssc1 & (SSCR1_RSRE | SSCR1_TSRE)) {
 		LOG_INF(" Ignoring %s%s%s%sfrom blob",
@@ -1892,6 +1979,7 @@ static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_co
 			regs->ssc1 & SSCR1_TSRE ? "SSCR1:TSRE " : "",
 			regs->ssc1 & SSCR1_RSRE ? "SSCR1:RSRE " : "");
 	}
+#endif
 
 	sys_write32(ssc0, dai_base(dp) + SSCR0);
 	sys_write32(regs->ssc2 & ~SSCR2_SFRMEN, dai_base(dp) + SSCR2); /* hardware specific flow */
@@ -1903,8 +1991,13 @@ static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_co
 	sys_write32(regs->sspsp2, dai_base(dp) + SSPSP2);
 	sys_write32(regs->ssioc, dai_base(dp) + SSIOC);
 	sys_write32(regs->sscto, dai_base(dp) + SSTO);
+#ifdef CONFIG_SOC_INTEL_ACE30_PTL
+	sys_write64((uint64_t)sstsa, dai_base(dp) + SSMODyTSA(0));
+	sys_write64((uint64_t)ssrsa, dai_base(dp) + SSMIDyTSA(0));
+#else
 	sys_write32(sstsa, dai_base(dp) + SSTSA);
 	sys_write32(ssrsa, dai_base(dp) + SSRSA);
+#endif
 
 	LOG_INF(" sscr0 = 0x%08x, sscr1 = 0x%08x, ssto = 0x%08x, sspsp = 0x%0x",
 		ssc0, sscr1, regs->sscto, regs->sspsp);
@@ -1923,15 +2016,6 @@ static void dai_ssp_set_reg_config(struct dai_intel_ssp *dp, const struct dai_co
 	dp->ssp_plat_data->params.rx_slots = SSRSA_GET(ssrsa);
 	dp->ssp_plat_data->params.fsync_rate = cfg->rate;
 
-	/* MCLK is needed if SSP is FS and/or BCLK provider */
-	if (!(regs->ssc1 & (SSCR1_SCLKDIR | SSCR1_SFRMDIR))) {
-		dp->ssp_plat_data->clk_active |= SSP_CLK_MCLK_IS_NEEDED;
-		/* BCLK is only needed if SSP is BCLK provider */
-		if (!(regs->ssc1 & SSCR1_SCLKDIR)) {
-			dp->ssp_plat_data->clk_active |= SSP_CLK_BCLK_IS_NEEDED;
-		}
-	}
-
 	dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
 	dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
 }
@@ -1956,19 +2040,14 @@ static int dai_ssp_set_config_blob(struct dai_intel_ssp *dp, const struct dai_co
 		if (err)
 			return err;
 		dai_ssp_set_reg_config(dp, cfg, &blob15->i2s_ssp_config);
-		if (ssp_plat_data->clk_active & SSP_CLK_MCLK_IS_NEEDED) {
-			err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
-			if (err)
-				return err;
-		}
+		err = dai_ssp_set_clock_control_ver_1_5(dp, &blob15->i2s_mclk_control);
+		if (err)
+			return err;
 	} else {
 		dai_ssp_set_reg_config(dp, cfg, &blob->i2s_driver_config.i2s_config);
-		if (ssp_plat_data->clk_active & SSP_CLK_MCLK_IS_NEEDED) {
-			err = dai_ssp_set_clock_control_ver_1(dp,
-							      &blob->i2s_driver_config.mclk_config);
-			if (err)
-				return err;
-		}
+		err = dai_ssp_set_clock_control_ver_1(dp, &blob->i2s_driver_config.mclk_config);
+		if (err)
+			return err;
 	}
 
 	ssp_plat_data->clk_active |= SSP_CLK_MCLK_ES_REQ;
@@ -2070,6 +2149,15 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
 
 
 	/* enable DMA */
+#if CONFIG_SOC_INTEL_ACE30_PTL
+	if (direction == DAI_DIR_PLAYBACK) {
+		dai_ssp_update_bits(dp, SSMODyCS(0), SSMODyCS_TSRE, SSMODyCS_TSRE);
+		dai_ssp_update_bits(dp, SSMODyCS(0), SSMODyCS_TXEN, SSMODyCS_TXEN);
+	} else {
+		dai_ssp_update_bits(dp, SSMIDyCS(0), SSMIDyCS_RSRE, SSMIDyCS_RSRE);
+		dai_ssp_update_bits(dp, SSMIDyCS(0), SSMIDyCS_RXEN, SSMIDyCS_RXEN);
+	}
+#else
 	if (direction == DAI_DIR_PLAYBACK) {
 		LOG_INF("SSP%d TX", dp->dai_index);
 		dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, SSCR1_TSRE);
@@ -2079,6 +2167,7 @@ static void dai_ssp_start(struct dai_intel_ssp *dp, int direction)
 		dai_ssp_update_bits(dp, SSCR1, SSCR1_RSRE, SSCR1_RSRE);
 		dai_ssp_update_bits(dp, SSRSA, SSRSA_RXEN, SSRSA_RXEN);
 	}
+#endif
 
 	dp->state[direction] = DAI_STATE_RUNNING;
 	ssp_acquire_port(dp->ssp_plat_data);
@@ -2128,8 +2217,13 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
 	if (direction == DAI_DIR_CAPTURE &&
 	    dp->state[DAI_DIR_CAPTURE] != DAI_STATE_PRE_RUNNING) {
 		LOG_INF("SSP%d RX", dp->dai_index);
+#if CONFIG_SOC_INTEL_ACE30_PTL
+		dai_ssp_update_bits(dp, SSMIDyCS(0), SSMIDyCS_RXEN, 0);
+		dai_ssp_update_bits(dp, SSMIDyCS(0), SSMIDyCS_RSRE, 0);
+#else
 		dai_ssp_update_bits(dp, SSRSA, SSRSA_RXEN, 0);
 		dai_ssp_update_bits(dp, SSCR1, SSCR1_RSRE, 0);
+#endif
 		ssp_empty_rx_fifo_on_stop(dp);
 		dp->state[DAI_DIR_CAPTURE] = DAI_STATE_PRE_RUNNING;
 		ssp_release_port(ssp_plat_data);
@@ -2139,9 +2233,15 @@ static void dai_ssp_stop(struct dai_intel_ssp *dp, int direction)
 	if (direction == DAI_DIR_PLAYBACK &&
 	    dp->state[DAI_DIR_PLAYBACK] != DAI_STATE_PRE_RUNNING) {
 		LOG_INF("SSP%d TX", dp->dai_index);
+#if CONFIG_SOC_INTEL_ACE30_PTL
+		dai_ssp_update_bits(dp, SSMODyCS(0), SSMODyCS_TSRE, 0);
+		dai_ssp_empty_tx_fifo(dp);
+		dai_ssp_update_bits(dp, SSMODyCS(0), SSMODyCS_TXEN, 0);
+#else
 		dai_ssp_update_bits(dp, SSCR1, SSCR1_TSRE, 0);
 		dai_ssp_empty_tx_fifo(dp);
 		dai_ssp_update_bits(dp, SSTSA, SSTSA_TXEN, 0);
+#endif
 		dp->state[DAI_DIR_PLAYBACK] = DAI_STATE_PRE_RUNNING;
 		ssp_release_port(ssp_plat_data);
 	}
diff --git a/drivers/dai/intel/ssp/ssp.h b/drivers/dai/intel/ssp/ssp.h
index 8c3e248a0d9..877ff75e532 100644
--- a/drivers/dai/intel/ssp/ssp.h
+++ b/drivers/dai/intel/ssp/ssp.h
@@ -48,234 +48,16 @@
 #define DAI_INTEL_SSP_CLOCK_AUDIO_CARDINAL	0x1
 #define DAI_INTEL_SSP_CLOCK_PLL_FIXED		0x2
 
-/* SSP register offsets */
-#define SSCR0			0x00
-#define SSCR1			0x04
-#define SSSR			0x08
-#define SSITR			0x0C
-#define SSDR			0x10
-#define SSTO			0x28
-#define SSPSP			0x2C
-#define SSTSA			0x30
-#define SSRSA			0x34
-#define SSTSS			0x38
-#define SSCR2			0x40
-
-/* SSCR0 bits */
-#define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
-#define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
-#define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
-#define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
-#define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
-#define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
-#define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
-#define SSCR0_ECS		BIT(6)
-#define SSCR0_SSE		BIT(7)
-#define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
-#define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
-#define SSCR0_EDSS		BIT(20)
-#define SSCR0_NCS		BIT(21)
-#define SSCR0_RIM		BIT(22)
-#define SSCR0_TIM		BIT(23)
-#define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
-#define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
-#define SSCR0_ACS		BIT(30)
-#define SSCR0_MOD		BIT(31)
-
-/* SSCR1 bits */
-#define SSCR1_RIE		BIT(0)
-#define SSCR1_TIE		BIT(1)
-#define SSCR1_LBM		BIT(2)
-#define SSCR1_SPO		BIT(3)
-#define SSCR1_SPH		BIT(4)
-#define SSCR1_MWDS		BIT(5)
-#define SSCR1_TFT_MASK		DAI_INTEL_SSP_MASK(9, 6)
-#define SSCR1_TFT(x)		DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
-#define SSCR1_RFT_MASK		DAI_INTEL_SSP_MASK(13, 10)
-#define SSCR1_RFT(x)		DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
-#define SSCR1_EFWR		BIT(14)
-#define SSCR1_STRF		BIT(15)
-#define SSCR1_IFS		BIT(16)
-#define SSCR1_PINTE		BIT(18)
-#define SSCR1_TINTE		BIT(19)
-#define SSCR1_RSRE		BIT(20)
-#define SSCR1_TSRE		BIT(21)
-#define SSCR1_TRAIL		BIT(22)
-#define SSCR1_RWOT		BIT(23)
-#define SSCR1_SFRMDIR		BIT(24)
-#define SSCR1_SCLKDIR		BIT(25)
-#define SSCR1_ECRB		BIT(26)
-#define SSCR1_ECRA		BIT(27)
-#define SSCR1_SCFR		BIT(28)
-#define SSCR1_EBCEI		BIT(29)
-#define SSCR1_TTE		BIT(30)
-#define SSCR1_TTELP		BIT(31)
-
-#define SSCR2_TURM1		BIT(1)
-#define SSCR2_PSPSRWFDFD	BIT(3)
-#define SSCR2_PSPSTWFDFD	BIT(4)
-#define SSCR2_SDFD		BIT(14)
-#define SSCR2_SDPM		BIT(16)
-#define SSCR2_LJDFD		BIT(17)
-#define SSCR2_MMRATF		BIT(18)
-#define SSCR2_SMTATF		BIT(19)
-#define SSCR2_SFRMEN		BIT(20)
-#define SSCR2_ACIOLBS		BIT(21)
-
-/* SSR bits */
-#define SSSR_TNF		BIT(2)
-#define SSSR_RNE		BIT(3)
-#define SSSR_BSY		BIT(4)
-#define SSSR_TFS		BIT(5)
-#define SSSR_RFS		BIT(6)
-#define SSSR_ROR		BIT(7)
-#define SSSR_TUR		BIT(21)
-
-/* SSPSP bits */
-#define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
-#define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
-#define SSPSP_ETDS		BIT(3)
-#define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
-#define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
-#define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
-#define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
-#define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
-#define SSPSP_DMYSTOP_BITS	2
-#define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
-#define SSPSP_FSRT		BIT(25)
-#define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
-
-#define SSPSP2			0x44
-#define SSPSP2_FEP_MASK		0xff
-
-#define SSCR3			0x48
-#define SSIOC			0x4C
-#define SSP_REG_MAX		SSIOC
-
-/* SSTSA bits */
-#define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
-#define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
-#define SSTSA_TXEN		BIT(8)
-
-/* SSRSA bits */
-#define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
-#define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
-#define SSRSA_RXEN		BIT(8)
-
-/* SSCR3 bits */
-#define SSCR3_FRM_MST_EN	BIT(0)
-#define SSCR3_I2S_MODE_EN	BIT(1)
-#define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
-#define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
-#define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
-#define SSCR3_I2S_TX_EN		BIT(9)
-#define SSCR3_I2S_RX_EN		BIT(10)
-#define SSCR3_CLK_EDGE_SEL	BIT(12)
-#define SSCR3_STRETCH_TX	BIT(14)
-#define SSCR3_STRETCH_RX	BIT(15)
-#define SSCR3_MST_CLK_EN	BIT(16)
-#define SSCR3_SYN_FIX_EN	BIT(17)
-
-/* SSCR4 bits */
-#define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
-
-/* SSCR5 bits */
-#define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
-#define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
-
-/* SFIFOTT bits */
-#define SFIFOTT_TX(x)		((x) - 1)
-#define SFIFOTT_RX(x)		(((x) - 1) << 16)
-
-/* SFIFOL bits */
-#define SFIFOL_TFL(x)		((x) & 0xFFFF)
-#define SFIFOL_RFL(x)		((x) >> 16)
-
-#define SSTSA_TSEN			BIT(8)
-#define SSRSA_RSEN			BIT(8)
-
-#define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
-#define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
-#define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
-#define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
-#define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
-#define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
-
-#define SSIOC_TXDPDEB	BIT(1)
-#define SSIOC_SFCR	BIT(4)
-#define SSIOC_SCOE	BIT(5)
-
-/* For 8000 Hz rate one sample is transmitted within 125us */
-#define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
-
-/* SSP flush retry counts maximum */
-#define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
-
-#define SSP_CLK_MCLK_IS_NEEDED	BIT(0)
-#define SSP_CLK_MCLK_ES_REQ	BIT(1)
-#define SSP_CLK_MCLK_ACTIVE	BIT(2)
-#define SSP_CLK_BCLK_IS_NEEDED	BIT(3)
-#define SSP_CLK_BCLK_ES_REQ	BIT(4)
-#define SSP_CLK_BCLK_ACTIVE	BIT(5)
-
-#define I2SLCTL_OFFSET		0x04
-
 #if defined(CONFIG_SOC_INTEL_ACE15_MTPM) || defined(CONFIG_SOC_SERIES_INTEL_ADSP_CAVS)
-#define I2SLCTL_SPA(x)		BIT(0 + x)
-#define I2SLCTL_CPA(x)		BIT(8 + x)
+#include "ssp_regs_v1.h"
 #elif defined(CONFIG_SOC_INTEL_ACE20_LNL)
-#define I2SLCTL_OFLEN		BIT(4)
-#define I2SLCTL_SPA(x)		BIT(16 + x)
-#define I2SLCTL_CPA(x)		BIT(23 + x)
-#define PCMS0CM_OFFSET		0x16
-#define PCMS1CM_OFFSET		0x1A
+#include "ssp_regs_v2.h"
+#elif defined(CONFIG_SOC_INTEL_ACE30_PTL)
+#include "ssp_regs_v3.h"
 #else
 #error "Missing ssp definitions"
 #endif
 
-#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
-#define SHIM_CLKCTL		0x78
-#define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
-#define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
-
-#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
-/** \brief Offset of MCLK Divider Control Register. */
-#define MN_MDIVCTRL 0x100
-
-/** \brief Offset of MCLK Divider x Ratio Register. */
-#define MN_MDIVR(x) (0x180 + (x) * 0x4)
-
-/** \brief Enables the output of MCLK Divider.
- *  On ACE+ there is a single divider for all MCLKs
- */
-#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(0)
-
-#else
-#define MN_MDIVCTRL 0x0
-#define MN_MDIVR(x) (0x80 + (x) * 0x4)
-
-/** \brief Enables the output of MCLK Divider.
- * Each MCLK divider can be enabled separately.
- */
-#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
-
-#endif
-
-/** \brief Bits for setting MCLK source clock. */
-#define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
-
-/** \brief Offset of BCLK x M/N Divider M Value Register. */
-#define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
-
-/** \brief Offset of BCLK x M/N Divider N Value Register. */
-#define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
-
-/** \brief Bits for setting M/N source clock. */
-#define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
-
-/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
-#define MN_SOURCE_CLKS_MASK 0x3
-
 #if CONFIG_INTEL_MN
 /** \brief BCLKs can be driven by multiple sources - M/N or XTAL directly.
  *	   Even in the case of M/N, the actual clock source can be XTAL,
@@ -334,7 +116,7 @@ struct dai_intel_ssp_plat_data {
 	uint32_t base;
 	uint32_t ip_base;
 	uint32_t shim_base;
-#ifdef CONFIG_SOC_INTEL_ACE20_LNL
+#if defined(CONFIG_SOC_INTEL_ACE20_LNL) || defined(CONFIG_SOC_INTEL_ACE30_PTL)
 	uint32_t hdamlssp_base;
 	uint32_t i2svss_base;
 #endif
diff --git a/drivers/dai/intel/ssp/ssp_regs_v1.h b/drivers/dai/intel/ssp/ssp_regs_v1.h
new file mode 100644
index 00000000000..a821ab8733a
--- /dev/null
+++ b/drivers/dai/intel/ssp/ssp_regs_v1.h
@@ -0,0 +1,252 @@
+/*
+ * Copyright (c) 2022 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DAI_DRIVER_SSP_REGSV1_H__
+#define __INTEL_DAI_DRIVER_SSP_REGSV1_H__
+
+/* SSP register offsets */
+#define SSCR0			0x00
+#define SSCR1			0x04
+#define SSSR			0x08
+#define SSITR			0x0C
+#define SSTO			0x28
+#define SSPSP			0x2C
+#define SSTSS			0x38
+#define SSCR2			0x40
+#define SSPSP2			0x44
+#define SSIOC			0x4C
+#define SSGFS			0x50
+#define SSDR			0x10 /* Not PTL */
+#define SSTSA			0x30 /* Not PTL */
+#define SSRSA			0x34 /* Not PTL */
+
+#define OUT_FIFO		SSDR
+#define IN_FIFO			SSDR
+
+/* SSCR0 bits */
+#define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
+#define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
+#define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
+#define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
+#define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
+#define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
+#define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
+#define SSCR0_ECS		BIT(6)
+#define SSCR0_SSE		BIT(7)
+#define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
+#define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
+#define SSCR0_EDSS		BIT(20)
+#define SSCR0_NCS		BIT(21)
+#define SSCR0_RIM		BIT(22)
+#define SSCR0_TIM		BIT(23)
+#define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
+#define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
+#define SSCR0_ACS		BIT(30)
+#define SSCR0_MOD		BIT(31)
+
+/* SSCR1 bits */
+#define SSCR1_RIE		BIT(0)
+#define SSCR1_TIE		BIT(1)
+#define SSCR1_LBM		BIT(2)
+#define SSCR1_SPO		BIT(3)
+#define SSCR1_SPH		BIT(4)
+#define SSCR1_MWDS		BIT(5)
+#define SSCR1_TFT_MASK		DAI_INTEL_SSP_MASK(9, 6)
+#define SSCR1_TFT(x)		DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
+#define SSCR1_RFT_MASK		DAI_INTEL_SSP_MASK(13, 10)
+#define SSCR1_RFT(x)		DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
+#define SSCR1_EFWR		BIT(14)
+#define SSCR1_STRF		BIT(15)
+#define SSCR1_IFS		BIT(16)
+#define SSCR1_PINTE		BIT(18)
+#define SSCR1_TINTE		BIT(19)
+#define SSCR1_RSRE		BIT(20)
+#define SSCR1_TSRE		BIT(21)
+#define SSCR1_TRAIL		BIT(22)
+#define SSCR1_RWOT		BIT(23)
+#define SSCR1_SFRMDIR		BIT(24)
+#define SSCR1_SCLKDIR		BIT(25)
+#define SSCR1_ECRB		BIT(26)
+#define SSCR1_ECRA		BIT(27)
+#define SSCR1_SCFR		BIT(28)
+#define SSCR1_EBCEI		BIT(29)
+#define SSCR1_TTE		BIT(30)
+#define SSCR1_TTELP		BIT(31)
+
+#define SSCR2_TURM1		BIT(1)
+#define SSCR2_PSPSRWFDFD	BIT(3)
+#define SSCR2_PSPSTWFDFD	BIT(4)
+#define SSCR2_SDFD		BIT(14)
+#define SSCR2_SDPM		BIT(16)
+#define SSCR2_LJDFD		BIT(17)
+#define SSCR2_MMRATF		BIT(18)
+#define SSCR2_SMTATF		BIT(19)
+#define SSCR2_SFRMEN		BIT(20)
+#define SSCR2_ACIOLBS		BIT(21)
+
+/* SSR bits */
+#define SSSR_TNF		BIT(2)
+#define SSSR_RNE		BIT(3)
+#define SSSR_BSY		BIT(4)
+#define SSSR_TFS		BIT(5)
+#define SSSR_RFS		BIT(6)
+#define SSSR_ROR		BIT(7)
+#define SSSR_TUR		BIT(21)
+
+/* SSPSP bits */
+#define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
+#define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSPSP_ETDS		BIT(3)
+#define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
+#define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
+#define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
+#define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
+#define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
+#define SSPSP_DMYSTOP_BITS	2
+#define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
+#define SSPSP_FSRT		BIT(25)
+#define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
+
+#define SSPSP2			0x44
+#define SSPSP2_FEP_MASK		0xff
+
+#define SSCR3			0x48
+#define SSIOC			0x4C
+#define SSP_REG_MAX		SSIOC
+
+/* SSTSA bits */
+#define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSTSA_TXEN		BIT(8)
+
+/* SSRSA bits */
+#define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSRSA_RXEN		BIT(8)
+
+/* SSCR3 bits */
+#define SSCR3_FRM_MST_EN	BIT(0)
+#define SSCR3_I2S_MODE_EN	BIT(1)
+#define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
+#define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
+#define SSCR3_I2S_TX_EN		BIT(9)
+#define SSCR3_I2S_RX_EN		BIT(10)
+#define SSCR3_CLK_EDGE_SEL	BIT(12)
+#define SSCR3_STRETCH_TX	BIT(14)
+#define SSCR3_STRETCH_RX	BIT(15)
+#define SSCR3_MST_CLK_EN	BIT(16)
+#define SSCR3_SYN_FIX_EN	BIT(17)
+
+/* SSCR4 bits */
+#define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
+
+/* SSCR5 bits */
+#define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
+#define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
+
+/* SFIFOTT bits */
+#define SFIFOTT_TX(x)		((x) - 1)
+#define SFIFOTT_RX(x)		(((x) - 1) << 16)
+
+/* SFIFOL bits */
+#define SFIFOL_TFL(x)		((x) & 0xFFFF)
+#define SFIFOL_RFL(x)		((x) >> 16)
+
+#define SSTSA_TSEN			BIT(8)
+#define SSRSA_RSEN			BIT(8)
+
+#define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
+#define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
+#define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
+#define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
+
+#define SSIOC_TXDPDEB	BIT(1)
+#define SSIOC_SFCR		BIT(4)
+#define SSIOC_SCOE		BIT(5)
+
+/* SSMIDyCS */
+#define SSMIDyCS_RXEN			BIT(0)
+#define SSMIDyCS_RSRE			BIT(1)
+#define SSMIDyCS_RFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMIDyCS_RNE			BIT(26)
+#define SSMIDyCS_RFS			BIT(27)
+#define SSMIDyCS_ROR			BIT(28)
+#define SSMIDyCS_PINT			BIT(29)
+#define SSMIDyCS_TINT			BIT(30)
+#define SSMIDyCS_EOC			BIT(31)
+
+/* SSMIDyTSA */
+#define SSMIDyTSA_RTSA			DAI_INTEL_SSP_MASK(63, 0)
+#define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* SSMODyCS */
+#define SSMODyCS_TXEN			BIT(0)
+#define SSMODyCS_TSRE			BIT(1)
+#define SSMODyCS_TFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMODyCS_TNF			BIT(26)
+#define SSMODyCS_TFS			BIT(27)
+#define SSMODyCS_TUR			BIT(28)
+
+/* SSMODyTSA */
+#define SSMODyTSA_TTSA		DAI_INTEL_SSP_MASK(63, 0)
+#define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* For 8000 Hz rate one sample is transmitted within 125us */
+#define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
+
+/* SSP flush retry counts maximum */
+#define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
+
+#define SSP_CLK_MCLK_ES_REQ	BIT(0)
+#define SSP_CLK_MCLK_ACTIVE	BIT(1)
+#define SSP_CLK_BCLK_ES_REQ	BIT(2)
+#define SSP_CLK_BCLK_ACTIVE	BIT(3)
+
+#define I2SLCTL_OFFSET		0x04
+
+#define I2SLCTL_SPA(x)		BIT(0 + x)
+#define I2SLCTL_CPA(x)		BIT(8 + x)
+
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define SHIM_CLKCTL		0x78
+#define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
+#define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
+
+#ifdef CONFIG_SOC_SERIES_INTEL_ADSP_ACE
+/** \brief Offset of MCLK Divider Control Register. */
+#define MN_MDIVCTRL 0x100
+
+/** \brief Offset of MCLK Divider x Ratio Register. */
+#define MN_MDIVR(x) (0x180 + (x) * 0x4)
+#else
+#define MN_MDIVCTRL 0x0
+#define MN_MDIVR(x) (0x80 + (x) * 0x4)
+#endif
+
+/** \brief Enables the output of MCLK Divider. */
+#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
+
+/** \brief Bits for setting MCLK source clock. */
+#define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
+
+/** \brief Offset of BCLK x M/N Divider M Value Register. */
+#define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
+
+/** \brief Offset of BCLK x M/N Divider N Value Register. */
+#define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
+
+/** \brief Bits for setting M/N source clock. */
+#define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
+
+/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
+#define MN_SOURCE_CLKS_MASK 0x3
+
+#endif /* __INTEL_DAI_DRIVER_SSP_REGSV1_H__ */
diff --git a/drivers/dai/intel/ssp/ssp_regs_v2.h b/drivers/dai/intel/ssp/ssp_regs_v2.h
new file mode 100644
index 00000000000..e2d1c826d07
--- /dev/null
+++ b/drivers/dai/intel/ssp/ssp_regs_v2.h
@@ -0,0 +1,250 @@
+/*
+ * Copyright (c) 2022 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DAI_DRIVER_SSP_REGSV2_H__
+#define __INTEL_DAI_DRIVER_SSP_REGSV2_H__
+
+/* SSP register offsets */
+#define SSCR0			0x00
+#define SSCR1			0x04
+#define SSSR			0x08
+#define SSITR			0x0C
+#define SSTO			0x28
+#define SSPSP			0x2C
+#define SSTSS			0x38
+#define SSCR2			0x40
+#define SSPSP2			0x44
+
+#define SSIOC			0x4C
+#define SSGFS			0x50
+#define SSDR			0x10 /* Not PTL */
+#define SSTSA			0x30 /* Not PTL */
+#define SSRSA			0x34 /* Not PTL */
+
+#define OUT_FIFO		SSDR
+#define IN_FIFO			SSDR
+
+/* SSCR0 bits */
+#define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
+#define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
+#define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
+#define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
+#define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
+#define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
+#define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
+#define SSCR0_ECS		BIT(6)
+#define SSCR0_SSE		BIT(7)
+#define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
+#define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
+#define SSCR0_EDSS		BIT(20)
+#define SSCR0_NCS		BIT(21)
+#define SSCR0_RIM		BIT(22)
+#define SSCR0_TIM		BIT(23)
+#define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
+#define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
+#define SSCR0_ACS		BIT(30)
+#define SSCR0_MOD		BIT(31)
+
+/* SSCR1 bits */
+#define SSCR1_RIE		BIT(0)
+#define SSCR1_TIE		BIT(1)
+#define SSCR1_LBM		BIT(2)
+#define SSCR1_SPO		BIT(3)
+#define SSCR1_SPH		BIT(4)
+#define SSCR1_MWDS		BIT(5)
+#define SSCR1_TFT_MASK		DAI_INTEL_SSP_MASK(9, 6)
+#define SSCR1_TFT(x)		DAI_INTEL_SSP_SET_BITS(9, 6, (x) - 1)
+#define SSCR1_RFT_MASK		DAI_INTEL_SSP_MASK(13, 10)
+#define SSCR1_RFT(x)		DAI_INTEL_SSP_SET_BITS(13, 10, (x) - 1)
+#define SSCR1_EFWR		BIT(14)
+#define SSCR1_STRF		BIT(15)
+#define SSCR1_IFS		BIT(16)
+#define SSCR1_PINTE		BIT(18)
+#define SSCR1_TINTE		BIT(19)
+#define SSCR1_RSRE		BIT(20)
+#define SSCR1_TSRE		BIT(21)
+#define SSCR1_TRAIL		BIT(22)
+#define SSCR1_RWOT		BIT(23)
+#define SSCR1_SFRMDIR		BIT(24)
+#define SSCR1_SCLKDIR		BIT(25)
+#define SSCR1_ECRB		BIT(26)
+#define SSCR1_ECRA		BIT(27)
+#define SSCR1_SCFR		BIT(28)
+#define SSCR1_EBCEI		BIT(29)
+#define SSCR1_TTE		BIT(30)
+#define SSCR1_TTELP		BIT(31)
+
+#define SSCR2_TURM1		BIT(1)
+#define SSCR2_PSPSRWFDFD	BIT(3)
+#define SSCR2_PSPSTWFDFD	BIT(4)
+#define SSCR2_SDFD		BIT(14)
+#define SSCR2_SDPM		BIT(16)
+#define SSCR2_LJDFD		BIT(17)
+#define SSCR2_MMRATF		BIT(18)
+#define SSCR2_SMTATF		BIT(19)
+#define SSCR2_SFRMEN		BIT(20)
+#define SSCR2_ACIOLBS		BIT(21)
+
+/* SSR bits */
+#define SSSR_TNF		BIT(2)
+#define SSSR_RNE		BIT(3)
+#define SSSR_BSY		BIT(4)
+#define SSSR_TFS		BIT(5)
+#define SSSR_RFS		BIT(6)
+#define SSSR_ROR		BIT(7)
+#define SSSR_TUR		BIT(21)
+
+/* SSPSP bits */
+#define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
+#define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSPSP_ETDS		BIT(3)
+#define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
+#define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
+#define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
+#define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
+#define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
+#define SSPSP_DMYSTOP_BITS	2
+#define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
+#define SSPSP_FSRT		BIT(25)
+#define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
+
+#define SSPSP2			0x44
+#define SSPSP2_FEP_MASK		0xff
+
+#define SSCR3			0x48
+#define SSIOC			0x4C
+#define SSP_REG_MAX		SSIOC
+
+/* SSTSA bits */
+#define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSTSA_TXEN		BIT(8)
+
+/* SSRSA bits */
+#define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSRSA_RXEN		BIT(8)
+
+/* SSCR3 bits */
+#define SSCR3_FRM_MST_EN	BIT(0)
+#define SSCR3_I2S_MODE_EN	BIT(1)
+#define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
+#define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
+#define SSCR3_I2S_TX_EN		BIT(9)
+#define SSCR3_I2S_RX_EN		BIT(10)
+#define SSCR3_CLK_EDGE_SEL	BIT(12)
+#define SSCR3_STRETCH_TX	BIT(14)
+#define SSCR3_STRETCH_RX	BIT(15)
+#define SSCR3_MST_CLK_EN	BIT(16)
+#define SSCR3_SYN_FIX_EN	BIT(17)
+
+/* SSCR4 bits */
+#define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
+
+/* SSCR5 bits */
+#define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
+#define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
+
+/* SFIFOTT bits */
+#define SFIFOTT_TX(x)		((x) - 1)
+#define SFIFOTT_RX(x)		(((x) - 1) << 16)
+
+/* SFIFOL bits */
+#define SFIFOL_TFL(x)		((x) & 0xFFFF)
+#define SFIFOL_RFL(x)		((x) >> 16)
+
+#define SSTSA_TSEN			BIT(8)
+#define SSRSA_RSEN			BIT(8)
+
+#define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
+#define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
+#define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
+#define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
+
+#define SSIOC_TXDPDEB	BIT(1)
+#define SSIOC_SFCR		BIT(4)
+#define SSIOC_SCOE		BIT(5)
+
+/* SSMIDyCS */
+#define SSMIDyCS_RXEN			BIT(0)
+#define SSMIDyCS_RSRE			BIT(1)
+#define SSMIDyCS_RFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMIDyCS_RNE			BIT(26)
+#define SSMIDyCS_RFS			BIT(27)
+#define SSMIDyCS_ROR			BIT(28)
+#define SSMIDyCS_PINT			BIT(29)
+#define SSMIDyCS_TINT			BIT(30)
+#define SSMIDyCS_EOC			BIT(31)
+
+/* SSMIDyTSA */
+#define SSMIDyTSA_RTSA			DAI_INTEL_SSP_MASK(63, 0)
+#define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* SSMODyCS */
+#define SSMODyCS_TXEN			BIT(0)
+#define SSMODyCS_TSRE			BIT(1)
+#define SSMODyCS_TFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMODyCS_TNF			BIT(26)
+#define SSMODyCS_TFS			BIT(27)
+#define SSMODyCS_TUR			BIT(28)
+
+/* SSMODyTSA */
+#define SSMODyTSA_TTSA		DAI_INTEL_SSP_MASK(63, 0)
+#define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* For 8000 Hz rate one sample is transmitted within 125us */
+#define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
+
+/* SSP flush retry counts maximum */
+#define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
+
+#define SSP_CLK_MCLK_ES_REQ	BIT(0)
+#define SSP_CLK_MCLK_ACTIVE	BIT(1)
+#define SSP_CLK_BCLK_ES_REQ	BIT(2)
+#define SSP_CLK_BCLK_ACTIVE	BIT(3)
+
+#define I2SLCTL_OFFSET		0x04
+#define I2SLCTL_OFLEN		BIT(4)
+#define I2SLCTL_SPA(x)		BIT(16 + x)
+#define I2SLCTL_CPA(x)		BIT(23 + x)
+#define PCMS0CM_OFFSET		0x16
+#define PCMS1CM_OFFSET		0x1A
+
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define SHIM_CLKCTL		0x78
+#define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
+#define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
+
+/** \brief Offset of MCLK Divider Control Register. */
+#define MN_MDIVCTRL 0x100
+
+/** \brief Offset of MCLK Divider x Ratio Register. */
+#define MN_MDIVR(x) (0x180 + (x) * 0x4)
+
+/** \brief Enables the output of MCLK Divider. */
+#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
+
+/** \brief Bits for setting MCLK source clock. */
+#define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
+
+/** \brief Offset of BCLK x M/N Divider M Value Register. */
+#define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
+
+/** \brief Offset of BCLK x M/N Divider N Value Register. */
+#define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
+
+/** \brief Bits for setting M/N source clock. */
+#define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
+
+/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
+#define MN_SOURCE_CLKS_MASK 0x3
+
+#endif /* __INTEL_DAI_DRIVER_SSP_REGSV2_H__ */
diff --git a/drivers/dai/intel/ssp/ssp_regs_v3.h b/drivers/dai/intel/ssp/ssp_regs_v3.h
new file mode 100644
index 00000000000..958c3919c60
--- /dev/null
+++ b/drivers/dai/intel/ssp/ssp_regs_v3.h
@@ -0,0 +1,246 @@
+/*
+ * Copyright (c) 2022 Intel Corporation.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef __INTEL_DAI_DRIVER_SSP_REGSV3_H__
+#define __INTEL_DAI_DRIVER_SSP_REGSV3_H__
+
+/* SSP register offsets */
+#define SSCR0			0x00
+#define SSCR1			0x04
+#define SSSR			0x08
+#define SSITR			0x0C
+#define SSTO			0x28
+#define SSPSP			0x2C
+#define SSTSS			0x38
+#define SSCR2			0x40
+#define SSPSP2			0x44
+
+#define SSIOC			0x4C
+#define SSGFS			0x50
+
+#define I2SIPCMC		8
+#define SSMIDyCS(y)		0x60 + 0x10*y
+#define SSMIDyD(y)		0x64 + 0x10*y
+#define SSMIDyTSA(y)	0x68 + 0x10*y
+#define SSMODyCS(y)		0x60 + 0x10*I2SIPCMC + 0x10*y
+#define SSMODyD(y)		0x64 + 0x10*I2SIPCMC + 0x10*y
+#define SSMODyTSA(y)	0x68 + 0x10*I2SIPCMC + 0x10*y
+
+#define OUT_FIFO		SSMODyD(0)
+#define IN_FIFO			SSMIDyD(0)
+
+/* SSCR0 bits */
+#define SSCR0_DSIZE(x)		DAI_INTEL_SSP_SET_BITS(3, 0, (x) - 1)
+#define SSCR0_DSIZE_GET(x)	(((x) & DAI_INTEL_SSP_MASK(3, 0)) + 1)
+#define SSCR0_FRF		DAI_INTEL_SSP_MASK(5, 4)
+#define SSCR0_MOT		DAI_INTEL_SSP_SET_BITS(5, 4, 0)
+#define SSCR0_TI		DAI_INTEL_SSP_SET_BITS(5, 4, 1)
+#define SSCR0_NAT		DAI_INTEL_SSP_SET_BITS(5, 4, 2)
+#define SSCR0_PSP		DAI_INTEL_SSP_SET_BITS(5, 4, 3)
+#define SSCR0_RSVD1		BIT(6)
+#define SSCR0_SSE		BIT(7)
+#define SSCR0_SCR_MASK		DAI_INTEL_SSP_MASK(19, 8)
+#define SSCR0_SCR(x)		DAI_INTEL_SSP_SET_BITS(19, 8, x)
+#define SSCR0_EDSS		BIT(20)
+#define SSCR0_RSVD2		BIT(21)
+#define SSCR0_RIM		BIT(22)
+#define SSCR0_TIM		BIT(23)
+#define SSCR0_FRDC(x)		DAI_INTEL_SSP_SET_BITS(26, 24, (x) - 1)
+#define SSCR0_FRDC_GET(x)	((((x) & DAI_INTEL_SSP_MASK(26, 24)) >> 24) + 1)
+#define SSCR0_EFRDC     BIT(27)
+#define SSCR0_EFRDC2    BIT(28)
+#define SSCR0_DLE		DAI_INTEL_SSP_SET_BITS(30, 29, 0)
+#define SSCR0_MOD		BIT(31)
+
+/* SSCR1 bits */
+#define SSCR1_RIE		BIT(0)
+#define SSCR1_TIE		BIT(1)
+#define SSCR1_LBM		BIT(2)
+#define SSCR1_RSVD1		DAI_INTEL_SSP_MASK(15, 3)
+#define SSCR1_IFS		BIT(16)
+#define SSCR1_PINTE		BIT(18)
+#define SSCR1_TINTE		BIT(19)
+#define SSCR1_RSVD21		DAI_INTEL_SSP_MASK(21, 20)
+#define SSCR1_TRAIL		BIT(22)
+#define SSCR1_RWOT		BIT(23)
+#define SSCR1_SFRMDIR		BIT(24)
+#define SSCR1_SCLKDIR		BIT(25)
+#define SSCR1_SCFR		BIT(28)
+#define SSCR1_EBCEI		BIT(29)
+#define SSCR1_TTE		BIT(30)
+#define SSCR1_TTELP		BIT(31)
+
+#define SSCR2_TURM1		BIT(1)
+#define SSCR2_PSPSRWFDFD	BIT(3)
+#define SSCR2_PSPSTWFDFD	BIT(4)
+#define SSCR2_SDFD		BIT(14)
+#define SSCR2_SDPM		BIT(16)
+#define SSCR2_LJDFD		BIT(17)
+#define SSCR2_MMRATF		BIT(18)
+#define SSCR2_SMTATF		BIT(19)
+#define SSCR2_SFRMEN		BIT(20)
+#define SSCR2_ACIOLBS		BIT(21)
+
+/* SSR bits */
+#define SSSR_BSY		BIT(4)
+#define SSSR_ROR		BIT(7)
+#define SSSR_TUR		BIT(21)
+
+/* SSPSP bits */
+#define SSPSP_SCMODE(x)		DAI_INTEL_SSP_SET_BITS(1, 0, x)
+#define SSPSP_SFRMP(x)		DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSPSP_STRTDLY(x)	DAI_INTEL_SSP_SET_BITS(6, 4, x)
+#define SSPSP_DMYSTRT(x)	DAI_INTEL_SSP_SET_BITS(8, 7, x)
+#define SSPSP_SFRMDLY(x)	DAI_INTEL_SSP_SET_BITS(15, 9, x)
+#define SSPSP_SFRMWDTH(x)	DAI_INTEL_SSP_SET_BITS(21, 16, x)
+#define SSPSP_DMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(24, 23, x)
+#define SSPSP_DMYSTOP_BITS	2
+#define SSPSP_DMYSTOP_MASK	DAI_INTEL_SSP_MASK(SSPSP_DMYSTOP_BITS - 1, 0)
+#define SSPSP_FSRT		BIT(25)
+#define SSPSP_EDMYSTOP(x)	DAI_INTEL_SSP_SET_BITS(28, 26, x)
+
+#define SSPSP2			0x44
+#define SSPSP2_FEP_MASK		0xff
+
+#define SSPSP2_RFAC		DAI_INTEL_SSP_MASK(9, 8)
+#define SSPSP2_TFAC		DAI_INTEL_SSP_MASK(11, 10)
+#define SSPSP2_EFEP		DAI_INTEL_SSP_MASK(13, 12)
+#define SSPSP2_ESFRMDW	DAI_INTEL_SSP_MASK(15, 14)
+
+
+#define SSCR3			0x48
+#define SSIOC			0x4C
+#define SSP_REG_MAX		SSIOC
+
+/* SSTSA bits */
+#define SSTSA_SSTSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSTSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+
+/* SSRSA bits */
+#define SSRSA_SSRSA(x)		DAI_INTEL_SSP_SET_BITS(7, 0, x)
+#define SSRSA_GET(x)		((x) & DAI_INTEL_SSP_MASK(7, 0))
+
+/* SSCR3 bits */
+#define SSCR3_FRM_MST_EN	BIT(0)
+#define SSCR3_I2S_MODE_EN	BIT(1)
+#define SSCR3_I2S_FRM_POL(x)	DAI_INTEL_SSP_SET_BIT(2, x)
+#define SSCR3_I2S_TX_SS_FIX_EN	BIT(3)
+#define SSCR3_I2S_RX_SS_FIX_EN	BIT(4)
+#define SSCR3_I2S_TX_EN		BIT(9)
+#define SSCR3_I2S_RX_EN		BIT(10)
+#define SSCR3_CLK_EDGE_SEL	BIT(12)
+#define SSCR3_STRETCH_TX	BIT(14)
+#define SSCR3_STRETCH_RX	BIT(15)
+#define SSCR3_MST_CLK_EN	BIT(16)
+#define SSCR3_SYN_FIX_EN	BIT(17)
+
+/* SSCR4 bits */
+#define SSCR4_TOT_FRM_PRD(x)	((x) << 7)
+
+/* SSCR5 bits */
+#define SSCR5_FRM_ASRT_CLOCKS(x)	(((x) - 1) << 1)
+#define SSCR5_FRM_POLARITY(x)	DAI_INTEL_SSP_SET_BIT(0, x)
+
+/* SFIFOTT bits */
+#define SFIFOTT_TX(x)		((x) - 1)
+#define SFIFOTT_RX(x)		(((x) - 1) << 16)
+
+/* SFIFOL bits */
+#define SFIFOL_TFL(x)		((x) & 0xFFFF)
+#define SFIFOL_RFL(x)		((x) >> 16)
+
+#define SSTSA_TSEN			BIT(8)
+#define SSRSA_RSEN			BIT(8)
+
+#define SSCR3_TFL_MASK	DAI_INTEL_SSP_MASK(5, 0)
+#define SSCR3_RFL_MASK	DAI_INTEL_SSP_MASK(13, 8)
+#define SSCR3_TFL_VAL(scr3_val)	(((scr3_val) >> 0) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_RFL_VAL(scr3_val)	(((scr3_val) >> 8) & DAI_INTEL_SSP_MASK(5, 0))
+#define SSCR3_TX(x)	DAI_INTEL_SSP_SET_BITS(21, 16, (x) - 1)
+#define SSCR3_RX(x)	DAI_INTEL_SSP_SET_BITS(29, 24, (x) - 1)
+
+#define SSIOC_TXDPDEB	BIT(1)
+#define SSIOC_SFCR		BIT(4)
+#define SSIOC_SCOE		BIT(5)
+
+/* SSMIDyCS */
+#define SSMIDyCS_RXEN			BIT(0)
+#define SSMIDyCS_RSRE			BIT(1)
+#define SSMIDyCS_RFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_RFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMIDyCS_RNE			BIT(26)
+#define SSMIDyCS_RFS			BIT(27)
+#define SSMIDyCS_ROR			BIT(28)
+#define SSMIDyCS_PINT			BIT(29)
+#define SSMIDyCS_TINT			BIT(30)
+#define SSMIDyCS_EOC			BIT(31)
+
+/* SSMIDyTSA */
+#define SSMIDyTSA_RTSA			DAI_INTEL_SSP_MASK(63, 0)
+#define SSMIDyTSA_SRTSA(x)		DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* SSMODyCS */
+#define SSMODyCS_TXEN			BIT(0)
+#define SSMODyCS_TSRE			BIT(1)
+#define SSMODyCS_TFL			DAI_INTEL_SSP_MASK(23, 16)
+#define SSMIDyCS_TFL_VAL(rfl_val) (((rfl_val) >> 16) & DAI_INTEL_SSP_MASK(7, 0))
+#define SSMODyCS_TNF			BIT(26)
+#define SSMODyCS_TFS			BIT(27)
+#define SSMODyCS_TUR			BIT(28)
+
+/* SSMODyTSA */
+#define SSMODyTSA_TTSA		DAI_INTEL_SSP_MASK(63, 0)
+#define SSMODyTSA_STTSA(x)	DAI_INTEL_SSP_MASK(63, 0, x)
+
+/* For 8000 Hz rate one sample is transmitted within 125us */
+#define DAI_INTEL_SSP_MAX_SEND_TIME_PER_SAMPLE 125
+
+/* SSP flush retry counts maximum */
+#define DAI_INTEL_SSP_RX_FLUSH_RETRY_MAX	16
+
+#define SSP_CLK_MCLK_ES_REQ	BIT(0)
+#define SSP_CLK_MCLK_ACTIVE	BIT(1)
+#define SSP_CLK_BCLK_ES_REQ	BIT(2)
+#define SSP_CLK_BCLK_ACTIVE	BIT(3)
+
+#define I2SLCTL_OFFSET		0x04
+
+#define I2SLCTL_OFLEN		BIT(4)
+#define I2SLCTL_SPA(x)		BIT(16 + x)
+#define I2SLCTL_CPA(x)		BIT(23 + x)
+#define PCMS0CM_OFFSET		0x16
+#define PCMS1CM_OFFSET		PCMS0CM_OFFSET + 4 * I2SIPCMC
+
+#define I2CLCTL_MLCS(x)		DAI_INTEL_SSP_SET_BITS(30, 27, x)
+#define SHIM_CLKCTL		0x78
+#define SHIM_CLKCTL_I2SFDCGB(x)		BIT(20 + x)
+#define SHIM_CLKCTL_I2SEFDCGB(x)	BIT(18 + x)
+
+/** \brief Offset of MCLK Divider Control Register. */
+#define MN_MDIVCTRL 0x100
+
+/** \brief Offset of MCLK Divider x Ratio Register. */
+#define MN_MDIVR(x) (0x180 + (x) * 0x4)
+
+/** \brief Enables the output of MCLK Divider. */
+#define MN_MDIVCTRL_M_DIV_ENABLE(x) BIT(x)
+
+/** \brief Bits for setting MCLK source clock. */
+#define MCDSS(x)	DAI_INTEL_SSP_SET_BITS(17, 16, x)
+
+/** \brief Offset of BCLK x M/N Divider M Value Register. */
+#define MN_MDIV_M_VAL(x) (0x100 + (x) * 0x8 + 0x0)
+
+/** \brief Offset of BCLK x M/N Divider N Value Register. */
+#define MN_MDIV_N_VAL(x) (0x100 + (x) * 0x8 + 0x4)
+
+/** \brief Bits for setting M/N source clock. */
+#define MNDSS(x)	DAI_INTEL_SSP_SET_BITS(21, 20, x)
+
+/** \brief Mask for clearing mclk and bclk source in MN_MDIVCTRL */
+#define MN_SOURCE_CLKS_MASK 0x3
+
+#endif /* __INTEL_DAI_DRIVER_SSP_REGSV1_H__ */
diff --git a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
index e823fb0fe4b..35825e6ea6a 100644
--- a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
@@ -204,7 +204,7 @@
 		};
 
 		ssp0: ssp@28100 {
-			compatible = "intel,ssp-dai";
+			compatible = "intel,ssp";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x00028100 0x1000
@@ -214,12 +214,19 @@
 			dmas = <&hda_link_out 1
 				&hda_link_in 1>;
 			dma-names = "tx", "rx";
+			ssp-index = <0>;
 			power-domain = <&io0_domain>;
 			status = "okay";
+
+			ssp00: ssp@0 {
+				compatible = "intel,ssp-dai";
+				reg = <0x0>;
+				status = "okay";
+			};
 		};
 
 		ssp1: ssp@29100 {
-			compatible = "intel,ssp-dai";
+			compatible = "intel,ssp";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x00029100 0x1000
@@ -229,12 +236,19 @@
 			dmas = <&hda_link_out 2
 				&hda_link_in 2>;
 			dma-names = "tx", "rx";
+			ssp-index = <1>;
 			power-domain = <&io0_domain>;
 			status = "okay";
+
+			ssp10: ssp@10 {
+				compatible = "intel,ssp-dai";
+				reg = <0x10>;
+				status = "okay";
+			};
 		};
 
 		ssp2: ssp@2a100 {
-			compatible = "intel,ssp-dai";
+			compatible = "intel,ssp";
 			#address-cells = <1>;
 			#size-cells = <0>;
 			reg = <0x0002a100 0x1000
@@ -244,53 +258,15 @@
 			dmas = <&hda_link_out 3
 				&hda_link_in 3>;
 			dma-names = "tx", "rx";
+			ssp-index = <2>;
 			power-domain = <&io0_domain>;
 			status = "okay";
-		};
 
-		ssp3: ssp@2b100 {
-			compatible = "intel,ssp-dai";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0002b100 0x1000
-				   0x00079C00 0x200>;
-			interrupts = <0x03 0 0>;
-			interrupt-parent = <&ace_intc>;
-			dmas = <&hda_link_out 4
-				&hda_link_in 4>;
-			dma-names = "tx", "rx";
-			power-domain = <&io0_domain>;
-			status = "okay";
-		};
-
-		ssp4: ssp@2c100 {
-			compatible = "intel,ssp-dai";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0002c100 0x1000
-				   0x00079C00 0x200>;
-			interrupts = <0x04 0 0>;
-			interrupt-parent = <&ace_intc>;
-			dmas = <&hda_link_out 5
-				&hda_link_in 5>;
-			dma-names = "tx", "rx";
-			power-domain = <&io0_domain>;
-			status = "okay";
-		};
-
-		ssp5: ssp@2d100 {
-			compatible = "intel,ssp-dai";
-			#address-cells = <1>;
-			#size-cells = <0>;
-			reg = <0x0002d100 0x1000
-				   0x00079C00 0x200>;
-			interrupts = <0x04 0 0>;
-			interrupt-parent = <&ace_intc>;
-			dmas = <&hda_link_out 6
-				&hda_link_in 6>;
-			dma-names = "tx", "rx";
-			power-domain = <&io0_domain>;
-			status = "okay";
+			ssp20: ssp@20 {
+				compatible = "intel,ssp-dai";
+				reg = <0x20>;
+				status = "okay";
+			};
 		};
 
 		mem_window0: mem_window@70200 {