From 07be9301b960224c96a317fc28c42d8e2bb4d912 Mon Sep 17 00:00:00 2001
From: Lukasz Majewski <lukma@denx.de>
Date: Tue, 30 Nov 2021 10:31:32 +0100
Subject: [PATCH] qspi: stm32: Add support for 'reset-gpios' property in
 'stm32-qspi-nor'

Some flash memories connected to QUADSPI IP block on stm32[fh]7 devices
require proper reset pulse before configuration.

This patch adds two new properties - the 'reset-gpios' phandle,
which allows specifying GPIO pin for RESETn pulse and
'reset-gpios-duration', which provides the time (in ms) for reset
duration.

Signed-off-by: Lukasz Majewski <lukma@denx.de>
---
 drivers/flash/flash_stm32_qspi.c              | 25 +++++++++++++++++++
 .../flash_controller/st,stm32-qspi-nor.yaml   | 10 ++++++++
 2 files changed, 35 insertions(+)

diff --git a/drivers/flash/flash_stm32_qspi.c b/drivers/flash/flash_stm32_qspi.c
index 567203dacdf..c682ee87724 100644
--- a/drivers/flash/flash_stm32_qspi.c
+++ b/drivers/flash/flash_stm32_qspi.c
@@ -20,6 +20,10 @@
 #include <drivers/dma.h>
 #include <drivers/dma/dma_stm32.h>
 
+#define STM32_QSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
+#if STM32_QSPI_RESET_GPIO
+#include <drivers/gpio.h>
+#endif
 #include <stm32_ll_dma.h>
 
 #include "spi_nor.h"
@@ -64,6 +68,9 @@ struct flash_stm32_qspi_config {
 	size_t flash_size;
 	uint32_t max_frequency;
 	const struct pinctrl_dev_config *pcfg;
+#if STM32_QSPI_RESET_GPIO
+	const struct gpio_dt_spec reset;
+#endif
 };
 
 struct flash_stm32_qspi_data {
@@ -642,6 +649,18 @@ static int spi_nor_process_bfp(const struct device *dev,
 	return 0;
 }
 
+#if STM32_QSPI_RESET_GPIO
+static void flash_stm32_qspi_gpio_reset(const struct device *dev)
+{
+	const struct flash_stm32_qspi_config *dev_cfg = DEV_CFG(dev);
+
+	/* Generate RESETn pulse for the flash memory */
+	gpio_pin_configure_dt(&dev_cfg->reset, GPIO_OUTPUT_ACTIVE);
+	k_msleep(DT_INST_PROP(0, reset_gpios_duration));
+	gpio_pin_set_dt(&dev_cfg->reset, 0);
+}
+#endif
+
 static int flash_stm32_qspi_init(const struct device *dev)
 {
 	const struct flash_stm32_qspi_config *dev_cfg = DEV_CFG(dev);
@@ -657,6 +676,9 @@ static int flash_stm32_qspi_init(const struct device *dev)
 		return ret;
 	}
 
+#if STM32_QSPI_RESET_GPIO
+	flash_stm32_qspi_gpio_reset(dev);
+#endif
 #if STM32_QSPI_USE_DMA
 	/*
 	 * DMA configuration
@@ -877,6 +899,9 @@ static const struct flash_stm32_qspi_config flash_stm32_qspi_cfg = {
 	.flash_size = DT_INST_PROP(0, size) / 8U,
 	.max_frequency = DT_INST_PROP(0, qspi_max_frequency),
 	.pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_QSPI_NODE),
+#if STM32_QSPI_RESET_GPIO
+	.reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
+#endif
 };
 
 static struct flash_stm32_qspi_data flash_stm32_qspi_dev_data = {
diff --git a/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
index 1e8f5bd3dba..ead3892e821 100644
--- a/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
+++ b/dts/bindings/flash_controller/st,stm32-qspi-nor.yaml
@@ -12,6 +12,8 @@ description: |
                 reg = <0>;
                 qspi-max-frequency = <80000000>;
                 size = <0x4000000>;
+                reset-gpios = <&gpiod 3 GPIO_ACTIVE_LOW>;
+                reset-gpios-duration = <1>;
                 status = "okay";
         };
 
@@ -33,3 +35,11 @@ properties:
     size:
       required: true
       description: Flash Memory size in bits
+    reset-gpios:
+      type: phandle-array
+      required: false
+      description: RESETn pin
+    reset-gpios-duration:
+      type: int
+      required: false
+      description: The duration (in ms) for the flash memory reset pulse