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ITE: soc: chip_chipregs: Access registers using structure method

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Access registers using structure method.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2022-11-07 13:47:17 +08:00 • committed by Carles Cufí
commit 0789442132
5 changed files with 139 additions and 132 deletions
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11
drivers/flash/flash_ite_it8xxx2.c
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@ -93,12 +93,14 @@ static const struct flash_parameters flash_it8xxx2_parameters = {
void __soc_ram_code ramcode_reset_i_cache(void)
{
struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
/* I-Cache tag sram reset */
IT83XX_GCTRL_MCCR |= IT83XX_GCTRL_ICACHE_RESET;
gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET;
/* Make sure the I-Cache is reset */
__asm__ volatile ("fence.i" ::: "memory");
IT83XX_GCTRL_MCCR &= ~IT83XX_GCTRL_ICACHE_RESET;
gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET;
__asm__ volatile ("fence.i" ::: "memory");
}
@ -135,6 +137,7 @@ void __soc_ram_code ramcode_flash_follow_mode_exit(void)
void __soc_ram_code ramcode_flash_fsce_high(void)
{
struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
/* FSCE# high level */
flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0);
@ -148,8 +151,8 @@ void __soc_ram_code ramcode_flash_fsce_high(void)
* So we perform 2 consecutive writes to WNCKR here to ensure the
* minimum delay is 15us.
*/
IT83XX_GCTRL_WNCKR = 0;
IT83XX_GCTRL_WNCKR = 0;
gctrl_regs->GCTRL_WNCKR = 0;
gctrl_regs->GCTRL_WNCKR = 0;
/* Writing 0 to EC-indirect memory data register */
flash_regs->SMFI_ECINDDR = 0x00;