x86: implement hw-based oops for both variants

We use a fixed value of 32 as the way interrupts/exceptions
are setup in x86_64's locore.S do not lend themselves to
Kconfig configuration of the vector to use.

HW-based kernel oops is now permanently on, there's no reason
to make it optional that I can see.

Default vectors for IPI and irq offload adjusted to not
collide.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>

include/arch/x86/arch.h

@@ -8,6 +8,11 @@
 
 #include <generated_dts_board.h>
 
+/* Changing this value will require manual changes to exception and IDT setup
+ * in locore.S for intel64
+ */
+#define Z_X86_OOPS_VECTOR	32
+
 #if !defined(_ASMLANGUAGE)
 
 #include <sys/sys_io.h>

include/arch/x86/ia32/arch.h

@@ -410,17 +410,15 @@ extern void k_float_enable(struct k_thread *thread, unsigned int options);
 extern struct task_state_segment _main_tss;
 #endif
 
-#if CONFIG_X86_KERNEL_OOPS
 #define ARCH_EXCEPT(reason_p) do { \
 	__asm__ volatile( \
 		"push %[reason]\n\t" \
 		"int %[vector]\n\t" \
 		: \
-		: [vector] "i" (CONFIG_X86_KERNEL_OOPS_VECTOR), \
+		: [vector] "i" (Z_X86_OOPS_VECTOR), \
 		  [reason] "i" (reason_p)); \
 	CODE_UNREACHABLE; \
 } while (false)
-#endif
 
 #ifdef __cplusplus
 }

include/arch/x86/intel64/arch.h

@@ -59,6 +59,15 @@ struct x86_esf {
 
 typedef struct x86_esf z_arch_esf_t;
 
+#define ARCH_EXCEPT(reason_p) do { \
+	__asm__ volatile( \
+		"movq %[reason], %%rax\n\t" \
+		"int $32\n\t" \
+		: \
+		: [reason] "i" (reason_p)); \
+	CODE_UNREACHABLE; \
+} while (false)
+
 #endif /* _ASMLANGUAGE */
 
 /*