michaelh/zephyr
1
0
Fork 0
Code Releases Activity

x86: implement hw-based oops for both variants

Browse source 
We use a fixed value of 32 as the way interrupts/exceptions
are setup in x86_64's locore.S do not lend themselves to
Kconfig configuration of the vector to use.

HW-based kernel oops is now permanently on, there's no reason
to make it optional that I can see.

Default vectors for IPI and irq offload adjusted to not
collide.

Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
This commit is contained in:
Andrew Boie 2019-12-18 14:12:54 -08:00 • committed by Anas Nashif
commit 077b587447
14 changed files with 63 additions and 50 deletions
Download patch file Download diff file Expand all files Collapse all files

16
arch/x86/core/Kconfig.ia32
View file

@ -197,22 +197,6 @@ config CACHE_FLUSHING
cache must be selected as well. By default, that mechanism is discovered at
runtime.
config X86_KERNEL_OOPS
bool "Enable handling of kernel oops as an exception"
default y
help
Enable handling of k_oops() API as a CPU exception, which will provide
extra debugging information such as program counter and register
values when the oops is triggered. Requires an entry in the IDT.
config X86_KERNEL_OOPS_VECTOR
int "IDT vector to use for kernel oops"
default 33
range 32 255
depends on X86_KERNEL_OOPS
help
Specify the IDT vector to use for the kernel oops exception handler.
config X86_DYNAMIC_IRQ_STUBS
int "Number of dynamic interrupt stubs"
depends on DYNAMIC_INTERRUPTS