diff --git a/include/zephyr/dt-bindings/clock/esp32s2_clock.h b/include/zephyr/dt-bindings/clock/esp32s2_clock.h index c61c8b88801..aa9eb90de62 100644 --- a/include/zephyr/dt-bindings/clock/esp32s2_clock.h +++ b/include/zephyr/dt-bindings/clock/esp32s2_clock.h @@ -21,7 +21,7 @@ #define ESP32_CLK_CPU_240M 240000000 /* Supported XTAL Frequencies */ -#define ESP32_CLK_XTAL_40M 0U +#define ESP32_CLK_XTAL_40M 40 /* Supported RTC fast clock frequencies */ #define ESP32_RTC_FAST_CLK_FREQ_8M 8500000U diff --git a/soc/espressif/esp32s2/CMakeLists.txt b/soc/espressif/esp32s2/CMakeLists.txt index 1c840ce2289..e93e5711089 100644 --- a/soc/espressif/esp32s2/CMakeLists.txt +++ b/soc/espressif/esp32s2/CMakeLists.txt @@ -3,7 +3,7 @@ zephyr_sources( soc.c soc_cache.c - loader.c + ../common/loader.c ) zephyr_include_directories(.) @@ -25,52 +25,21 @@ dt_reg_addr(boot_off PATH ${dts_partition_path}) math(EXPR esptoolpy_flashsize "${CONFIG_FLASH_SIZE} / 0x100000") if(CONFIG_BOOTLOADER_ESP_IDF) - include(ExternalProject) - ## we use hello-world project, but I think any can be used. - set(espidf_components_dir ${ESP_IDF_PATH}/components) - set(espidf_prefix ${CMAKE_BINARY_DIR}/esp-idf) - set(espidf_build_dir ${espidf_prefix}/build) + set(bootloader_dir "${ZEPHYR_HAL_ESPRESSIF_MODULE_DIR}/zephyr/blobs/lib/${CONFIG_SOC_SERIES}") - ExternalProject_Add( - EspIdfBootloader - PREFIX ${espidf_prefix} - SOURCE_DIR ${espidf_components_dir}/bootloader/subproject - BINARY_DIR ${espidf_build_dir}/bootloader - CONFIGURE_COMMAND - ${CMAKE_COMMAND} -G${CMAKE_GENERATOR} - -S ${espidf_components_dir}/bootloader/subproject - -B ${espidf_build_dir}/bootloader -DSDKCONFIG=${espidf_build_dir}/sdkconfig - -DIDF_PATH=${ESP_IDF_PATH} -DIDF_TARGET=${CONFIG_SOC_SERIES} - -DPYTHON_DEPS_CHECKED=1 - -DCMAKE_C_COMPILER=${CMAKE_C_COMPILER} - -DCMAKE_CXX_COMPILER=${CMAKE_CXX_COMPILER} - -DCMAKE_ASM_COMPILER=${CMAKE_ASM_COMPILER} - -DCMAKE_SYSTEM_NAME=${CMAKE_SYSTEM_NAME} - -DPYTHON=${PYTHON_EXECUTABLE} - BUILD_COMMAND - ${CMAKE_COMMAND} --build . - INSTALL_COMMAND "" # This particular build system has no install command - ) + if(EXISTS "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/bootloader-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/bootloader-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/bootloader.bin") + endif() - ExternalProject_Add( - EspPartitionTable - SOURCE_DIR ${espidf_components_dir}/partition_table - BINARY_DIR ${espidf_build_dir} - CONFIGURE_COMMAND "" - BUILD_COMMAND - ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/partition_table/gen_esp32part.py -q - --offset 0x8000 --flash-size ${esptoolpy_flashsize}MB ${ESP_IDF_PATH}/components/partition_table/partitions_singleapp.csv ${espidf_build_dir}/partitions_singleapp.bin - INSTALL_COMMAND "" - ) + if(EXISTS "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin") + file(COPY "${bootloader_dir}/partition-table-${CONFIG_SOC_SERIES}.bin" DESTINATION ${CMAKE_BINARY_DIR}) + file(RENAME "${CMAKE_BINARY_DIR}/partition-table-${CONFIG_SOC_SERIES}.bin" "${CMAKE_BINARY_DIR}/partition-table.bin") + endif() + board_finalize_runner_args(esp32 "--esp-flash-bootloader=${CMAKE_BINARY_DIR}/bootloader.bin") - set_property(TARGET bintools PROPERTY disassembly_flag_inline_source) - - add_dependencies(app EspIdfBootloader EspPartitionTable) - - board_finalize_runner_args(esp32 "--esp-flash-bootloader=${espidf_build_dir}/bootloader/bootloader.bin") - - board_finalize_runner_args(esp32 "--esp-flash-partition_table=${espidf_build_dir}/partitions_singleapp.bin") + board_finalize_runner_args(esp32 "--esp-flash-partition_table=${CMAKE_BINARY_DIR}/partition-table.bin") board_finalize_runner_args(esp32 "--esp-partition-table-address=0x8000") @@ -80,7 +49,7 @@ if(CONFIG_MCUBOOT OR CONFIG_BOOTLOADER_ESP_IDF) if(CONFIG_BUILD_OUTPUT_BIN) set_property(GLOBAL APPEND PROPERTY extra_post_build_commands - COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/components/esptool_py/esptool/esptool.py + COMMAND ${PYTHON_EXECUTABLE} ${ESP_IDF_PATH}/tools/esptool_py/esptool.py ARGS --chip esp32s2 elf2image --flash_mode dio --flash_freq 40m --flash_size ${esptoolpy_flashsize}MB -o ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.bin ${CMAKE_BINARY_DIR}/zephyr/${CONFIG_KERNEL_BIN_NAME}.elf) diff --git a/soc/espressif/esp32s2/Kconfig b/soc/espressif/esp32s2/Kconfig index 1c657c4e1b5..0efda60d23c 100644 --- a/soc/espressif/esp32s2/Kconfig +++ b/soc/espressif/esp32s2/Kconfig @@ -19,72 +19,6 @@ config IDF_TARGET_ESP32S2 bool "ESP32S2 as target SOC" default y -config ESP_SYSTEM_RTC_EXT_XTAL - bool - -config ESP_SYSTEM_RTC_EXT_OSC - bool - -choice ESP32S2_RTC_CLK_SRC - prompt "RTC clock source" - default ESP32S2_RTC_CLK_SRC_INT_RC - help - Choose which clock is used as RTC clock source. - - - "Internal 90kHz oscillator" option provides lowest deep sleep current - consumption, and does not require extra external components. However - frequency stability with respect to temperature is poor, so time may - drift in deep/light sleep modes. - - "External 32kHz crystal" provides better frequency stability, at the - expense of slightly higher (1uA) deep sleep current consumption. - - "External 32kHz oscillator" allows using 32kHz clock generated by an - external circuit. In this case, external clock signal must be connected - to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, - and <1V in case of square wave signal. Common mode voltage should be - 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. - Additionally, 1nF capacitor must be connected between 32K_XP pin and - ground. 32K_XP pin can not be used as a GPIO in this case. - - "Internal 8MHz oscillator divided by 256" option results in higher - deep sleep current (by 5uA) but has better frequency stability than - the internal 90kHz oscillator. It does not require external components. - -config ESP32S2_RTC_CLK_SRC_INT_RC - bool "Internal 90kHz RC oscillator" - -config ESP32S2_RTC_CLK_SRC_EXT_CRYS - bool "External 32kHz crystal" - select ESP_SYSTEM_RTC_EXT_XTAL - -config ESP32S2_RTC_CLK_SRC_EXT_OSC - bool "External 32kHz oscillator at 32K_XN pin" - select ESP_SYSTEM_RTC_EXT_OSC - -config ESP32S2_RTC_CLK_SRC_INT_8MD256 - bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" - -endchoice - -config ESP32S2_RTC_CLK_CAL_CYCLES - int "Number of cycles for RTC_SLOW_CLK calibration" - default 3000 if ESP32S2_RTC_CLK_SRC_EXT_CRYS || ESP32S2_RTC_CLK_SRC_EXT_OSC || ESP32S2_RTC_CLK_SRC_INT_8MD256 - default 576 if ESP32S2_RTC_CLK_SRC_INT_RC - range 0 125000 - help - When the startup code initializes RTC_SLOW_CLK, it can perform - calibration by comparing the RTC_SLOW_CLK frequency with main XTAL - frequency. This option sets the number of RTC_SLOW_CLK cycles measured - by the calibration routine. Higher numbers increase calibration - precision, which may be important for applications which spend a lot of - time in deep sleep. Lower numbers reduce startup time. - - When this option is set to 0, clock calibration will not be performed at - startup, and approximate clock frequencies will be assumed: - - - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. - - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. - In case more value will help improve the definition of the launch of the crystal. - If the crystal could not start, it will be switched to internal RC. - menu "Cache config" choice @@ -111,19 +45,18 @@ choice endchoice -choice +choice ESP32S2_DATA_CACHE_SIZE prompt "Data cache size" - default ESP32S2_DATA_CACHE_0KB if !ESP_SPIRAM - default ESP32S2_DATA_CACHE_8KB if ESP_SPIRAM - + default ESP32S2_DATA_CACHE_8KB + help + Data cache size to be set on application startup. config ESP32S2_DATA_CACHE_0KB - bool "0KB data cache size" - + depends on !ESP_SPIRAM + bool "0KB" config ESP32S2_DATA_CACHE_8KB - bool "8KB data cache size" - + bool "8KB" config ESP32S2_DATA_CACHE_16KB - bool "16KB data cache size" + bool "16KB" endchoice @@ -152,67 +85,6 @@ config ESP32S2_DATA_CACHE_SIZE endmenu # Cache config -menu "PSRAM clock and cs IO for ESP32-S2" - depends on ESP_SPIRAM - -config DEFAULT_PSRAM_CLK_IO - int "PSRAM CLK IO number" - range 0 33 - default 30 - help - The PSRAM CLOCK IO can be any unused GPIO, user can config - it based on hardware design. - -config DEFAULT_PSRAM_CS_IO - int "PSRAM CS IO number" - range 0 33 - default 26 - help - The PSRAM CS IO can be any unused GPIO, user can config it - based on hardware design. - -endmenu # PSRAM clock and cs IO for ESP32S2 - -choice ESP32S2_UNIVERSAL_MAC_ADDRESSES - bool "Number of universally administered (by IEEE) MAC address" - default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - help - Configure the number of universally administered (by IEEE) MAC addresses. - During initialization, MAC addresses for each network interface are generated or - derived from a single base MAC address. If the number of universal MAC addresses is two, - all interfaces (WiFi station, WiFi softap) receive a universally administered MAC - address. - They are generated sequentially by adding 0, and 1 (respectively) to the final octet of - the base MAC address. If the number of universal MAC addresses is one, only WiFi station - receives a universally administered MAC address. - The WiFi softap receives local MAC addresses. It's derived from the universal WiFi - station MAC addresses. - When using the default (Espressif-assigned) base MAC address, either setting can be used. - When using a custom universal MAC address range, the correct setting will depend on the - allocation of MAC addresses in this range (either 1 or 2 per device). - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - bool "One" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - bool "Two" - select ESP_MAC_ADDR_UNIVERSE_WIFI_STA - select ESP_MAC_ADDR_UNIVERSE_WIFI_AP - -endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES - -config ESP_MAC_ADDR_UNIVERSE_WIFI_AP - bool - -config ESP_MAC_ADDR_UNIVERSE_WIFI_STA - bool - -config ESP32S2_UNIVERSAL_MAC_ADDRESSES - int - default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE - default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO - config ESP32_PHY_MAX_WIFI_TX_POWER int "Max WiFi TX power (dBm)" range 10 20 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig b/soc/espressif/esp32s2/Kconfig.defconfig index 6daf53e76df..ec58addff67 100644 --- a/soc/espressif/esp32s2/Kconfig.defconfig +++ b/soc/espressif/esp32s2/Kconfig.defconfig @@ -3,22 +3,10 @@ if SOC_SERIES_ESP32S2 -config MINIMAL_LIBC_OPTIMIZE_STRING_FOR_SIZE - default n - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config ESPTOOLPY_FLASHFREQ_80M - default y - config FLASH_SIZE default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) config FLASH_BASE_ADDRESS default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) -endif # SOC_SERIES_ESP32S3 +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.defconfig.series b/soc/espressif/esp32s2/Kconfig.defconfig.series deleted file mode 100644 index 50ddbd72704..00000000000 --- a/soc/espressif/esp32s2/Kconfig.defconfig.series +++ /dev/null @@ -1,27 +0,0 @@ -# Copyright (c) 2023 Espressif Systems (Shanghai) Co., Ltd. -# SPDX-License-Identifier: Apache-2.0 - -if SOC_SERIES_ESP32S2 - -config SYS_CLOCK_HW_CYCLES_PER_SEC - default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) - -config XTENSA_CCOUNT_HZ - default SYS_CLOCK_HW_CYCLES_PER_SEC - -config MP_MAX_NUM_CPUS - default 1 - -config ISR_STACK_SIZE - default 2048 - -config ESPTOOLPY_FLASHFREQ_80M - default y - -config FLASH_SIZE - default $(dt_node_reg_size_int,/soc/flash-controller@3f402000/flash@0,0) - -config FLASH_BASE_ADDRESS - default $(dt_node_reg_addr_hex,/soc/flash-controller@3f402000/flash@0) - -endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.mac b/soc/espressif/esp32s2/Kconfig.mac new file mode 100644 index 00000000000..97a5ff1d914 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.mac @@ -0,0 +1,42 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +choice ESP32S2_UNIVERSAL_MAC_ADDRESSES + bool "Number of universally administered (by IEEE) MAC address" + default ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + help + Configure the number of universally administered (by IEEE) MAC addresses. + During initialization, MAC addresses for each network interface are generated or + derived from a single base MAC address. If the number of universal MAC addresses is two, + all interfaces (WiFi station, WiFi softap) receive a universally administered MAC + address. + They are generated sequentially by adding 0, and 1 (respectively) to the final octet of + the base MAC address. If the number of universal MAC addresses is one, only WiFi station + receives a universally administered MAC address. + The WiFi softap receives local MAC addresses. It's derived from the universal WiFi + station MAC addresses. + When using the default (Espressif-assigned) base MAC address, either setting can be used. + When using a custom universal MAC address range, the correct setting will depend on the + allocation of MAC addresses in this range (either 1 or 2 per device). + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + bool "One" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + bool "Two" + select ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO + select ESP_MAC_ADDR_UNIVERSE_WIFI_STA + select ESP_MAC_ADDR_UNIVERSE_WIFI_AP + +endchoice # ESP32S2_UNIVERSAL_MAC_ADDRESSES + +config ESP32S2_UNIVERSAL_MAC_ADDRESSES + int + default 1 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_ONE + default 2 if ESP32S2_UNIVERSAL_MAC_ADDRESSES_TWO + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/Kconfig.rtc b/soc/espressif/esp32s2/Kconfig.rtc new file mode 100644 index 00000000000..837ab8623e5 --- /dev/null +++ b/soc/espressif/esp32s2/Kconfig.rtc @@ -0,0 +1,76 @@ +# Copyright (c) 2024 Espressif Systems (Shanghai) Co., Ltd. +# SPDX-License-Identifier: Apache-2.0 + +if SOC_SERIES_ESP32S2 + +choice RTC_CLK_SRC + prompt "RTC clock source" + default RTC_CLK_SRC_INT_RC + help + Choose which clock is used as RTC clock source. + + - "Internal 90kHz oscillator" option provides lowest deep sleep current + consumption, and does not require extra external components. However + frequency stability with respect to temperature is poor, so time may + drift in deep/light sleep modes. + - "External 32kHz crystal" provides better frequency stability, at the + expense of slightly higher (1uA) deep sleep current consumption. + - "External 32kHz oscillator" allows using 32kHz clock generated by an + external circuit. In this case, external clock signal must be connected + to 32K_XN pin. Amplitude should be <1.2V in case of sine wave signal, + and <1V in case of square wave signal. Common mode voltage should be + 0.1 < Vcm < 0.5Vamp, where Vamp is the signal amplitude. + Additionally, 1nF capacitor must be connected between 32K_XP pin and + ground. 32K_XP pin can not be used as a GPIO in this case. + - "Internal 8MHz oscillator divided by 256" option results in higher + deep sleep current (by 5uA) but has better frequency stability than + the internal 90kHz oscillator. It does not require external components. + +config RTC_CLK_SRC_INT_RC + bool "Internal 90kHz RC oscillator" + +config RTC_CLK_SRC_EXT_CRYS + bool "External 32kHz crystal" + select ESP_SYSTEM_RTC_EXT_XTAL + +config RTC_CLK_SRC_EXT_OSC + bool "External 32kHz oscillator at 32K_XN pin" + select ESP_SYSTEM_RTC_EXT_OSC + +config RTC_CLK_SRC_INT_8MD256 + bool "Internal 8MHz oscillator, divided by 256 (~32kHz)" + +endchoice + +config RTC_CLK_CAL_CYCLES + int "Number of cycles for RTC_SLOW_CLK calibration" + default 3000 if RTC_CLK_SRC_EXT_CRYS || RTC_CLK_SRC_EXT_OSC || RTC_CLK_SRC_INT_8MD256 + default 576 if RTC_CLK_SRC_INT_RC + range 0 125000 + help + When the startup code initializes RTC_SLOW_CLK, it can perform + calibration by comparing the RTC_SLOW_CLK frequency with main XTAL + frequency. This option sets the number of RTC_SLOW_CLK cycles measured + by the calibration routine. Higher numbers increase calibration + precision, which may be important for applications which spend a lot of + time in deep sleep. Lower numbers reduce startup time. + + When this option is set to 0, clock calibration will not be performed at + startup, and approximate clock frequencies will be assumed: + + - 90000 Hz if internal RC oscillator is used as clock source. For this use value 1024. + - 32768 Hz if the 32k crystal oscillator is used. For this use value 3000 or more. + In case more value will help improve the definition of the launch of the crystal. + If the crystal could not start, it will be switched to internal RC. + +config RTC_XTAL_CAL_RETRY + int "Number of attempts to repeat 32k XTAL calibration" + default 3 + depends on RTC_CLK_SRC_EXT_CRYS + help + Number of attempts to repeat 32k XTAL calibration + before giving up and switching to the internal RC. + Increase this option if the 32k crystal oscillator + does not start and switches to internal RC. + +endif # SOC_SERIES_ESP32S2 diff --git a/soc/espressif/esp32s2/default.ld b/soc/espressif/esp32s2/default.ld index 8a78bb89ac2..6c335aafa1d 100644 --- a/soc/espressif/esp32s2/default.ld +++ b/soc/espressif/esp32s2/default.ld @@ -71,7 +71,7 @@ MEMORY rtc_iram_seg(RWX): org = 0x40070000, len = 0x2000 rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 #if defined(CONFIG_ESP_SPIRAM) - ext_ram_seg(RW): org = 0x3f500000, len = CONFIG_ESP_SPIRAM_SIZE + ext_ram_seg(RW): org = 0x3f800000, len = CONFIG_ESP_SPIRAM_SIZE #endif #ifdef CONFIG_GEN_ISR_TABLES IDT_LIST(RW): org = 0x3ebfe010, len = 0x2000 @@ -137,6 +137,7 @@ SECTIONS { _rodata_reserved_start = ABSOLUTE(.); __rodata_region_start = ABSOLUTE(.); + _rodata_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.rodata start, this can be used for mmu driver to maintain virtual address */ . = ALIGN(4); #include @@ -196,8 +197,9 @@ SECTIONS _rodata_reserved_end = ABSOLUTE(.); . = ALIGN(4); _image_rodata_end = ABSOLUTE(.); - } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) + _rodata_reserved_end = ABSOLUTE(.); + } GROUP_DATA_LINK_IN(RODATA_REGION, ROMABLE_REGION) /* Send .iram0 code to iram */ .iram0.vectors : ALIGN(4) @@ -249,17 +251,11 @@ SECTIONS *(.iram0.literal .iram.literal .iram.text.literal .iram0.text .iram.text) *libesp32.a:panic.*(.literal .text .literal.* .text.*) *librtc.a:(.literal .text .literal.* .text.*) - *libsubsys__net__l2__ethernet.a:(.literal .text .literal.* .text.*) - *libsubsys__net__lib__config.a:(.literal .text .literal.* .text.*) - *libsubsys__net__ip.a:(.literal .text .literal.* .text.*) - *libsubsys__net.a:(.literal .text .literal.* .text.*) *libarch__xtensa__core.a:(.literal .text .literal.* .text.*) *libkernel.a:(.literal .text .literal.* .text.*) *libsoc.a:rtc_*.*(.literal .text .literal.* .text.*) *libsoc.a:cpu_util.*(.literal .text .literal.* .text.*) *libgcc.a:lib2funcs.*(.literal .text .literal.* .text.*) - *libdrivers__flash.a:flash_esp32.*(.literal .text .literal.* .text.*) - *libzephyr.a:spi_flash_rom_patch.*(.literal .text .literal.* .text.*) *libzephyr.a:windowspill_asm.*(.literal .text .literal.* .text.*) *libzephyr.a:log_noos.*(.literal .text .literal.* .text.*) *libdrivers__timer.a:xtensa_sys_timer.*(.literal .text .literal.* .text.*) @@ -271,12 +267,59 @@ SECTIONS *libdrivers__console.a:uart_console.*(.literal.console_out .text.console_out) *libzephyr.a:log_output.*(.literal .text .literal.* .text.*) *libzephyr.a:log_backend_uart.*(.literal .text .literal.* .text.*) + *libzephyr.a:cache_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) *libzephyr.a:loader.*(.literal .text .literal.* .text.*) *liblib__libc__minimal.a:string.*(.literal .text .literal.* .text.*) *liblib__libc__newlib.a:string.*(.literal .text .literal.* .text.*) *libc.a:*(.literal .text .literal.* .text.*) *libphy.a:( .phyiram .phyiram.*) *libgcov.a:(.literal .text .literal.* .text.*) + *libzephyr.a:cpu.*(.literal.esp_cpu_compare_and_set .text.esp_cpu_compare_and_set) + *libzephyr.a:cpu.*(.literal.esp_cpu_reset .text.esp_cpu_reset) + *libzephyr.a:cpu.*(.literal.esp_cpu_stall .text.esp_cpu_stall) + *libzephyr.a:cpu.*(.literal.esp_cpu_unstall .text.esp_cpu_unstall) + *libzephyr.a:cpu.*(.literal.esp_cpu_wait_for_intr .text.esp_cpu_wait_for_intr) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_is_pin_reserved .text.esp_gpio_is_pin_reserved) + *libzephyr.a:esp_gpio_reserve.*(.literal.esp_gpio_reserve_pins .text.esp_gpio_reserve_pins) + *libzephyr.a:esp_memory_utils.*(.literal .literal.* .text .text.*) + *libzephyr.a:periph_ctrl.*(.literal.periph_module_reset .text.periph_module_reset) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_disable .text.wifi_module_disable) + *libzephyr.a:periph_ctrl.*(.literal.wifi_module_enable .text.wifi_module_enable) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_sleep.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_wdt.*(.literal .literal.* .text .text.*) + *libzephyr.a:sar_periph_ctrl.*(.literal.sar_periph_ctrl_power_enable .text.sar_periph_ctrl_power_enable) + *libzephyr.a:systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_cache.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_spiflash.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_rom_systimer.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_err.*(.literal .literal.* .text .text.*) + *libzephyr.a:esp_system_chip.*(.literal.esp_system_abort .text.esp_system_abort) + *libzephyr.a:cache_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:i2c_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:ledc_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:mmu_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_slave_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:systimer_hal.*(.literal .literal.* .text .text.*) + *libzephyr.a:wdt_hal_iram.*(.literal .literal.* .text .text.*) + *libzephyr.a:flash_brownout_hook.*(.literal .literal.* .text .text.*) + *libzephyr.a:memspi_host_driver.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_boya.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_gd.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_generic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_issi.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_mxic.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_th.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_chip_winbond.*(.literal .literal.* .text .text.*) + *libzephyr.a:spi_flash_wrap.*(.literal .literal.* .text .text.*) #if defined(CONFIG_ESP32_WIFI_IRAM_OPT) *libnet80211.a:( .wifi0iram .wifi0iram.* .wifislpiram .wifislpiram.*) @@ -329,11 +372,18 @@ SECTIONS } GROUP_LINK_IN(RAMABLE_REGION) #if defined(CONFIG_ESP_SPIRAM) - .ext_ram.bss (NOLOAD): + /* This section holds .ext_ram.bss data, and will be put in PSRAM */ + .ext_ram.bss (NOLOAD) : { _ext_ram_data_start = ABSOLUTE(.); _ext_ram_bss_start = ABSOLUTE(.); + *(.ext_ram.bss*) + . = ALIGN(4); + _ext_ram_bss_end = ABSOLUTE(.); + } > ext_ram_seg + .ext_ram_noinit (NOLOAD) : + { #if defined(CONFIG_ESP32_WIFI_NET_ALLOC_SPIRAM) *libdrivers__wifi.a:(.noinit .noinit.*) *libsubsys__net__l2__ethernet.a:(.noinit .noinit.*) @@ -344,10 +394,6 @@ SECTIONS _spiram_heap_start = ABSOLUTE(.); . = . + CONFIG_ESP_SPIRAM_HEAP_SIZE; - *(.ext_ram.bss*) - . = ALIGN(4); - _ext_ram_bss_end = ABSOLUTE(.); - _ext_ram_data_end = ABSOLUTE(.); } > ext_ram_seg #endif @@ -384,10 +430,41 @@ SECTIONS *libzephyr.a:log_core.*(.rodata .rodata.*) *libzephyr.a:log_backend_uart.*(.rodata .rodata.*) *libzephyr.a:log_output.*(.rodata .rodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) *libzephyr.a:loader.*(.rodata .rodata.*) - *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) - *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) + *libdrivers__flash.a:flash_esp32.*(.rodata .rodata.*) + *libzephyr.a:spi_flash_rom_patch.*(.rodata .rodata.*) *libdrivers__serial.a:uart_esp32.*(.rodata .rodata.*) + *libzephyr.a:esp_memory_utils.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_cache.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_cache_esp32s2_esp32s3.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_spiflash.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_rom_systimer.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:esp_err.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:cache_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:i2c_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:ledc_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:mmu_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_encrypt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_gpspi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_init.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_slave_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:systimer_hal.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:wdt_hal_iram.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:flash_brownout_hook.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:memspi_host_driver.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_boya.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_gd.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_generic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_issi.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_mxic.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_th.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_chip_winbond.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) + *libzephyr.a:spi_flash_wrap.*(.rodata .rodata.* .sdata2 .sdata2.* .srodata .srodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) @@ -436,6 +513,7 @@ SECTIONS { . = ALIGN(8); _stext = .; + _instruction_reserved_start = ABSOLUTE(.); /* This is a symbol marking the flash.text start, this can be used for mmu driver to maintain virtual address */ _text_start = ABSOLUTE(.); #if !defined(CONFIG_ESP32_WIFI_IRAM_OPT) @@ -453,6 +531,7 @@ SECTIONS *(.literal .text .literal.* .text.*) . = ALIGN(8); _text_end = ABSOLUTE(.); + _instruction_reserved_end = ABSOLUTE(.); _etext = .; /* Similar to _iram_start, this symbol goes here so it is diff --git a/soc/espressif/esp32s2/loader.c b/soc/espressif/esp32s2/loader.c deleted file mode 100644 index 53eda01310b..00000000000 --- a/soc/espressif/esp32s2/loader.c +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2022 Espressif Systems (Shanghai) Co., Ltd. - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include -#include -#include -#include -#include - -#include -#include "soc/cache_memory.h" -#include "soc/extmem_reg.h" -#include - -#ifdef CONFIG_BOOTLOADER_MCUBOOT - -#define BOOT_LOG_INF(_fmt, ...) \ - ets_printf("[" CONFIG_SOC_SERIES "] [INF] " _fmt "\n\r", ##__VA_ARGS__) - -#define HDR_ATTR __attribute__((section(".entry_addr"))) __attribute__((used)) - -extern uint32_t _image_irom_start, _image_irom_size, _image_irom_vaddr; -extern uint32_t _image_drom_start, _image_drom_size, _image_drom_vaddr; - -void __start(void); - -static HDR_ATTR void (*_entry_point)(void) = &__start; - -static int map_rom_segments(void) -{ - int rc = 0; - - size_t _partition_offset = FIXED_PARTITION_OFFSET(slot0_partition); - uint32_t _app_irom_start = _partition_offset + (uint32_t)&_image_irom_start; - uint32_t _app_irom_size = (uint32_t)&_image_irom_size; - uint32_t _app_irom_vaddr = (uint32_t)&_image_irom_vaddr; - - uint32_t _app_drom_start = _partition_offset + (uint32_t)&_image_drom_start; - uint32_t _app_drom_size = (uint32_t)&_image_drom_size; - uint32_t _app_drom_vaddr = (uint32_t)&_image_drom_vaddr; - - uint32_t autoload = esp_rom_Cache_Suspend_ICache(); - - esp_rom_Cache_Invalidate_ICache_All(); - - /* Clear the MMU entries that are already set up, - * so the new app only has the mappings it creates. - */ - for (size_t i = 0; i < FLASH_MMU_TABLE_SIZE; i++) { - FLASH_MMU_TABLE[i] = MMU_TABLE_INVALID_VAL; - } - - uint32_t drom_page_count = bootloader_cache_pages_to_map(_app_drom_size, _app_drom_vaddr); - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_drom_vaddr & 0xffff0000, - _app_drom_start & 0xffff0000, 64, drom_page_count, 0); - - uint32_t irom_page_count = bootloader_cache_pages_to_map(_app_irom_size, _app_irom_vaddr); - - if (_app_irom_vaddr + _app_irom_size > IRAM1_ADDRESS_LOW) { - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM0_ADDRESS_LOW, 0, 64, 64, 1); - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, IRAM1_ADDRESS_LOW, 0, 64, 64, 1); - REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, EXTMEM_PRO_ICACHE_MASK_IRAM1); - } - - rc |= esp_rom_Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, _app_irom_vaddr & 0xffff0000, - _app_irom_start & 0xffff0000, 64, irom_page_count, 0); - - REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, (EXTMEM_PRO_ICACHE_MASK_IRAM0) | - (EXTMEM_PRO_ICACHE_MASK_IRAM1 & 0) | EXTMEM_PRO_ICACHE_MASK_DROM0); - - esp_rom_Cache_Resume_ICache(autoload); - - /* Show map segments continue using same log format as during MCUboot phase */ - BOOT_LOG_INF("DROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map", - _app_drom_start, _app_drom_vaddr, _app_drom_size, _app_drom_size); - BOOT_LOG_INF("IROM segment: paddr=%08Xh, vaddr=%08Xh, size=%05Xh (%6d) map\r\n", - _app_irom_start, _app_irom_vaddr, _app_irom_size, _app_irom_size); - esp_rom_uart_tx_wait_idle(0); - - return rc; -} -#endif - -void __start(void) -{ -#ifdef CONFIG_BOOTLOADER_MCUBOOT - int err = map_rom_segments(); - - if (err != 0) { - ets_printf("Failed to setup XIP, aborting\n"); - abort(); - } -#endif - __esp_platform_start(); -} diff --git a/soc/espressif/esp32s2/mcuboot.ld b/soc/espressif/esp32s2/mcuboot.ld index 6d52100db75..17a975ee363 100644 --- a/soc/espressif/esp32s2/mcuboot.ld +++ b/soc/espressif/esp32s2/mcuboot.ld @@ -36,8 +36,8 @@ MEMORY { - iram_seg (RWX) : org = 0x40040000, len = 0x6000 - iram_loader_seg (RWX) : org = 0x40046000, len = 0x2000 + iram_seg (RWX) : org = 0x40040000, len = 0x7000 + iram_loader_seg (RWX) : org = 0x40047000, len = 0x3000 dram_seg (RW) : org = 0x3FFE6000, len = 0x6000 #ifdef CONFIG_GEN_ISR_TABLES @@ -136,7 +136,8 @@ SECTIONS *(.sdata2) *(.sdata2.*) *(.gnu.linkonce.s2.*) - + *libzephyr.a:mmu_hal.*(.rodata .rodata.*) + *libzephyr.a:rtc_clk.*(.rodata .rodata.*) KEEP(*(.jcr)) *(.dram1 .dram1.*) . = ALIGN(4); @@ -237,6 +238,10 @@ SECTIONS *libzephyr.a:esp_efuse_api_key_esp32xx.*(.literal .text .literal.* .text.*) *esp_mcuboot.*(.literal .text .literal.* .text.*) *esp_loader.*(.literal .text .literal.* .text.*) + *libzephyr.a:mmu_hal.*(.literal .text .literal.* .text.*) + *libzephyr.a:rtc_clk.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_clk_init.*(.literal .literal.* .text .text.*) + *libzephyr.a:rtc_time.*(.literal .literal.* .text .text.*) *(.fini.literal) *(.fini) *(.gnu.version) diff --git a/soc/espressif/esp32s2/soc.c b/soc/espressif/esp32s2/soc.c index 5e1ec21c075..0ff49920737 100644 --- a/soc/espressif/esp32s2/soc.c +++ b/soc/espressif/esp32s2/soc.c @@ -11,6 +11,13 @@ #include #include #include +#include +#include +#include +#if CONFIG_ESP_SPIRAM +#include +#include +#endif #include #include @@ -18,18 +25,16 @@ #include #include -#include "esp_private/system_internal.h" -#include "esp32s2/rom/cache.h" -#include "soc/gpio_periph.h" -#include "esp_spi_flash.h" -#include "esp_cpu.h" -#include "hal/cpu_ll.h" -#include "hal/soc_ll.h" -#include "hal/wdt_hal.h" -#include "esp_timer.h" -#include "esp_err.h" -#include "esp32s2/spiram.h" -#include "esp_clk_internal.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include #include #ifdef CONFIG_MCUBOOT @@ -54,43 +59,19 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) extern uint32_t _init_start; /* Move the exception vector table to IRAM. */ - __asm__ __volatile__ ( - "wsr %0, vecbase" - : - : "r"(&_init_start)); + __asm__ __volatile__("wsr %0, vecbase" : : "r"(&_init_start)); /* Zero out BSS */ z_bss_zero(); - /* - * Configure the mode of instruction cache : - * cache size, cache associated ways, cache line size. - */ - esp_config_instruction_cache_mode(); - - /* - * If we need use SPIRAM, we should use data cache, or if we want to - * access rodata, we also should use data cache. - * Configure the mode of data : cache size, cache associated ways, cache - * line size. - * Enable data cache, so if we don't use SPIRAM, it just works. - */ -#if CONFIG_ESP_SPIRAM - esp_config_data_cache_mode(); - esp_rom_Cache_Enable_DCache(0); -#endif - /* Disable normal interrupts. */ - __asm__ __volatile__ ( - "wsr %0, PS" - : - : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); + __asm__ __volatile__("wsr %0, PS" : : "r"(PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE)); /* Initialize the architecture CPU pointer. Some of the * initialization code wants a valid _current before * arch_kernel_init() is invoked. */ - __asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); + __asm__ __volatile__("wsr.MISC0 %0; rsync" : : "r"(&_kernel.cpus[0])); esp_reset_reason_init(); @@ -110,42 +91,67 @@ void __attribute__((section(".iram1"))) __esp_platform_start(void) wdt_hal_disable(&rtc_wdt_ctx); wdt_hal_write_protect_enable(&rtc_wdt_ctx); - /* Configures the CPU clock, RTC slow and fast clocks, and performs - * RTC slow clock calibration. + /* + * Configure the mode of instruction cache : + * cache size, cache associated ways, cache line size. */ - esp_clk_init(); + esp_config_instruction_cache_mode(); - esp_timer_early_init(); + /* + * If we need use SPIRAM, we should use data cache, or if we want to + * access rodata, we also should use data cache. + * Configure the mode of data : cache size, cache associated ways, cache + * line size. + * Enable data cache, so if we don't use SPIRAM, it just works. + */ + esp_config_data_cache_mode(); + esp_rom_Cache_Enable_DCache(0); + +#ifdef CONFIG_SOC_FLASH_ESP32 + esp_mspi_pin_init(); + spi_flash_init_chip_state(); +#endif /*CONFIG_SOC_FLASH_ESP32*/ + + esp_mmu_map_init(); #if CONFIG_ESP_SPIRAM - - memset(&_ext_ram_bss_start, - 0, - (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); - - esp_err_t err = esp_spiram_init(); + esp_err_t err = esp_psram_init(); if (err != ESP_OK) { printk("Failed to Initialize SPIRAM, aborting.\n"); abort(); } - esp_spiram_init_cache(); - if (esp_spiram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { + if (esp_psram_get_size() < CONFIG_ESP_SPIRAM_SIZE) { printk("SPIRAM size is less than configured size, aborting.\n"); abort(); } + if (esp_psram_is_initialized()) { + if (!esp_psram_extram_test()) { + printk("External RAM failed memory test!"); + abort(); + } + } + + memset(&_ext_ram_bss_start, 0, + (&_ext_ram_bss_end - &_ext_ram_bss_start) * sizeof(_ext_ram_bss_start)); + #endif /* CONFIG_ESP_SPIRAM */ -/* Scheduler is not started at this point. Hence, guard functions - * must be initialized after esp_spiram_init_cache which internally - * uses guard functions. Setting guard functions before SPIRAM - * cache initialization will result in a crash. - */ + /* Configures the CPU clock, RTC slow and fast clocks, and performs + * RTC slow clock calibration. + */ + esp_clk_init(); + esp_timer_early_init(); + + /* Scheduler is not started at this point. Hence, guard functions + * must be initialized after esp_spiram_init_cache which internally + * uses guard functions. Setting guard functions before SPIRAM + * cache initialization will result in a crash. + */ #if CONFIG_SOC_FLASH_ESP32 || CONFIG_ESP_SPIRAM spi_flash_guard_set(&g_flash_guard_default_ops); #endif - #endif /* CONFIG_MCUBOOT */ esp_intr_initialize(); @@ -169,60 +175,3 @@ void sys_arch_reboot(int type) { esp_restart_noos(); } - -void IRAM_ATTR esp_restart_noos(void) -{ - /* Disable interrupts */ - z_xt_ints_off(0xFFFFFFFF); - - /* - * Reset and stall the other CPU. - * CPU must be reset before stalling, in case it was running a s32c1i - * instruction. This would cause memory pool to be locked by arbiter - * to the stalled CPU, preventing current CPU from accessing this pool. - */ - const uint32_t core_id = cpu_ll_get_core_id(); - - /* Flush any data left in UART FIFOs */ - esp_rom_uart_tx_wait_idle(0); - esp_rom_uart_tx_wait_idle(1); - /* Disable cache */ - esp_rom_Cache_Disable_ICache(); - esp_rom_Cache_Disable_DCache(); - - /* - * 2nd stage bootloader reconfigures SPI flash signals. - * Reset them to the defaults expected by ROM - */ - WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); - WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); - - /* Reset wifi/ethernet/sdio (bb/mac) */ - DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, - DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST | DPORT_BT_RST | - DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_RST | - DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST | - DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST); - DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0); - - /* Reset timer/spi/uart */ - DPORT_SET_PERI_REG_MASK( - DPORT_PERIP_RST_EN_REG, - DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | - DPORT_SPI3_RST | DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | - DPORT_UART_RST); - DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0); - - /* Reset CPUs */ - if (core_id == 0) { - soc_ll_reset_core(0); - } - - while (true) { - ; - } -} diff --git a/soc/espressif/esp32s2/soc.h b/soc/espressif/esp32s2/soc.h index f7246ed6a2d..2edd0d12cc9 100644 --- a/soc/espressif/esp32s2/soc.h +++ b/soc/espressif/esp32s2/soc.h @@ -14,7 +14,7 @@ #include #include #include -#include +#include #include #include