michaelh/zephyr
1
0
Fork 0
Code Releases Activity

samples: drivers: mbox: Update mbox sample to work with nRF54L15

Browse source 
Update mbox sample configuration to work with production
board and SoC.

Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
This commit is contained in:
Karol Lasończyk 2024-08-22 15:11:02 +02:00 • committed by Carles Cufí
commit 070b1a4d41
9 changed files with 125 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
samples/drivers/mbox/CMakeLists.txt
View file

@ -22,6 +22,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUAPP OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUAPP OR
CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUAPP OR
CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M7)
message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as Main in this sample")
else()

1
samples/drivers/mbox/Kconfig.sysbuild
View file

@ -16,6 +16,7 @@ config REMOTE_BOARD
default "lpcxpresso55s69/lpc55s69/cpu1" if $(BOARD) = "lpcxpresso55s69"
default "nrf54h20dk/nrf54h20/cpuapp" if "$(BOARD)${BOARD_QUALIFIERS}" = "nrf54h20dk/nrf54h20/cpurad"
default "nrf54l15pdk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15pdk"
default "nrf54l15dk/nrf54l15/cpuflpr" if $(BOARD) = "nrf54l15dk"
default "stm32h747i_disco/stm32h747xx/m4" if $(BOARD) = "stm32h747i_disco"
default "esp32_devkitc_wroom/esp32/appcpu" if "$(BOARD)${BOARD_QUALIFIERS}" = "esp32_devkitc_wroom/esp32/procpu"
default "esp32s3_devkitm/esp32s3/appcpu" if "$(BOARD)${BOARD_QUALIFIERS}" = "esp32s3_devkitm/esp32s3/procpu"

20
samples/drivers/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay Normal file
View file

@ -0,0 +1,20 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuapp_vevif_rx 20>, <&cpuapp_vevif_tx 21>;
mbox-names = "rx", "tx";
};
};
&cpuapp_vevif_rx {
status = "okay";
};
&cpuapp_vevif_tx {
status = "okay";
};

1
samples/drivers/mbox/remote/CMakeLists.txt
View file

@ -22,6 +22,7 @@ if(CONFIG_BOARD_NRF5340DK_NRF5340_CPUNET OR
CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUFLPR OR
CONFIG_BOARD_NRF54L15PDK_NRF54L15_CPUFLPR_XIP OR
CONFIG_BOARD_NRF54L15DK_NRF54L15_CPUFLPR OR
CONFIG_BOARD_STM32H747I_DISCO_STM32H747XX_M4)
message(STATUS "${BOARD}${BOARD_QUALIFIERS} compile as remote in this sample")
else()

24
samples/drivers/mbox/remote/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay Normal file
View file

@ -0,0 +1,24 @@
/*
* Copyright 2024 Nordic Semiconductor ASA
* SPDX-License-Identifier: Apache-2.0
*/
/ {
mbox-consumer {
compatible = "vnd,mbox-consumer";
mboxes = <&cpuflpr_vevif_rx 21>, <&cpuflpr_vevif_tx 20>;
mbox-names = "rx", "tx";
};
};
&cpuflpr_vevif_rx {
status = "okay";
};
&cpuflpr_vevif_tx {
status = "okay";
};
&uart30 {
/delete-property/ hw-flow-control;
};

29
snippets/nordic-flpr-xip/boards/nrf54l15dk_nrf54l15_cpuapp.overlay Normal file
View file

@ -0,0 +1,29 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
};
};
&uart30 {
status = "reserved";
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_code_partition>;
};
&cpuapp_vevif_tx {
status = "okay";
};

3
snippets/nordic-flpr-xip/snippet.yml
View file

@ -6,6 +6,9 @@ boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54l15dk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
nrf54h20dk/nrf54h20/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay

43
snippets/nordic-flpr/boards/nrf54l15dk_nrf54l15_cpuapp.overlay Normal file
View file

@ -0,0 +1,43 @@
/*
* Copyright (c) 2024 Nordic Semiconductor
* SPDX-License-Identifier: Apache-2.0
*/
/ {
soc {
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
cpuflpr_code_partition: image@165000 {
/* FLPR core code partition */
reg = <0x165000 DT_SIZE_K(96)>;
};
};
cpuflpr_sram_code_data: memory@20028000 {
compatible = "mmio-sram";
reg = <0x20028000 DT_SIZE_K(96)>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20028000 0x18000>;
};
};
};
&uart30 {
status = "reserved";
};
&cpuapp_sram {
reg = <0x20000000 DT_SIZE_K(160)>;
ranges = <0x0 0x20000000 0x28000>;
};
&cpuflpr_vpr {
execution-memory = <&cpuflpr_sram_code_data>;
source-memory = <&cpuflpr_code_partition>;
};
&cpuapp_vevif_tx {
status = "okay";
};

3
snippets/nordic-flpr/snippet.yml
View file

@ -6,6 +6,9 @@ boards:
nrf54l15pdk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
nrf54l15dk/nrf54l15/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
nrf54h20dk/nrf54h20/cpuapp:
append:
EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay