samples: drivers: mbox: Update mbox sample to work with nRF54L15
Update mbox sample configuration to work with production board and SoC. Signed-off-by: Karol Lasończyk <karol.lasonczyk@nordicsemi.no>
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9 changed files with 125 additions and 0 deletions
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@ -0,0 +1,29 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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cpuflpr_code_partition: image@165000 {
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/* FLPR core code partition */
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reg = <0x165000 DT_SIZE_K(96)>;
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};
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};
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};
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};
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&uart30 {
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status = "reserved";
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};
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&cpuflpr_vpr {
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execution-memory = <&cpuflpr_code_partition>;
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};
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&cpuapp_vevif_tx {
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status = "okay";
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};
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@ -6,6 +6,9 @@ boards:
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nrf54l15pdk/nrf54l15/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
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nrf54l15dk/nrf54l15/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
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nrf54h20dk/nrf54h20/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay
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@ -0,0 +1,43 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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soc {
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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cpuflpr_code_partition: image@165000 {
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/* FLPR core code partition */
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reg = <0x165000 DT_SIZE_K(96)>;
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};
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};
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cpuflpr_sram_code_data: memory@20028000 {
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compatible = "mmio-sram";
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reg = <0x20028000 DT_SIZE_K(96)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20028000 0x18000>;
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};
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};
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};
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&uart30 {
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status = "reserved";
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};
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(160)>;
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ranges = <0x0 0x20000000 0x28000>;
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};
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&cpuflpr_vpr {
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execution-memory = <&cpuflpr_sram_code_data>;
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source-memory = <&cpuflpr_code_partition>;
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};
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&cpuapp_vevif_tx {
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status = "okay";
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};
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@ -6,6 +6,9 @@ boards:
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nrf54l15pdk/nrf54l15/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15pdk_nrf54l15_cpuapp.overlay
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nrf54l15dk/nrf54l15/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54l15dk_nrf54l15_cpuapp.overlay
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nrf54h20dk/nrf54h20/cpuapp:
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append:
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EXTRA_DTC_OVERLAY_FILE: boards/nrf54h20dk_nrf54h20_cpuapp.overlay
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