diff --git a/drivers/serial/uart_esp32.c b/drivers/serial/uart_esp32.c
index d70e071b065..14b2c70a12a 100644
--- a/drivers/serial/uart_esp32.c
+++ b/drivers/serial/uart_esp32.c
@@ -476,7 +476,7 @@ static const struct uart_driver_api uart_esp32_api = {
 ESP32_UART_IRQ_HANDLER_DECL(idx);						\
 static const struct uart_esp32_config uart_esp32_cfg_port_##idx = {		\
 	.dev_conf = {								\
-		.base = (u8_t *)DT_INST_##idx##_XTENSA_ESP32_UART_BASE_ADDRESS,	\
+		.base = (u8_t *)DT_INST_##idx##_ESPRESSIF_ESP32_UART_BASE_ADDRESS,	\
 		.sys_clk_freq = DT_INST_0_CADENCE_TENSILICA_XTENSA_LX6_CLOCK_FREQUENCY,	      \
 		ESP32_UART_IRQ_HANDLER_FUNC(idx)				\
 	},									\
@@ -494,10 +494,10 @@ static const struct uart_esp32_config uart_esp32_cfg_port_##idx = {		\
 	},									\
 										\
 	.pins = {								\
-		.tx = DT_INST_##idx##_XTENSA_ESP32_UART_TX_PIN,			\
-		.rx = DT_INST_##idx##_XTENSA_ESP32_UART_RX_PIN,			\
-		.rts = DT_INST_##idx##_XTENSA_ESP32_UART_RTS_PIN,		\
-		.cts = DT_INST_##idx##_XTENSA_ESP32_UART_CTS_PIN,		\
+		.tx = DT_INST_##idx##_ESPRESSIF_ESP32_UART_TX_PIN,		\
+		.rx = DT_INST_##idx##_ESPRESSIF_ESP32_UART_RX_PIN,		\
+		.rts = DT_INST_##idx##_ESPRESSIF_ESP32_UART_RTS_PIN,		\
+		.cts = DT_INST_##idx##_ESPRESSIF_ESP32_UART_CTS_PIN,		\
 	},									\
 										\
 	.irq = {								\
@@ -508,7 +508,7 @@ static const struct uart_esp32_config uart_esp32_cfg_port_##idx = {		\
 										\
 static struct uart_esp32_data uart_esp32_data_##idx = {				\
 	.uart_config = {							\
-		.baudrate = DT_INST_##idx##_XTENSA_ESP32_UART_CURRENT_SPEED,	\
+		.baudrate = DT_INST_##idx##_ESPRESSIF_ESP32_UART_CURRENT_SPEED,	\
 		.parity = UART_CFG_PARITY_NONE,					\
 		.stop_bits = UART_CFG_STOP_BITS_1,				\
 		.data_bits = UART_CFG_DATA_BITS_8,				\
@@ -517,7 +517,7 @@ static struct uart_esp32_data uart_esp32_data_##idx = {				\
 };										\
 										\
 DEVICE_AND_API_INIT(uart_esp32_##idx,						\
-		    DT_INST_##idx##_XTENSA_ESP32_UART_LABEL,			\
+		    DT_INST_##idx##_ESPRESSIF_ESP32_UART_LABEL,			\
 		    uart_esp32_init,						\
 		    &uart_esp32_data_##idx,					\
 		    &uart_esp32_cfg_port_##idx,					\
@@ -527,14 +527,14 @@ DEVICE_AND_API_INIT(uart_esp32_##idx,						\
 										\
 ESP32_UART_IRQ_HANDLER(idx)
 
-#ifdef DT_INST_0_XTENSA_ESP32_UART
+#ifdef DT_INST_0_ESPRESSIF_ESP32_UART
 ESP32_UART_INIT(0);
 #endif
 
-#ifdef DT_INST_1_XTENSA_ESP32_UART
+#ifdef DT_INST_1_ESPRESSIF_ESP32_UART
 ESP32_UART_INIT(1);
 #endif
 
-#ifdef DT_INST_2_XTENSA_ESP32_UART
+#ifdef DT_INST_2_ESPRESSIF_ESP32_UART
 ESP32_UART_INIT(2);
 #endif
diff --git a/dts/bindings/serial/xtensa,esp32-uart.yaml b/dts/bindings/serial/espressif,esp32-uart.yaml
similarity index 67%
rename from dts/bindings/serial/xtensa,esp32-uart.yaml
rename to dts/bindings/serial/espressif,esp32-uart.yaml
index 6f34c3c75d5..73442d8aa24 100644
--- a/dts/bindings/serial/xtensa,esp32-uart.yaml
+++ b/dts/bindings/serial/espressif,esp32-uart.yaml
@@ -3,7 +3,7 @@ title: ESP32 Uart
 description: >
     This binding gives a base representation of the ESP32 UART
 
-compatible: "xtensa,esp32-uart"
+compatible: "espressif,esp32-uart"
 
 include: uart-controller.yaml
 
@@ -12,27 +12,24 @@ properties:
       required: true
 
     interrupts:
-      category: optional
-
-    clocks:
-      category: required
+      required: false
 
     tx-pin:
       type: int
       description: TX pin
-      category: required
+      required: true
 
     rx-pin:
       type: int
       description: RX pin
-      category: required
+      required: true
 
     rts-pin:
       type: int
       description: RTS pin
-      category: optional
+      required: false
 
     cts-pin:
       type: int
       description: CTS pin
-      category: optional
+      required: false
diff --git a/dts/bindings/vendor-prefixes.txt b/dts/bindings/vendor-prefixes.txt
index f8cc9e22780..b175b8bb91a 100644
--- a/dts/bindings/vendor-prefixes.txt
+++ b/dts/bindings/vendor-prefixes.txt
@@ -454,7 +454,6 @@ x-powers	X-Powers
 xes	Extreme Engineering Solutions (X-ES)
 xillybus	Xillybus Ltd.
 xlnx	Xilinx
-xtensa The Tensilica Xtensa processor architecture
 xunlong	Shenzhen Xunlong Software CO.,Limited
 ysoft	Y Soft Corporation a.s.
 zarlink	Zarlink Semiconductor
diff --git a/dts/xtensa/espressif/esp32.dtsi b/dts/xtensa/espressif/esp32.dtsi
index 3a0546992a5..9d094c13454 100644
--- a/dts/xtensa/espressif/esp32.dtsi
+++ b/dts/xtensa/espressif/esp32.dtsi
@@ -32,7 +32,7 @@
 
 	soc {
 		uart0: uart@3ff40000 {
-			compatible = "xtensa,esp32-uart";
+			compatible = "espressif,esp32-uart";
 			reg = <0x3ff40000 0x400>;
 			/* interrupts = <12>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
 			label = "UART_0";
@@ -40,7 +40,7 @@
 		};
 
 		uart1: uart@3ff50000 {
-			compatible = "xtensa,esp32-uart";
+			compatible = "espressif,esp32-uart";
 			reg = <0x3ff50000 0x400>;
 			/* interrupts = <17>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
 			label = "UART_1";
@@ -48,7 +48,7 @@
 		};
 
 		uart2: uart@3ff6e000 {
-			compatible = "xtensa,esp32-uart";
+			compatible = "espressif,esp32-uart";
 			reg = <0x3ff6E000 0x400>;
 			/* interrupts = <18>; - FIXME: Enable interrupts when interrupt-controller got supported in device tree */
 			label = "UART_2";