tests: kernel: interrupt: Explain Cortex-M nested interrupt priorities

This commit adds an explanation comment for the interrupt priorities
used by the Cortex-M nested interrupt test.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
This commit is contained in:
Stephanos Ioannidis 2020-03-28 23:30:10 +09:00 committed by Ioannis Glaropoulos
commit 06e3e40c0c

View file

@ -24,7 +24,10 @@
#if defined(CONFIG_CPU_CORTEX_M)
/*
* For Cortex-M NVIC, unused and available IRQs are automatically detected when
* when the test is run.
* the test is run.
*
* The IRQ priorities start at 1 because the priority 0 is reserved for the
* SVCall exception and Zero-Latency IRQs (see `_EXCEPTION_RESERVED_PRIO`).
*/
#define IRQ0_PRIO 2
#define IRQ1_PRIO 1