tests: kernel: interrupt: Explain Cortex-M nested interrupt priorities
This commit adds an explanation comment for the interrupt priorities used by the Cortex-M nested interrupt test. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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@ -24,7 +24,10 @@
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#if defined(CONFIG_CPU_CORTEX_M)
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#if defined(CONFIG_CPU_CORTEX_M)
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/*
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/*
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* For Cortex-M NVIC, unused and available IRQs are automatically detected when
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* For Cortex-M NVIC, unused and available IRQs are automatically detected when
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* when the test is run.
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* the test is run.
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*
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* The IRQ priorities start at 1 because the priority 0 is reserved for the
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* SVCall exception and Zero-Latency IRQs (see `_EXCEPTION_RESERVED_PRIO`).
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*/
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*/
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#define IRQ0_PRIO 2
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#define IRQ0_PRIO 2
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#define IRQ1_PRIO 1
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#define IRQ1_PRIO 1
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