dts: mps2_an385: Add ARM CMSDK support
This patch adds device tree support for ARM CMSDK IPs on MPS2 AN385. Signed-off-by: Vincenzo Frascino <vincenzo.frascino@linaro.org>
This commit is contained in:
Vincenzo Frascino
Kumar Gala
parent
df3cec7641
commit
051da9fd4a
3 changed files with 85 additions and 55 deletions
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@ -10,56 +10,6 @@
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#include <soc_memory_map.h>
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#include <soc_irq.h>
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#if defined(CONFIG_GPIO)
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/* CMSDK AHB General Purpose Input/Output (GPIO) */
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#define CMSDK_AHB_GPIO0 GPIO_0_BASE_ADDR
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#define IRQ_PORT0_ALL IRQ_GPIO_0_COMBINED
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#define CMSDK_AHB_GPIO1 GPIO_1_BASE_ADDR
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#define IRQ_PORT1_ALL IRQ_GPIO_1_COMBINED
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#define CMSDK_AHB_GPIO2 GPIO_2_BASE_ADDR
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#define IRQ_PORT2_ALL IRQ_GPIO_2_COMBINED
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#define CMSDK_AHB_GPIO3 GPIO_3_BASE_ADDR
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#define IRQ_PORT3_ALL IRQ_GPIO_3_COMBINED
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#endif /* CONFIG_GPIO */
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#if defined(CONFIG_UART_CMSDK_APB)
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/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
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#define CMSDK_APB_UART0 UART_0_BASE_ADDR
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#define CMSDK_APB_UART1 UART_1_BASE_ADDR
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#define CMSDK_APB_UART2 UART_2_BASE_ADDR
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#define CMSDK_APB_UART3 UART_3_BASE_ADDR
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#define CMSDK_APB_UART4 UART_4_BASE_ADDR
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#ifndef CONFIG_HAS_DTS
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#define CMSDK_APB_UART_0_IRQ_TX IRQ_UART_0_TX
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#define CMSDK_APB_UART_0_IRQ_RX IRQ_UART_0_RX
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#define CMSDK_APB_UART_1_IRQ_TX IRQ_UART_1_TX
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#define CMSDK_APB_UART_1_IRQ_RX IRQ_UART_1_RX
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#define CMSDK_APB_UART_2_IRQ_TX IRQ_UART_2_TX
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#define CMSDK_APB_UART_2_IRQ_RX IRQ_UART_2_RX
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#define CMSDK_APB_UART_3_IRQ_TX IRQ_UART_3_TX
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#define CMSDK_APB_UART_3_IRQ_RX IRQ_UART_3_RX
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#define CMSDK_APB_UART_4_IRQ_TX IRQ_UART_4_TX
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#define CMSDK_APB_UART_4_IRQ_RX IRQ_UART_4_RX
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#endif
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#endif /* CONFIG_UART_CMSDK_APB */
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#if defined(CONFIG_WATCHDOG)
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/* CMSDK APB Watchdog */
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#define CMSDK_APB_WDOG WDOG_BASE_ADDR
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#endif /* CONFIG_WATCHDOG */
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#if defined(CONFIG_COUNTER)
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/* CMSDK APB Timers */
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#define CMSDK_APB_TIMER0 TIMER_0_BASE_ADDR
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#define CMSDK_APB_TIMER_0_IRQ IRQ_TIMER_0
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#define CMSDK_APB_TIMER1 TIMER_1_BASE_ADDR
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#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER_1
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/* CMSDK APB Dual Timer */
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#define CMSDK_APB_DTIMER DTIMER_BASE_ADDR
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#define CMSDK_APB_DUALTIMER_IRQ IRQ_DUAL_TIMER
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#endif /* CONFIG_COUNTER */
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#if defined(CONFIG_I2C_SBCON)
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#define I2C_SBCON_0_BASE_ADDR I2C_TOUCH_BASE_ADDR
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#define I2C_SBCON_1_BASE_ADDR I2C_AUDIO_CONF_BASE_ADDR
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@ -30,40 +30,87 @@
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};
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soc {
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timer0: timer@40000000 {
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compatible = "arm,cmsdk-timer";
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reg = <0x40000000 0x1000>;
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interrupts = <IRQ_TIMER_0 3>;
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};
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timer1: timer@40001000 {
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compatible = "arm,cmsdk-timer";
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reg = <0x40001000 0x1000>;
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interrupts = <IRQ_TIMER_1 3>;
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};
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dtimer0: dtimer@40002000 {
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compatible = "arm,cmsdk-dtimer";
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reg = <0x40000000 0x1000>;
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interrupts = <IRQ_DUAL_TIMER 3>;
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};
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uart0: uart@40004000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40004000 0x14>;
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reg = <0x40004000 0x1000>;
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interrupts = <IRQ_UART_0_TX 3 IRQ_UART_0_RX 3>;
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current-speed = <115200>;
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};
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uart1: uart@40005000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40005000 0x14>;
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reg = <0x40005000 0x1000>;
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interrupts = <IRQ_UART_1_TX 3 IRQ_UART_1_RX 3>;
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current-speed = <115200>;
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};
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uart2: uart@40006000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40006000 0x14>;
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reg = <0x40006000 0x1000>;
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interrupts = <IRQ_UART_2_TX 3 IRQ_UART_2_RX 3>;
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current-speed = <115200>;
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};
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uart3: uart@40007000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40007000 0x14>;
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reg = <0x40007000 0x1000>;
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interrupts = <IRQ_UART_3_TX 3 IRQ_UART_3_RX 3>;
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current-speed = <115200>;
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};
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wdog0: wdog@40008000 {
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compatible = "arm,cmsdk-watchdog";
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reg = <0x40008000 0x1000>;
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};
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uart4: uart@40009000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x40009000 0x14>;
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reg = <0x40009000 0x1000>;
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interrupts = <IRQ_UART_4_TX 3 IRQ_UART_4_RX 3>;
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current-speed = <115200>;
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};
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gpio0: gpio@40010000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40010000 0x1000>;
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interrupts = <IRQ_GPIO_0_COMBINED 3>;
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};
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gpio1: gpio@40011000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40011000 0x1000>;
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interrupts = <IRQ_GPIO_1_COMBINED 3>;
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};
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gpio2: gpio@40012000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40012000 0x1000>;
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interrupts = <IRQ_GPIO_2_COMBINED 3>;
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};
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gpio3: gpio@40013000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x40013000 0x1000>;
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interrupts = <IRQ_GPIO_3_COMBINED 3>;
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};
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};
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};
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@ -1,26 +1,59 @@
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#define CONFIG_NUM_IRQ_PRIO_BITS ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
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/* CMSDK APB Timers */
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#define CMSDK_APB_TIMER0 ARM_CMSDK_TIMER_40000000_BASE_ADDRESS_0
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#define CMSDK_APB_TIMER_0_IRQ ARM_CMSDK_TIMER_40000000_IRQ_0
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#define CMSDK_APB_TIMER1 ARM_CMSDK_TIMER_40001000_BASE_ADDRESS_0
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#define CMSDK_APB_TIMER_1_IRQ IRQ_TIMER1 ARM_CMSDK_TIMER_40001000_IRQ_0
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/* CMSDK APB Dual Timer */
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#define CMSDK_APB_DTIMER ARM_CMSDK_DTIMER_40002000_BASE_ADDRESS_0
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#define CMSDK_APB_DUALTIMER_IRQ ARM_CMSDK_DTIMER_40002000_IRQ_0
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/* CMSDK APB Universal Asynchronous Receiver-Transmitter (UART) */
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#define CMSDK_APB_UART0 ARM_CMSDK_UART_40004000_BASE_ADDRESS_0
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#define CMSDK_APB_UART_0_IRQ_TX ARM_CMSDK_UART_40004000_IRQ_0
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#define CMSDK_APB_UART_0_IRQ_RX ARM_CMSDK_UART_40004000_IRQ_1
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#define CONFIG_UART_CMSDK_APB_PORT0_IRQ_PRI ARM_CMSDK_UART_40004000_IRQ_0_PRIORITY
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#define CONFIG_UART_CMSDK_APB_PORT0_BAUD_RATE ARM_CMSDK_UART_40004000_CURRENT_SPEED
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#define CMSDK_APB_UART1 ARM_CMSDK_UART_40005000_BASE_ADDRESS_0
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#define CMSDK_APB_UART_1_IRQ_TX ARM_CMSDK_UART_40005000_IRQ_0
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#define CMSDK_APB_UART_1_IRQ_RX ARM_CMSDK_UART_40005000_IRQ_1
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#define CONFIG_UART_CMSDK_APB_PORT1_IRQ_PRI ARM_CMSDK_UART_40005000_IRQ_0_PRIORITY
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#define CONFIG_UART_CMSDK_APB_PORT1_BAUD_RATE ARM_CMSDK_UART_40005000_CURRENT_SPEED
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#define CMSDK_APB_UART2 ARM_CMSDK_UART_40006000_BASE_ADDRESS_0
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#define CMSDK_APB_UART_2_IRQ_TX ARM_CMSDK_UART_40006000_IRQ_0
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#define CMSDK_APB_UART_2_IRQ_RX ARM_CMSDK_UART_40006000_IRQ_1
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#define CONFIG_UART_CMSDK_APB_PORT2_IRQ_PRI ARM_CMSDK_UART_40006000_IRQ_0_PRIORITY
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#define CONFIG_UART_CMSDK_APB_PORT2_BAUD_RATE ARM_CMSDK_UART_40006000_CURRENT_SPEED
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#define CMSDK_APB_UART3 ARM_CMSDK_UART_40007000_BASE_ADDRESS_0
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#define CMSDK_APB_UART_3_IRQ_TX ARM_CMSDK_UART_40007000_IRQ_0
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#define CMSDK_APB_UART_3_IRQ_RX ARM_CMSDK_UART_40007000_IRQ_1
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#define CONFIG_UART_CMSDK_APB_PORT3_IRQ_PRI ARM_CMSDK_UART_40007000_IRQ_0_PRIORITY
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#define CONFIG_UART_CMSDK_APB_PORT3_BAUD_RATE ARM_CMSDK_UART_40007000_CURRENT_SPEED
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#define CMSDK_APB_UART4 ARM_CMSDK_UART_40009000_BASE_ADDRESS_0
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#define CMSDK_APB_UART_4_IRQ_TX ARM_CMSDK_UART_40009000_IRQ_0
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#define CMSDK_APB_UART_4_IRQ_RX ARM_CMSDK_UART_40009000_IRQ_1
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#define CONFIG_UART_CMSDK_APB_PORT4_IRQ_PRI ARM_CMSDK_UART_40009000_IRQ_0_PRIORITY
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#define CONFIG_UART_CMSDK_APB_PORT4_BAUD_RATE ARM_CMSDK_UART_40009000_CURRENT_SPEED
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/* CMSDK APB Watchdog */
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#define CMSDK_APB_WDOG ARM_CMSDK_WATCHDOG_40008000_BASE_ADDRESS_0
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/* CMSDK AHB General Purpose Input/Output (GPIO) */
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#define CMSDK_AHB_GPIO0 ARM_CMSDK_GPIO_40010000_BASE_ADDRESS_0
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#define IRQ_PORT0_ALL ARM_CMSDK_GPIO_40010000_IRQ_0
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#define CMSDK_AHB_GPIO1 ARM_CMSDK_GPIO_40011000_BASE_ADDRESS_0
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#define IRQ_PORT1_ALL ARM_CMSDK_GPIO_40011000_IRQ_0
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#define CMSDK_AHB_GPIO2 ARM_CMSDK_GPIO_40012000_BASE_ADDRESS_0
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#define IRQ_PORT2_ALL ARM_CMSDK_GPIO_40012000_IRQ_0
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#define CMSDK_AHB_GPIO3 ARM_CMSDK_GPIO_40013000_BASE_ADDRESS_0
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#define IRQ_PORT3_ALL ARM_CMSDK_GPIO_40013000_IRQ_0
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