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boards: nxp: imx95_evk_mimx9596_m7: enable SPI1 interface

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Enabled SPI1 interface for imx95_evk_mimx9596_m7.

Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
This commit is contained in:
Yangbo Lu 2025-01-07 12:22:26 +08:00 • committed by Benjamin Cabé
commit 04c63996e1
3 changed files with 15 additions and 0 deletions
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8
boards/nxp/imx95_evk/doc/index.rst
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@ -92,6 +92,8 @@ The Zephyr ``imx95_evk/mimx9596/m7`` board target supports the following hardwar
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| TPM | on-chip | tpm | | TPM | on-chip | tpm |
+-----------+------------+-------------------------------------+ +-----------+------------+-------------------------------------+
| SPI | on-chip | spi |
+-----------+------------+-------------------------------------+
The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support The Zephyr ``imx95_evk/mimx9596/a55`` and ``imx95_evk/mimx9596/a55/smp`` board targets support
the following hardware features: the following hardware features:
@ -133,6 +135,12 @@ oscilloscope.
Channel 2 signal routed to resistance R881. Channel 2 signal routed to resistance R881.
Channel 3 signal routed to resistance R882. Channel 3 signal routed to resistance R882.
SPI
---
The EVK board need to be reworked to solder R1217/R1218/R1219/R1220 with 0R resistances.
SPI1 on J35 is enabled for M7.
Programming and Debugging (A55) Programming and Debugging (A55)
******************************* *******************************

6
boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.dts
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@ -35,6 +35,12 @@
status = "okay"; status = "okay";
}; };
&lpspi1 {
pinctrl-0 = <&lpspi1_default>;
pinctrl-names = "default";
status = "okay";
};
&lpuart3 { &lpuart3 {
status = "okay"; status = "okay";
current-speed = <115200>; current-speed = <115200>;

1
boards/nxp/imx95_evk/imx95_evk_mimx9596_m7.yaml
View file

@ -17,4 +17,5 @@ supported:
- uart - uart
- i2c - i2c
- pwm - pwm
- spi
vendor: nxp vendor: nxp