drivers/ethernet: stm32: Get static boot configuration from dts
Update stm32 ethernet driver to get basic boot configuration from device tree. So far information are: - Label - Base address - IRQ number and prio - Clock settings Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
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e8f1c17e79
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04c1fcfde6
2 changed files with 20 additions and 17 deletions
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@ -4,6 +4,8 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT st_stm32_ethernet
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#define LOG_MODULE_NAME eth_stm32_hal
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#define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
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@ -50,11 +52,6 @@ LOG_MODULE_REGISTER(LOG_MODULE_NAME);
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#define ETH_MEDIA_INTERFACE_MII HAL_ETH_MII_MODE
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#define ETH_MEDIA_INTERFACE_RMII HAL_ETH_RMII_MODE
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#define LL_AHB1_GRP1_PERIPH_ETHMAC LL_AHB1_GRP1_PERIPH_ETH1MAC
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#define LL_AHB1_GRP1_PERIPH_ETHMACTX LL_AHB1_GRP1_PERIPH_ETH1TX
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#define LL_AHB1_GRP1_PERIPH_ETHMACRX LL_AHB1_GRP1_PERIPH_ETH1RX
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#define LL_AHB1_GRP1_PERIPH_ETHMACPTP LL_AHB1_GRP1_PERIPH_ETH1MAC
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#define ETH_DMA_TRANSMIT_TIMEOUT 20U /* transmit timeout in sys tiks */
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#else
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@ -534,8 +531,10 @@ static int eth_initialize(struct device *dev)
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(clock_control_subsys_t *)&cfg->pclken_tx);
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ret |= clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken_rx);
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#if !defined(CONFIG_SOC_SERIES_STM32H7X)
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ret |= clock_control_on(dev_data->clock,
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(clock_control_subsys_t *)&cfg->pclken_ptp);
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#endif /* !defined(CONFIG_SOC_SERIES_STM32H7X) */
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if (ret) {
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LOG_ERR("Failed to enable ethernet clock");
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@ -730,26 +729,28 @@ DEVICE_DECLARE(eth0_stm32_hal);
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static void eth0_irq_config(void)
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{
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IRQ_CONNECT(ETH_IRQn, CONFIG_ETH_STM32_HAL_IRQ_PRI, eth_isr,
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IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority), eth_isr,
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DEVICE_GET(eth0_stm32_hal), 0);
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irq_enable(ETH_IRQn);
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irq_enable(DT_INST_IRQN(0));
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}
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static const struct eth_stm32_hal_dev_cfg eth0_config = {
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.config_func = eth0_irq_config,
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.pclken = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMAC },
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.pclken_tx = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACTX },
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.pclken_rx = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACRX },
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.pclken_ptp = { .bus = STM32_CLOCK_BUS_AHB1,
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.enr = LL_AHB1_GRP1_PERIPH_ETHMACPTP },
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.pclken = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, stmmaceth, bits)},
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.pclken_tx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_tx, bits)},
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.pclken_rx = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_rx, bits)},
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#if !defined(CONFIG_SOC_SERIES_STM32H7X)
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.pclken_ptp = {.bus = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bus),
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.enr = DT_INST_CLOCKS_CELL_BY_NAME(0, mac_clk_ptp, bits)},
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#endif /* !CONFIG_SOC_SERIES_STM32H7X */
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};
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static struct eth_stm32_hal_dev_data eth0_data = {
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.heth = {
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.Instance = ETH,
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.Instance = (ETH_TypeDef *)DT_INST_REG_ADDR(0),
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.Init = {
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#if !defined(CONFIG_SOC_SERIES_STM32H7X)
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.AutoNegotiation = ETH_AUTONEGOTIATION_ENABLE,
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@ -776,6 +777,6 @@ static struct eth_stm32_hal_dev_data eth0_data = {
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},
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};
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ETH_NET_DEVICE_INIT(eth0_stm32_hal, CONFIG_ETH_STM32_HAL_NAME, eth_initialize,
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ETH_NET_DEVICE_INIT(eth0_stm32_hal, DT_INST_LABEL(0), eth_initialize,
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device_pm_control_nop, ð0_data, ð0_config,
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CONFIG_ETH_INIT_PRIORITY, ð_api, ETH_STM32_HAL_MTU);
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@ -26,7 +26,9 @@ struct eth_stm32_hal_dev_cfg {
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struct stm32_pclken pclken;
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struct stm32_pclken pclken_rx;
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struct stm32_pclken pclken_tx;
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#if !defined(CONFIG_SOC_SERIES_STM32H7X)
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struct stm32_pclken pclken_ptp;
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#endif /* !defined(CONFIG_SOC_SERIES_STM32H7X) */
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};
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/* Device run time data */
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