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riscv: make core code 64-bit compatible

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There are two aspects to this: CPU registers are twice as big, and the
load and store instructions must use the 'd' suffix instead of the 'w'
one. To abstract register differences, we simply use a ulong_t instead
of u32_t given that RISC-V is either ILP32 or LP64. And the relevant
lw/sw instructions are replaced by LR/SR (load/store register) that get
defined as either lw/sw or ld/sd. Finally a few constants to deal with
register offsets are also provided.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This commit is contained in:
Nicolas Pitre 2019-07-24 16:21:58 -04:00 • committed by Andrew Boie
commit 0440a815a9
10 changed files with 234 additions and 212 deletions
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17
include/arch/riscv/arch.h
View file

@ -31,6 +31,18 @@ extern "C" {
/* stacks, for RISCV architecture stack should be 16byte-aligned */
#define STACK_ALIGN 16
#ifdef CONFIG_64BIT
#define LR ld
#define SR sd
#define RV_REGSIZE 8
#define RV_REGSHIFT 3
#else
#define LR lw
#define SR sw
#define RV_REGSIZE 4
#define RV_REGSHIFT 2
#endif
#ifndef _ASMLANGUAGE
#include <sys/util.h>
@ -91,7 +103,8 @@ void z_irq_spurious(void *unused);
*/
static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
{
unsigned int key, mstatus;
unsigned int key;
ulong_t mstatus;
__asm__ volatile ("csrrc %0, mstatus, %1"
: "=r" (mstatus)
@ -108,7 +121,7 @@ static ALWAYS_INLINE unsigned int z_arch_irq_lock(void)
*/
static ALWAYS_INLINE void z_arch_irq_unlock(unsigned int key)
{
unsigned int mstatus;
ulong_t mstatus;
__asm__ volatile ("csrrs %0, mstatus, %1"
: "=r" (mstatus)

40
include/arch/riscv/exp.h
View file

@ -42,29 +42,29 @@ struct soc_esf {
#endif
struct __esf {
u32_t ra; /* return address */
u32_t gp; /* global pointer */
u32_t tp; /* thread pointer */
ulong_t ra; /* return address */
ulong_t gp; /* global pointer */
ulong_t tp; /* thread pointer */
u32_t t0; /* Caller-saved temporary register */
u32_t t1; /* Caller-saved temporary register */
u32_t t2; /* Caller-saved temporary register */
u32_t t3; /* Caller-saved temporary register */
u32_t t4; /* Caller-saved temporary register */
u32_t t5; /* Caller-saved temporary register */
u32_t t6; /* Caller-saved temporary register */
ulong_t t0; /* Caller-saved temporary register */
ulong_t t1; /* Caller-saved temporary register */
ulong_t t2; /* Caller-saved temporary register */
ulong_t t3; /* Caller-saved temporary register */
ulong_t t4; /* Caller-saved temporary register */
ulong_t t5; /* Caller-saved temporary register */
ulong_t t6; /* Caller-saved temporary register */
u32_t a0; /* function argument/return value */
u32_t a1; /* function argument */
u32_t a2; /* function argument */
u32_t a3; /* function argument */
u32_t a4; /* function argument */
u32_t a5; /* function argument */
u32_t a6; /* function argument */
u32_t a7; /* function argument */
ulong_t a0; /* function argument/return value */
ulong_t a1; /* function argument */
ulong_t a2; /* function argument */
ulong_t a3; /* function argument */
ulong_t a4; /* function argument */
ulong_t a5; /* function argument */
ulong_t a6; /* function argument */
ulong_t a7; /* function argument */
u32_t mepc; /* machine exception program counter */
u32_t mstatus; /* machine status register */
ulong_t mepc; /* machine exception program counter */
ulong_t mstatus; /* machine status register */
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
struct soc_esf soc_context;