boards: nxp: add configuration for MIPI-DSI and LCDIF on mimxrt700_evk

1.Add clock configuration for DCNano LCDIF video and
command mode.
2.Update board dts file

Signed-off-by: Kate Wang <yumeng.wang@nxp.com>

boards/nxp/mimxrt700_evk/board.c

@@ -441,6 +441,62 @@ void board_early_init_hook(void)
 #if DT_NODE_HAS_STATUS(DT_NODELABEL(sc_timer), okay)
 	CLOCK_AttachClk(kFRO0_DIV6_to_SCT);
 #endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_dcnano_lcdif, okay) && \
+	CONFIG_DISPLAY
+	/* Assert LCDIF reset. */
+	RESET_SetPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+
+	/* Disable media main and LCDIF power down. */
+	POWER_DisablePD(kPDRUNCFG_SHUT_MEDIA_MAINCLK);
+	POWER_DisablePD(kPDRUNCFG_APD_LCDIF);
+	POWER_DisablePD(kPDRUNCFG_PPD_LCDIF);
+
+	/* Apply power down configuration. */
+	POWER_ApplyPD();
+
+	CLOCK_AttachClk(kMAIN_PLL_PFD2_to_LCDIF);
+	/* Note- pixel clock follows formula
+	 * (height  VSW  VFP  VBP) * (width  HSW  HFP  HBP) * frame rate.
+	 * this means the clock divider will vary depending on
+	 * the attached display.
+	 *
+	 * The root clock used here is the main PLL (PLL PFD2).
+	 */
+	CLOCK_SetClkDiv(
+		kCLOCK_DivLcdifClk,
+		(CLOCK_GetMainPfdFreq(kCLOCK_Pfd2) /
+		  DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings), clock_frequency)));
+
+	CLOCK_EnableClock(kCLOCK_Lcdif);
+
+	/* Clear LCDIF reset. */
+	RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+#endif
+
+#if DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lcdif), nxp_mipi_dbi_dcnano_lcdif, okay)
+	/* Assert LCDIF reset. */
+	RESET_SetPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+
+	/* Disable media main and LCDIF power down. */
+	POWER_DisablePD(kPDRUNCFG_SHUT_MEDIA_MAINCLK);
+	POWER_DisablePD(kPDRUNCFG_APD_LCDIF);
+	POWER_DisablePD(kPDRUNCFG_PPD_LCDIF);
+
+	/* Apply power down configuration. */
+	POWER_ApplyPD();
+
+	/* Calculate the divider for MEDIA MAIN clock source main pll pfd2. */
+	CLOCK_InitMainPfd(kCLOCK_Pfd2, (uint64_t)CLOCK_GetMainPllFreq() * 18UL /
+						DT_PROP(DT_NODELABEL(lcdif), clock_frequency));
+	CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 1U);
+	CLOCK_AttachClk(kMAIN_PLL_PFD2_to_MEDIA_MAIN);
+
+	CLOCK_EnableClock(kCLOCK_Lcdif);
+
+	/* Clear LCDIF reset. */
+	RESET_ClearPeripheralReset(kLCDIF_RST_SHIFT_RSTn);
+#endif
 }
 
 static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx)

boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts

@@ -30,6 +30,7 @@
 		zephyr,sram = &sram0;
 		zephyr,console = &flexcomm0_lpuart0;
 		zephyr,shell-uart = &flexcomm0_lpuart0;
+		zephyr,display = &lcdif;
 	};
 
 	leds {
@@ -57,6 +58,35 @@
 			zephyr,code = <INPUT_KEY_1>;
 		};
 	};
+
+	/*
+	 * This node describes the GPIO pins of the MIPI FPC interface,
+	 * J50 on the EVK. This interface is standard to several
+	 * NXP EVKs, and is used with several MIPI displays
+	 * (available as zephyr shields)
+	 */
+	nxp_mipi_connector: mipi-connector {
+		compatible = "gpio-nexus";
+		#gpio-cells = <2>;
+		gpio-map-mask = <0xffffffff 0xffffffc0>;
+		gpio-map-pass-thru = <0 0x3f>;
+		gpio-map =	<0  0 &gpio1 14 0>,	/* Pin 1, LEDK */
+					<21 0 &gpio3 4 0>,	/* Pin 21, RESET */
+					<22 0 &gpio3 5 0>,	/* Pin 22, LPTE */
+					<26 0 &gpio0 6 0>,	/* Pin 26, CTP_I2C SDA */
+					<27 0 &gpio0 7 0>,	/* Pin 27, CTP_I2C SCL */
+					<28 0 &gpio3 8 0>,	/* Pin 28, CTP_RST */
+					<29 0 &gpio1 13 0>,	/* Pin 29, CTP_INT */
+					<32 0 &gpio1 10 0>,	/* Pin 32, PWR_EN */
+					<34 0 &gpio1 14 0>;	/* Pin 34, BL_PWM */
+	};
+
+	en_mipi_display: enable-mipi-display {
+		compatible = "regulator-fixed";
+		regulator-name = "en_mipi_display";
+		enable-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+	};
 };
 
 &ctimer0 {
@@ -107,6 +137,12 @@
 	clock-frequency = <I2C_BITRATE_STANDARD>;
 };
 
+nxp_mipi_i2c: &flexcomm8_lpi2c8 {};
+
+zephyr_mipi_dsi: &mipi_dsi {};
+
+zephyr_lcdif: &lcdif {};
+
 &gpio0 {
 	status = "okay";
 };
@@ -115,6 +151,14 @@
 	status = "okay";
 };
 
+&gpio2 {
+	status = "okay";
+};
+
+&gpio3 {
+	status = "okay";
+};
+
 &green_led {
 	status = "okay";
 };