michaelh/zephyr
1
0
Fork 0
Code Releases Activity

drivers: intc_gicv3: use BIT64_MASK instead of BIT_MASK

Browse source 
On 32bit compiler the BIT_MASK(32) generate a warning,
after discussion on #42226 and #42163, advise was to use
BIT64_MASK instead.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
This commit is contained in:
Julien Massot 2022-03-09 10:03:34 +01:00 • committed by Carles Cufí
commit 03dffa5434
1 changed files with 6 additions and 6 deletions
Download patch file Download diff file Expand all files Collapse all files

12
drivers/interrupt_controller/intc_gicv3.c
View file

@ -328,19 +328,19 @@ static void gicv3_cpuif_init(void)
mem_addr_t base = gic_get_rdist() + GICR_SGI_BASE_OFF; mem_addr_t base = gic_get_rdist() + GICR_SGI_BASE_OFF;
/* Disable all sgi ppi */ /* Disable all sgi ppi */
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0)); sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICENABLER(base, 0));
/* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */ /* Any sgi/ppi intid ie. 0-31 will select GICR_CTRL */
gic_wait_rwp(0); gic_wait_rwp(0);
/* Clear pending */ /* Clear pending */
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0)); sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), ICPENDR(base, 0));
/* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr /* Configure all SGIs/PPIs as G1S or G1NS depending on Zephyr
* is run in EL1S or EL1NS respectively. * is run in EL1S or EL1NS respectively.
* All interrupts will be delivered as irq * All interrupts will be delivered as irq
*/ */
sys_write32(IGROUPR_VAL, IGROUPR(base, 0)); sys_write32(IGROUPR_VAL, IGROUPR(base, 0));
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0)); sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG), IGROUPMODR(base, 0));
/* /*
* Configure default priorities for SGI 0:15 and PPI 0:15. * Configure default priorities for SGI 0:15 and PPI 0:15.
@ -411,13 +411,13 @@ static void gicv3_dist_init(void)
intid += GIC_NUM_INTR_PER_REG) { intid += GIC_NUM_INTR_PER_REG) {
idx = intid / GIC_NUM_INTR_PER_REG; idx = intid / GIC_NUM_INTR_PER_REG;
/* Disable interrupt */ /* Disable interrupt */
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
ICENABLER(base, idx)); ICENABLER(base, idx));
/* Clear pending */ /* Clear pending */
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
ICPENDR(base, idx)); ICPENDR(base, idx));
sys_write32(IGROUPR_VAL, IGROUPR(base, idx)); sys_write32(IGROUPR_VAL, IGROUPR(base, idx));
sys_write32(BIT_MASK(GIC_NUM_INTR_PER_REG), sys_write32(BIT64_MASK(GIC_NUM_INTR_PER_REG),
IGROUPMODR(base, idx)); IGROUPMODR(base, idx));
} }