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arch/xtensa: "NMILEVEL" is an optional feature

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Some oddballs cores can be generated without an "NMI" interrupt, in
which case core-isa.h will not define XCHAL_NMILEVEL.  This code is
trying to unconditionally mask interrupts, so XCHAL_EXCM_LEVEL is the
pedantically correct choice anyway (NMI's by definition, cannot be
masked).

Signed-off-by: Andy Ross <andyross@google.com>
This commit is contained in:
Andy Ross 2024-05-13 17:38:53 -07:00 • committed by Anas Nashif
commit 03cafbdaef
1 changed files with 1 additions and 1 deletions
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2
arch/xtensa/core/vector_handlers.c
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@ -364,7 +364,7 @@ void *xtensa_excint1_c(int *interrupted_stack)
* thread.
*/
__asm__ volatile("rsil %0, %1"
: "=r" (ignore) : "i"(XCHAL_NMILEVEL));
: "=r" (ignore) : "i"(XCHAL_EXCM_LEVEL));
_current_cpu->nested = 1;
}