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drivers: clock_stm32: add APB3 support for STM32WL

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STM32WL series have an extra APB3 bus with the SUBGHZSPI device on it.
Add the relevant code to enable and disable that clock, and to obtain
the actual clock rate. This is enough to run the STM32 SPI driver
against it.

Signed-off-by: Fabio Baltieri <fabio.baltieri@gmail.com>
This commit is contained in:
Fabio Baltieri 2021-05-05 23:24:04 +01:00 • committed by Carles Cufí
commit 03adc1e2bb
1 changed files with 23 additions and 0 deletions
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23
drivers/clock_control/clock_stm32_ll_common.c
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@ -154,6 +154,11 @@ static inline int stm32_clock_control_on(const struct device *dev,
LL_APB2_GRP1_EnableClock(pclken->enr); LL_APB2_GRP1_EnableClock(pclken->enr);
break; break;
#endif #endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_EnableClock(pclken->enr);
break;
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ #if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X) defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP: case STM32_CLOCK_BUS_IOP:
@ -221,6 +226,11 @@ static inline int stm32_clock_control_off(const struct device *dev,
LL_APB2_GRP1_DisableClock(pclken->enr); LL_APB2_GRP1_DisableClock(pclken->enr);
break; break;
#endif #endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_APB3:
LL_APB3_GRP1_DisableClock(pclken->enr);
break;
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ #if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X) defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP: case STM32_CLOCK_BUS_IOP:
@ -252,13 +262,19 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
!defined (CONFIG_SOC_SERIES_STM32G0X) !defined (CONFIG_SOC_SERIES_STM32G0X)
uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER); uint32_t apb2_clock = get_bus_clock(ahb_clock, STM32_APB2_PRESCALER);
#endif #endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
uint32_t ahb3_clock = get_bus_clock(ahb_clock * STM32_CPU1_PRESCALER,
STM32_AHB3_PRESCALER);
#endif
ARG_UNUSED(clock); ARG_UNUSED(clock);
switch (pclken->bus) { switch (pclken->bus) {
case STM32_CLOCK_BUS_AHB1: case STM32_CLOCK_BUS_AHB1:
case STM32_CLOCK_BUS_AHB2: case STM32_CLOCK_BUS_AHB2:
#if !defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_AHB3: case STM32_CLOCK_BUS_AHB3:
#endif
#if defined (CONFIG_SOC_SERIES_STM32L0X) || \ #if defined (CONFIG_SOC_SERIES_STM32L0X) || \
defined (CONFIG_SOC_SERIES_STM32G0X) defined (CONFIG_SOC_SERIES_STM32G0X)
case STM32_CLOCK_BUS_IOP: case STM32_CLOCK_BUS_IOP:
@ -288,6 +304,13 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
case STM32_CLOCK_BUS_APB2: case STM32_CLOCK_BUS_APB2:
*rate = apb2_clock; *rate = apb2_clock;
break; break;
#endif
#if defined(CONFIG_SOC_SERIES_STM32WLX)
case STM32_CLOCK_BUS_AHB3:
case STM32_CLOCK_BUS_APB3:
/* AHB3 and APB3 share the same clock and prescaler. */
*rate = ahb3_clock;
break;
#endif #endif
default: default:
return -ENOTSUP; return -ENOTSUP;