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ITE: riscv: it8xxx2: declare gctrl dts node and registers

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Add general control(gctrl) node in dts, and declare gctrl registers

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit is contained in:
Tim Lin 2021-08-18 16:46:02 +08:00 • committed by Anas Nashif
commit 033eb55aca
2 changed files with 82 additions and 1 deletions
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6
dts/riscv/it8xxx2.dtsi
View file

@ -791,5 +791,11 @@
pinctrl-0 = <&pinctrl_pwm7>; /* GPA7 */ pinctrl-0 = <&pinctrl_pwm7>; /* GPA7 */
#pwm-cells = <2>; #pwm-cells = <2>;
}; };
gctrl: general-control@f02000 {
compatible = "ite,it8xxx2-gctrl";
reg = <0x00f02000 0x100>;
label = "GCTRL";
};
}; };
}; };

77
soc/riscv/riscv-ite/common/chip_chipregs.h
View file

@ -1,4 +1,4 @@
/* /*
* Copyright (c) 2020 ITE Corporation. All Rights Reserved. * Copyright (c) 2020 ITE Corporation. All Rights Reserved.
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@ -1945,4 +1945,79 @@ enum chip_pll_mode {
#define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27) #define IT83XX_SPI_RX_VLISR ECREG(IT83XX_SPI_BASE + 0x27)
#define IT83XX_SPI_RVLI BIT(0) #define IT83XX_SPI_RVLI BIT(0)
/**
*
* (20xxh) General Control (GCTRL) registers
*
*/
#ifndef __ASSEMBLER__
struct gctrl_it8xxx2_regs {
/* 0x00-0x01: Reserved1 */
volatile uint8_t reserved1[2];
/* 0x02: Chip Version */
volatile uint8_t GCTRL_ECHIPVER;
/* 0x03-0x05: Reserved2 */
volatile uint8_t reserved2[3];
/* 0x06: Reset Status */
volatile uint8_t GCTRL_RSTS;
/* 0x07-0x1B: Reserved3 */
volatile uint8_t reserved3[21];
/* 0x1C: Special Control 4 */
volatile uint8_t GCTRL_SPCTRL4;
/* 0x1D-0x1F: Reserved4 */
volatile uint8_t reserved4[3];
/* 0x20: Memory Controller Configuration 3 */
volatile uint8_t GCTRL_MCCR3;
/* 0x21: Reset Control 5 */
volatile uint8_t GCTRL_RSTC5;
/* 0x22-0x2F: Reserved5 */
volatile uint8_t reserved5[14];
/* 0x30: Memory Controller Configuration */
volatile uint8_t GCTRL_MCCR;
/* 0x31: Externel ILM/DLM Size */
volatile uint8_t GCTRL_EIDSR;
/* 0x32-0x36: Reserved6 */
volatile uint8_t reserved6[5];
/* 0x37: Eflash Protect Lock */
volatile uint8_t GCTRL_EPLR;
/* 0x38-0x40: Reserved7 */
volatile uint8_t reserved7[9];
/* 0x41: Interrupt Vector Table Base Address */
volatile uint8_t GCTRL_IVTBAR;
/* 0x42-0x43: Reserved8 */
volatile uint8_t reserved8[2];
/* 0x44: Memory Controller Configuration 2 */
volatile uint8_t GCTRL_MCCR2;
/* 0x45: Reserved9 */
volatile uint8_t reserved9;
/* 0x46: Pin Multi-function Enable 3 */
volatile uint8_t GCTRL_PMER3;
/* 0x47-0x4A: Reserved10 */
volatile uint8_t reserved10[4];
/* 0x4B: ETWD and UART Control */
volatile uint8_t GCTRL_ETWDUARTCR;
/* 0x4C: Wakeup MCU Control */
volatile uint8_t GCTRL_WMCR;
/* 0x4D-0x84: Reserved11 */
volatile uint8_t reserved11[56];
/* 0x85: Chip ID Byte 1 */
volatile uint8_t GCTRL_ECHIPID1;
/* 0x86: Chip ID Byte 2 */
volatile uint8_t GCTRL_ECHIPID2;
/* 0x87: Chip ID Byte 3 */
volatile uint8_t GCTRL_ECHIPID3;
};
#endif /* !__ASSEMBLER__ */
/* GCTRL register fields */
/* 0x06: Reset Status */
#define IT8XXX2_GCTRL_LRS (BIT(1) | BIT(0))
#define IT8XXX2_GCTRL_IWDTR BIT(1)
/* 0x1C: Special Control 4 */
#define IT8XXX2_GCTRL_LRSIWR BIT(2)
#define IT8XXX2_GCTRL_LRSIPWRSWTR BIT(1)
#define IT8XXX2_GCTRL_LRSIPGWR BIT(0)
/* 0x4B: ETWD and UART Control */
#define IT8XXX2_GCTRL_ETWD_HW_RST_EN BIT(0)
#endif /* CHIP_CHIPREGS_H */ #endif /* CHIP_CHIPREGS_H */