diff --git a/dts/arm/nxp/nxp_imx943_m33.dtsi b/dts/arm/nxp/nxp_imx943_m33.dtsi
new file mode 100644
index 00000000000..c9f76a3e165
--- /dev/null
+++ b/dts/arm/nxp/nxp_imx943_m33.dtsi
@@ -0,0 +1,188 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv8-m.dtsi>
+#include <zephyr/dt-bindings/clock/imx943_clock.h>
+#include <mem.h>
+#include <freq.h>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m33";
+			reg = <0>;
+			clock-frequency = <DT_FREQ_M(333)>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv8m-mpu";
+				reg = <0xe000ed90 0x40>;
+			};
+		};
+	};
+
+	reserved-memory {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		scmi_shmem0: memory@44721000 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x44721000 0x80>;
+		};
+	};
+
+	firmware {
+		scmi {
+			compatible = "arm,scmi";
+			shmem = <&scmi_shmem0>;
+			mboxes = <&mu8 0>;
+			mbox-names = "tx";
+
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				compatible = "arm,scmi-clock";
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+
+			scmi_iomuxc: protocol@19 {
+				compatible = "arm,scmi-pinctrl";
+				reg = <0x19>;
+
+				pinctrl: pinctrl {
+					compatible = "nxp,imx943-pinctrl", "nxp,imx93-pinctrl";
+				};
+			};
+		};
+	};
+
+	soc {
+		itcm: itcm@ffc0000 {
+			compatible = "nxp,imx-itcm";
+			reg = <0xffc0000 DT_SIZE_K(256)>;
+		};
+
+		dtcm: dtcm@20000000 {
+			compatible = "nxp,imx-dtcm";
+			reg = <0x20000000 DT_SIZE_K(256)>;
+		};
+
+		lpuart3: serial@42570000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42570000 DT_SIZE_K(64)>;
+			interrupts = <74 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART3>;
+			status = "disabled";
+		};
+
+		lpuart4: serial@42580000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42580000 DT_SIZE_K(64)>;
+			interrupts = <75 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART4>;
+			status = "disabled";
+		};
+
+		lpuart5: serial@42590000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42590000 DT_SIZE_K(64)>;
+			interrupts = <76 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART5>;
+			status = "disabled";
+		};
+
+		lpuart6: serial@425a0000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x425a0000 DT_SIZE_K(64)>;
+			interrupts = <77 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART6>;
+			status = "disabled";
+		};
+
+		lpuart7: serial@42690000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42690000 DT_SIZE_K(64)>;
+			interrupts = <78 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART7>;
+			status = "disabled";
+		};
+
+		lpuart8: serial@426a0000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x426a0000 DT_SIZE_K(64)>;
+			interrupts = <79 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART8>;
+			status = "disabled";
+		};
+
+		lpuart9: serial@42a50000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42a50000 DT_SIZE_K(64)>;
+			interrupts = <80 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART9>;
+			status = "disabled";
+		};
+
+		lpuart10: serial@42a60000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42a60000 DT_SIZE_K(64)>;
+			interrupts = <81 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART10>;
+			status = "disabled";
+		};
+
+		lpuart11: serial@42a70000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42a70000 DT_SIZE_K(64)>;
+			interrupts = <82 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART11>;
+			status = "disabled";
+		};
+
+		lpuart12: serial@42a80000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x42a80000 DT_SIZE_K(64)>;
+			interrupts = <83 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART12>;
+			status = "disabled";
+		};
+
+		lpuart1: serial@44380000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x44380000 DT_SIZE_K(64)>;
+			interrupts = <21 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART1>;
+			status = "disabled";
+		};
+
+		lpuart2: serial@44390000 {
+			compatible = "nxp,imx-lpuart", "nxp,lpuart";
+			reg = <0x44390000 DT_SIZE_K(64)>;
+			interrupts = <22 3>;
+			clocks = <&scmi_clk IMX943_CLK_LPUART2>;
+			status = "disabled";
+		};
+
+		mu8: mbox@44720000 {
+			compatible = "nxp,mbox-imx-mu";
+			reg = <0x44720000 DT_SIZE_K(64)>;
+			interrupts = <273 0>;
+			#mbox-cells = <1>;
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};